Patent Application
20230087499
The embodiments discussed herein relate to a semiconductor unit and a semiconductor device.
A semiconductor device includes power devices. The power devices are, for example, semiconductor chips, each of which includes an insulated gate bipolar transistor (IGBT) or a power metal-oxide-semiconductor field-effect transistor (MOSFET). The semiconductor device includes a ceramic circuit board on which the above semiconductor chips are disposed. The ceramic circuit board includes a ceramic plate and a plurality of circuit patterns formed on the front surface of the ceramic plate. Circuit patterns corresponding to an upper arm and circuit patterns corresponding to a lower arm are formed on a single ceramic circuit board. The semiconductor chips are suitably mounted on the plurality of circuit patterns. The control electrodes and main electrodes of the semiconductor chips are suitably and electrically connected to the circuit patterns on the ceramic circuit board by bonding wires. In this way, the semiconductor device realizes its desired function (see, for example, International Publication Pamphlet No. WO 2016/084622).
In the case of the above semiconductor device, the circuit patterns corresponding to the upper arm and the circuit patterns corresponding to the lower arm need to be formed on the ceramic plate, with a predetermined distance therebetween. In this way, it is possible to prevent short-circuiting between the circuit patterns corresponding to the upper arm and the circuit patterns corresponding to the lower arm. However, because a predetermined distance needs to be maintained between these sets of circuit patterns, the mounting areas of the circuit patterns on the ceramic plate are reduced, and downsizing of the ceramic plate becomes difficult. Thus, downsizing of the semiconductor device also becomes difficult.
According to an aspect, there is provided a semiconductor unit, including: a plurality of semiconductor chips, each of which has an output electrode and a control electrode on a front surface thereof and an input electrode on a rear surface thereof; and an insulated circuit board, including an insulating plate having, in a plan view of the semiconductor unit, a rectangular shape surrounded by a first side and a second side which are opposite to each other and a third side and a fourth side which are perpendicular to the first side and the second side and which are opposite to each other, an output circuit pattern provided on a front surface of the insulating plate, and an input circuit pattern which is provided on the front surface of the insulating plate and to which the rear surfaces of the plurality of semiconductor chips are bonded, wherein the output circuit pattern and the input circuit pattern each extend from the third side to the fourth side, and the input circuit pattern and the output circuit pattern are disposed in this order side by side in a main current direction that is a direction from the first side toward the second side, and wherein the plurality of semiconductor chips are bonded to the input circuit pattern in an area that extends from the third side to the fourth side and includes a center of the third and fourth sides.
The object and advantages of the invention will be realized and attained by means of the elements and combinations particularly pointed out in the claims.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are not restrictive of the invention.
Hereinafter, embodiments will be described with reference to the accompanying drawings. In the following description, regarding a semiconductor unit 10 in
Hereinafter, a semiconductor device according to a first embodiment will be described with reference to
As will be described below, the semiconductor device includes two semiconductor units 10, one of which is illustrated in
The individual semiconductor chip 30 is made of silicon or silicon carbide as its main component. The individual semiconductor chip 30 includes a reverse-conducting (RC)-IGBT as a switching element. The RC-IGBT is structured by connecting an IGBT and a free-wheeling diode (FWD) in reverse-parallel to each other on a single chip. The individual semiconductor chip 30 includes a control electrode 31 (a gate electrode) and an output electrode 32 (the emitter electrode of the IGBT portion and the cathode electrode of the FWD portion) on its front surface. The individual semiconductor chip 30 has a rectangular shape in plan view. The control electrode 31 of the individual semiconductor chip 30 is located at a center portion of one side of the front surface of this semiconductor chip 30. The output electrode 32 of the individual semiconductor chip 30 is formed in an area of the front surface of this semiconductor chip 30, the area being other than the area where the control electrode 31 is formed. In addition, the individual semiconductor chip 30 includes an input electrode not illustrated (the collector electrode of the IGBT portion and the anode electrode of the FWD portion) on its rear surface. The control electrodes 31 of the four semiconductor chips 30 are located in an inner area of the semiconductor unit 10, and one of the control electrodes 31 faces other control electrodes 31. In addition, the rear surfaces of the four semiconductor chips 30 are bonded to the circuit pattern 23a. The number of semiconductor chips 30 and the locations of the semiconductor chips 30 are not limited to those described above.
The ceramic circuit board 20 has a rectangular shape in plan view. The ceramic circuit board 20 has a ceramic plate 21 and a metal plate 22, which is formed on the rear surface of the ceramic plate 21. In addition, the ceramic circuit board 20 has circuit patterns 23a to 23f on the front surface of the ceramic plate 21. The ceramic plate 21 and the metal plate 22 each have a rectangular shape in plan view. In addition, the ceramic plate 21 and the metal plate 22 may be formed to have rounded or chamfered corners. In plan view, the metal plate 22 is smaller than the ceramic plate 21 and is formed inside the ceramic plate 21.
The ceramic plate 21 has, in plan view, a rectangular shape surrounded by first and second sides 21a and 21b which are located in opposite directions (the ±X directions) and third and fourth sides 21c and 21d which are perpendicular to the first and second sides 21a and 21b and which are located in opposite directions (the ±Y directions). The ceramic plate 21 may have, in plan view, a rectangular shape surrounded by the first and second sides 21a and 21b formed as its long sides and the third and fourth sides 21c and 21d formed as its short sides. When this ceramic plate 21 is used, the direction (the +X direction) from the first side 21a near which input terminal areas 23a2 to be described below are formed to the second side 21b near which output terminal areas 23b2 to be described below are formed will be referred to as a main current direction D1. The ceramic plate 21 is made of ceramic material having good thermal conductivity as its main component. For example, this ceramic material constituting the ceramic plate 21 contains, as its main component, a composite material of aluminum oxide and zirconium oxide added thereto. Alternatively, the ceramic material contains material containing silicon nitride as its main component. The ceramic plate 21 has a thickness between 0.2 mm and 2.5 mm, inclusive.
The metal plate 22 is made of metal material having excellent thermal conductivity as its main component. Examples of the metal material include aluminum, iron, silver, copper, and an alloy containing at least one of these kinds. The thickness of the metal plate 22 is between 0.1 mm and 5.0 mm, inclusive. The surface of the metal plate 22 may be plated to improve its corrosion resistance. Examples of the plating material include nickel, a nickel-phosphorus alloy, and a nickel-boron alloy.
The circuit patterns 23a to 23f are each made of metal material having excellent electrical conductivity as its main component. Examples of the metal material include silver, copper, nickel, and an alloy containing at least one of these kinds. In addition, the circuit patterns 23a to 23f each have a thickness between 0.1 mm and 5.0 mm, inclusive. The surface of each of the circuit patterns 23a to 23f may be plated to improve its corrosion resistance. Examples of the plating material include nickel, a nickel-phosphorus alloy, and a nickel-boron alloy. The circuit patterns 23a to 23f are obtained by forming a metal layer on the front surface of the ceramic plate 21 and performing etching or the like on this metal layer. Alternatively, the circuit patterns 23a to 23f may first be cut out from a metal layer and may next be fixed to the front surface of the ceramic plate 21 by applying pressure. The circuit patterns 23a to 23f illustrated in
For example, a direct copper bonding (DCB) substrate or an active metal brazed (AMB) substrate may be used as the ceramic circuit board 20 having the above structure. The ceramic circuit board 20 transfers the heat generated by the semiconductor chips 30 to the outside via the circuit pattern 23a, the ceramic plate 21, and the metal plate 22.
Next, each of the circuit patterns 23a to 23f will be described in detail. The circuit pattern 23a (an input circuit pattern) is mechanically and electrically connected to the input electrodes formed on the rear surfaces of the semiconductor chips 30 via solder. The circuit pattern 23a has an approximately rectangular shape and includes a concave portion 23a1 in a lower part in
The circuit pattern 23a is formed in an area including a center line (the dashed-dotted line X-X) perpendicular to the main current direction D1. The semiconductor chips 30 are disposed in the area including the center line (the dashed-dotted line X-X). In
The circuit pattern 23b (an output circuit pattern) is mechanically and electrically connected to the output electrodes 32 of the semiconductor chips 30 by main current wires 41 that extend in the main current direction D1. The circuit pattern 23b includes the two output terminal areas 23b2 near the circuit pattern 23f.
These circuit patterns 23a and 23b are formed to extend from the third side 21c to the fourth side 21d of the ceramic plate 21. In addition, the circuit patterns 23a and 23b are formed side by side in this order in the main current direction D1. That is, the circuit patterns 23a and 23b are formed adjacent to each other in the ±X directions, and no other circuit patterns are formed therebetween. In addition, end portions of the circuit patterns 23a and 23b, the end portions being located in the -Y direction, are formed adjacent to the third side 21c of the ceramic plate 21, and no other circuit patterns are formed therebetween. End portions of the circuit patterns 23a and 23b, the end portions being located in the +Y direction, are formed adjacent to and face the fourth side 21d of the ceramic plate 21, and no circuit patterns are formed therebetween. Thus, a main current that flows to the input terminal areas 23a2 of the ceramic circuit board 20 flows in the main current direction D1 and is output from the output terminal areas 23b2.
The gap between the circuit patterns 23a and 23b, the gap between the -Y direction end portions of the circuit patterns 23a and 23b and the third side 21c of the ceramic plate 21, and the gap between the +Y direction end portions of the circuit patterns 23a and 23b and the fourth side 21d of the ceramic plate 21 may each be formed based on a predetermined insulating distance. For example, the gap formed based on a predetermined insulating distance may be between 0.5 mm and 4.0 mm, inclusive.
In addition, for example, each of the ±Y direction end portions of the circuit pattern 23b (the output circuit pattern) may be formed adjacent to a corresponding one of the third and fourth sides 21c and 21d. In the area where the semiconductor chips 30 are disposed, each of the ±Y direction end portions of the circuit pattern 23a (the input circuit pattern) may be formed adjacent to a corresponding one of the third and fourth sides 21c and 21d. In contrast, the circuit pattern 23c or 23d, e.g., a control circuit or a sense circuit to be described below, may be formed between one of the end portions of the area where the input terminal areas 23a2 are disposed, the end portions being located in the ±Y direction, and the third side 21c or fourth side 21d.
The input terminal areas 23a2 are disposed near the first side 21a of the ceramic circuit board 20, and the output terminal areas 23b2 are disposed near the second side 21b of the ceramic circuit board 20. That is, the main current direction D1 is the direction from the input terminal areas 23a2 to the output terminal areas 23b2. The input terminal areas 23a2 and the output terminal areas 23b2 are equally distanced from the center line (the dashed-dotted line X-X) of the ceramic circuit board 20, the center line being perpendicular to the main current direction D1. In addition, the input terminal areas 23a2 and the output terminal areas 23b2 are approximately equally distanced from the first and second sides 21a and 21b, respectively.
The circuit pattern 23c (a first control circuit pattern) is electrically connected to the control electrodes 31 of the semiconductor chips 30. The circuit pattern 23c is formed outside and adjacent to the circuit pattern 23a (on the side opposite to the main current direction D1). In other words, the circuit pattern 23c is disposed closer to the first side 21a than is the circuit patten 23a. The (±Y direction) end portions of the circuit pattern 23c are formed to correspond to the width of the area where the input terminal areas 23a2 of the circuit pattern 23a are formed. That is, there is a gap between the (-Y direction) end portion of the circuit pattern 23c and the third side 21c of the ceramic plate 21, and there is a gap between the (+Y direction) end portion of the circuit pattern 23c and the fourth side 21d of the ceramic plate 21. In addition, the circuit pattern 23c includes the contact area 23c1 at a location corresponding to the midpoint between the third and fourth sides 21c and 21d of the ceramic plate 21. This contact area 23c1 is located inside the concave portion 23a1 of the circuit pattern 23a. The circuit pattern 23c (the contact area 23c1) is mechanically and electrically connected to the control electrodes 31 of the semiconductor chips 30, the control electrodes 31 being located in the inner area of the semiconductor unit 10, by control wires 42 (control wiring members) that extend in the main current direction D1.
The circuit pattern 23f (a second control circuit pattern) may be electrically connected to the control electrodes 31 of the semiconductor chips 30. The circuit pattern 23f has a linear shape and is formed outside and adjacent to the circuit pattern 23b (in the main current direction D1). The (±Y direction) end portions of the circuit pattern 23f are formed to correspond to the (±Y direction) end portions of the circuit pattern 23b.
These circuit patterns 23c and 23f are formed symmetrically with respect to the center line (the dashed-dotted line X-X) of the ceramic circuit board 20, the center line being perpendicular to the main current direction D1. In addition, the circuit patterns 23c and 23f are equally distanced from the first and second sides 21a and 21b of the ceramic plate 21, respectively.
The circuit pattern 23d (a first sense circuit pattern) is electrically connected to the output electrodes 32 of the semiconductor chips 30. The circuit pattern 23d is formed near the circuit pattern 23a on the side opposite to the main current direction D1. The circuit pattern 23d is formed outside and adjacent to the circuit pattern 23c (in the -X direction). In other words, the circuit pattern 23d is closer to the first side 21a than is the circuit pattern 23c. That is, according to the first embodiment, the circuit pattern 23d has a U shape in plan view. Specifically, the circuit pattern 23d is formed along the area in which the input terminal areas 23a2 of the circuit pattern 23a are set, the (±Y direction) end portions of the circuit pattern 23c, and a side of the circuit pattern 23c on the side opposite to the main current direction D1. Therefore, the circuit pattern 23d surrounds the area in which the input terminal areas 23a2 of the circuit pattern 23a are set and the circuit pattern 23c. The circuit pattern 23d is mechanically and electrically connected to the output electrodes 32 of the semiconductor chips 30 by sense wires 46 extending in the main current direction D1.
The circuit pattern 23e (a second sense circuit pattern) may be electrically connected to the output electrodes 32 of the semiconductor chips 30. The circuit pattern 23e has a linear shape and is formed outside and adjacent to the circuit pattern 23f (in the main current direction D1). In other words, the circuit pattern 23e is closer to the second side 21b than is the circuit pattern 23f. The (±Y direction) end portions of the circuit pattern 23e are formed to correspond to the (±Y direction) end portions of the circuit pattern 23f.
In addition, these circuit patterns 23d and 23e are equally distanced from the center line (the dashed-dotted line X-X) of the ceramic circuit board 20, the center line being perpendicular to the main current direction D1. In addition, the circuit patterns 23d and 23e are equally distanced from the first and second sides 21a and 21b of the ceramic plate 21, respectively.
The main current wires 41, the control wires 42, and the sense wires 46 are each made of metal material having excellent electrical conductivity as its main component. Examples of the metal material include gold, silver, copper, aluminum, and an alloy containing at least one of these kinds. The control wires 42 and the sense wires 46 may have a diameter smaller than that of the main current wires 41. In this way, the corresponding bonding areas are reduced, and wiring is easily achieved in fine portions. The control wires 42 and the sense wires 46 each have a diameter between 50 µm and 400 µm, inclusive, and the main current wires 41 each have a diameter between 300 µm and 600 µm, inclusive, for example. Control coupling wires 44a and 44b and sense coupling wires 45a and 45b to be described below are also made of the same material as that of the control wires 42 and the sense wires 46. The control coupling wires 44a and 44b and the sense coupling wires 45a and 45b may have the same diameter as that of the control wires 42 and the sense wires 46. This diameter may be smaller than that of the main current wires 41.
The control wires 42 and the sense wires 46 may be formed to extend as illustrated in
In this way, the semiconductor chips 30 and the circuit patterns 23a, 23b, 23c, and 23d are connected to each other by the main current wires 41, the control wires 42, and the sense wires 46. By connecting the above components of the semiconductor unit 10, an arm portion is structured. This arm portion functions as an upper arm or a lower arm, depending on the direction of the arm portion (the main current direction D1), which will be described in detail below.
Next, a semiconductor device including the semiconductor unit 10 as described above will be described with reference to
A semiconductor device 1 includes two semiconductor units 10a and 10b. The semiconductor unit 10a is equivalent to the semiconductor unit 10 and functions as an upper arm. While the semiconductor unit 10b is also equivalent to the semiconductor unit 10, the main current direction D1 thereof is opposite to that of the semiconductor unit 10a, and the semiconductor unit 10b functions as a lower arm. Thus, while the semiconductor units 10a and 10b each include the same components as those of the semiconductor unit 10, one of the semiconductor units 10a and 10b is disposed in the opposite direction to the other.
In the case of the semiconductor device 1, the circuit pattern 23b of the semiconductor unit 10a and the circuit pattern 23a of the semiconductor unit 10b may be mechanically and electrically connected to each other by a main circuit coupling wire (not illustrated).
In addition, in the case of the semiconductor device 1, the circuit pattern 23c of the semiconductor unit 10a and the circuit pattern 23f of the semiconductor unit 10b are mechanically and electrically connected to each other by the control coupling wire 44a. The circuit pattern 23f of the semiconductor unit 10a and the circuit pattern 23c of the semiconductor unit 10b are mechanically and electrically connected to each other by the control coupling wire 44b.
In addition, in the case of the semiconductor device 1, the circuit pattern 23d of the semiconductor unit 10a and the circuit pattern 23e of the semiconductor unit 10b are mechanically and electrically connected to each other by the sense coupling wire 45a. The circuit pattern 23e of the semiconductor unit 10a and the circuit pattern 23d of the semiconductor unit 10b are mechanically and electrically connected to each other by the sense coupling wire 45b.
In addition, the semiconductor device 1 includes busbars 50a and 50b. The busbars 50a and 50b are each made of metal material having excellent electrical conductivity as its main component. Examples of the metal material include silver, copper, nickel, and an alloy containing at least one of these kinds. The surface of each of the busbars 50a and 50b may be plated to improve its corrosion resistance. Examples of the plating material include nickel, a nickel-phosphorus alloy, and a nickel-boron alloy.
The busbar 50a includes leg portions 51a and a wiring portion 52a. The leg portions 51a are bonded to the input terminal areas 23a2 of the circuit pattern 23a of the semiconductor unit 10a. This bonding of the leg portions 51a is performed by soldering or ultrasonic bonding, for example. The wiring portion 52a is mechanically connected to the leg portions 51a. The wiring portion 52a and the leg portions 51a may be formed integrally or may be bonded to each other by welding, for example. In addition, the wiring portion 52a is perpendicular to the main current direction D1 and extends in the ±Y directions in
The busbar 50b also includes leg portions 51b and a wiring portion 52b. The leg portions 51b are bonded to the output terminal areas 23b2 of the circuit pattern 23b of the semiconductor unit 10b. This bonding of the leg portions 51b is also performed by soldering or ultrasonic bonding, for example. The wiring portion 52b is mechanically connected to the leg portions 51b. The wiring portion 52b and the leg portions 51b may be formed integrally or may be bonded to each other by welding, for example. In addition, the wiring portion 52b is perpendicular to the main current direction D1 and extends in the ±Y directions in
A busbar 50c also includes leg portions 51c and a wiring portion 52c. The leg portions 51c are bonded to the output terminal areas 23b2 of the circuit pattern 23b of the semiconductor unit 10a and to the input terminal areas 23a2 of the circuit pattern 23a of the semiconductor unit 10b. This bonding of the leg portions 51c is also performed by soldering or ultrasonic bonding, for example. The wiring portion 52c is mechanically connected to the leg portions 51c. The wiring portion 52c and the leg portions 51c may be formed integrally or may be bonded to each other by welding, for example. In addition, the wiring portion 52c is perpendicular to the main current direction D1 and extends in the ±Y directions in
The semiconductor device 1 constitutes a half-bridge circuit illustrated in
A wiring extends from the connection point C1 to the outside of the semiconductor device 1 via the busbar 50a and is connected to the high-potential terminal (P) of the external power supply. A wiring extends from the connection point E2 to the outside of the semiconductor device 1 via the busbar 50b and is connected to the low-potential terminal (N) of the external power supply. In addition, a wiring extends from the connection point E1C2 to the outside of the semiconductor device 1 via the busbar 50c and is connected to the terminal (O) of the load. The semiconductor units 10 consequently function as an inverter.
The semiconductor device 1 structured by connecting the semiconductor units 10a and 10b is disposed on a heat dissipation board via solder or silver solder, for example. The heat dissipation board may be a flat plate having a rectangular shape in plan view. The heat dissipation board is made of metal material having excellent thermal conductivity as its main component. Examples of the metal material include aluminum, iron, silver, copper, and an alloy containing at least one of these kinds. Nickel may be formed on the surface of the heat dissipation board by plating or the like, to improve the corrosion resistance. Specifically, examples of the plating material include not only nickel but also a nickel-phosphorus alloy and a nickel-boron alloy. For example, attachment holes are suitably formed in the heat dissipation board as described above, and these attachment holes are used to attach the semiconductor device 1 to an external device.
In addition, a cooling unit may be attached to the rear surface of the heat dissipation board of the semiconductor device 1 via thermal grease. The thermal grease is, for example, silicone in which filler of metal oxide is mixed. This cooling unit is also made of material having excellent thermal conductivity as its main component, and as needed, the surface of the cooling unit may be plated. The cooling unit is, for example, a heat sink having a plurality of fins or a water-cooled cooling device. The heat dissipation board may be formed integrally with such a cooling unit as described above.
The semiconductor device 1 may be sealed with sealing material. The sealing material may seal the front surface of the ceramic circuit board 20, the semiconductor chips 30, and the wires such as the main current wires 41, the control wires 42, and the sense wires 46. The rear surface of the heat dissipation board may be exposed to the outside from the sealing material. The sealing material is thermosetting resin such as epoxy resin or silicone gel. The sealing material may further contain filler.
Alternatively, after stored in a case (not illustrated), the semiconductor device 1 may be sealed with sealing material. As needed, the case may be provided with wiring members. Examples of the wiring members include a lead frame and the busbars 50a, 50b, and 50c. In this case, the control terminals and sense terminals included in the lead frame and the external terminals included in the busbars 50a, 50b, and 50c are exposed to the outside of the case. The individual control terminal receives a control signal, and the individual sense terminal outputs a measured signal. The individual external terminal receives and outputs a predetermined current from and to the outside. The case as described above is made of thermoplastic resin as its main component. Examples of this resin include polyphenylene sulfide resin, polybutylene terephthalate resin, polybutylene succinate resin, polyamide resin, and acrylonitrile butadiene styrene resin.
Next, in comparison to the semiconductor unit 10, a semiconductor unit according to a reference example will be described with reference to
The semiconductor chips 130 each include a switching element, and the semiconductor chips 131 each include a diode element. The individual semiconductor chip 130 as a switching element includes an input electrode on its rear surface and a control electrode and an output electrode on its front surface. The individual semiconductor chip 131 as a diode element includes an output electrode on its rear surface and an input electrode on its front surface.
The circuit pattern 230a constitutes a pattern including the connection point E1C2 in
The circuit pattern 230b constitutes a pattern including the connection point C1 of the upper arm A in
The circuit pattern 230c constitutes a pattern including the connection point E2 of the lower arm in
The circuit pattern 230d constitutes a control pattern of the upper arm A. The circuit pattern 230d is connected to the control electrodes of corresponding semiconductor chips 130 via control wires 42. The circuit pattern 230d is formed near the second side 21b of the ceramic plate 21 in
The circuit pattern 230g constitutes a control pattern of the lower arm B. The circuit pattern 230g is connected to the control electrodes of corresponding semiconductor chips 130 on the circuit pattern 230a via control wires 42. The circuit pattern 230g is formed near the first side 21a of the ceramic plate 21 in
In addition, the circuit patterns 230e and 230f each constitute a sense pattern. The circuit pattern 230f is disposed near the first side 21a of the ceramic plate 21, and the circuit pattern 230e is disposed near the second side 21b, which is located in the opposite direction to the first side 21a near which the circuit pattern 230f is located. The circuit patterns 230e and 230f are each mechanically and electrically connected to the output electrode of a corresponding semiconductor chip 130 via a sense wire 46.
In the case of this semiconductor unit 100, a gap G needs to be maintained between the circuit pattern 230b of the upper arm A and the circuit pattern 230a of the lower arm B. In this way, short-circuiting between the circuit pattern 230b and the circuit pattern 230a is prevented. That is, in the case of the semiconductor unit 100, since the gap G needs to be maintained, the area of the ceramic plate 21 is increased. Thus, it is difficult to achieve downsizing of the ceramic plate 21, and therefore, downsizing of the semiconductor unit 100 and a semiconductor device including the semiconductor unit 100 become difficult, too.
In contrast, the semiconductor unit 10 includes the semiconductor chips 30 and the ceramic circuit board 20. The individual semiconductor chip 30 has the output electrode 32 and the control electrode 31 on its front surface and has the input electrode on its rear surface. The ceramic circuit board 20 includes the ceramic plate 21 and the circuit patterns 23b and 23a. The ceramic plate 21 has, in plan view, a rectangular shape surrounded by the first and second sides 21a and 21b which are located in opposite directions and the third and fourth sides 21c and 21d which are perpendicular to the first and second sides 21a and 21b and which are located in opposite directions. The circuit pattern 23b is formed on the front surface of the ceramic plate 21. The circuit pattern 23a is formed on the front surface of the ceramic plate 21, and the rear surfaces of the semiconductor chips 30 are bonded to the circuit pattern 23a. In addition, the circuit pattern 23b and the circuit pattern 23a are each formed from the third side 21c to the fourth side 21d and are formed side by side in the main current direction D1 from the first side 21a to the second side 21b.
By disposing the two semiconductor units 10a and 10b, each of which corresponds to the semiconductor unit 10, side by side such that their respective main current directions D1 are opposite to each other, and by connecting the two semiconductor units 10a and 10b with the wires as described above, the semiconductor device 1 is obtained. In this way, the semiconductor device 1 is easily structured by combining the semiconductor units 10 oriented in different directions. Other than the above case, by combining semiconductor units 10 in various ways, various semiconductor devices 1 are structured.
In addition, in the case of the semiconductor device 1, since the semiconductor units 10a and 10b include their respective ceramic circuit boards 20, the insulating property between the semiconductor units 10a and 10b is maintained, and short-circuiting between the semiconductor units 10a and 10b is prevented. Thus, the expansion of the area of the individual ceramic plate 21 is prevented, and expansion of the individual semiconductor unit 10 (the semiconductor unit 10a or 10b) is prevented. In addition, downsizing of the semiconductor unit 10 is achieved, and downsizing of the semiconductor device 1 is achieved.
Hereinafter, variations of the semiconductor device obtained by combining semiconductor units 10 in various ways will be described.
Variation 1 in which two sets of semiconductor units 10a and 10b illustrated in
As illustrated in
In addition, in the case of the semiconductor device 1a, the semiconductor units 10a and 10a (Y1 and Y3) are connected to each other by a busbar 50a, and the semiconductor units 10b and 10b (Y2 and Y4) are connected to each other by a busbar 50b. In addition, the semiconductor units 10a, 10b, 10a, and 10b (Y1, Y2, Y3, and Y4) are connected to each other by a busbar 50c. The busbars 50a, 50b, and 50c connect the semiconductor units 10a and 10b in the same way as in
Leg portions 51a of the busbar 50a are bonded to the input terminal areas 23a2 of the circuit patterns 23a of the semiconductor units 10a and 10a (Y1 and Y3). A wiring portion 52a is mechanically connected to the leg portions 51a. In addition, the wiring portion 52a is perpendicular to the main current direction D1 and extends in the ±Y directions in
Leg portions 51b of the busbar 50b are also bonded to the output terminal areas 23b2 of the circuit patterns 23b of the semiconductor units 10b and 10b (Y2 and Y4). A wiring portion 52b is mechanically connected to the leg portions 51b. In addition, the wiring portion 52b is perpendicular to the main current direction D1 and extends in the ±Y directions in
Leg portions 51c of the busbar 50c are also bonded to the output terminal areas 23b2 of the circuit patterns 23b of the semiconductor units 10a (Y1 and Y3) and to the input terminal areas 23a2 of the circuit patterns 23a of the semiconductor units 10b (Y2 and Y4). This bonding of the leg portions 51c is also performed by soldering or ultrasonic bonding, for example. In addition, a wiring portion 52c is perpendicular to the main current direction D1 and extends in the ±Y directions in
The semiconductor device 1a according to variation 1 includes two sets of semiconductor units 10a and 10b connected to each other. As needed, more sets of semiconductor units 10a and 10b may be connected in the Y direction in
Variation 2 in which semiconductor units 10a and 10b are connected to the outside of the semiconductor units 10a and 10b illustrated in
As illustrated in
In addition, in the case of the semiconductor device 1b, the semiconductor units 10a and 10a (Y1 and Y2) are connected to each other by a busbar 50a, and the semiconductor units 10b and 10b (Y3 and Y4) are connected to each other by a busbar 50b. In addition, the semiconductor units 10a, 10a, 10b, and 10b (Y1, Y2, Y3, and Y4) are connected to each other by a busbar 50c.
Leg portions 51a of the busbar 50a are bonded to the input terminal areas 23a2 of the circuit patterns 23a of the semiconductor units 10a and 10a (Y1 and Y2). A wiring portion 52a is mechanically connected to the leg portions 51a. In addition, the wiring portion 52a is perpendicular to the main current direction D1 and extends in the ±Y directions in
Leg portions 51b of the busbar 50b are bonded to the output terminal areas 23b2 of the circuit pattern 23b of the semiconductor units 10b and 10b (Y3 and Y4). A wiring portion 52b is mechanically connected to the leg portions 51b. In addition, the wiring portion 52b is perpendicular to the main current direction D1 and extends in the ±Y directions in
Leg portions 51c of the busbar 50c are bonded to the output terminal areas 23b2 of the circuit patterns 23b of the semiconductor units 10a (Y1 and Y2) and to the input terminal areas 23a2 of the circuit patterns 23a of the semiconductor units 10b (Y3 and Y4). This bonding of the leg portions 51c also is performed by soldering or ultrasonic bonding, for example. In addition, a wiring portion 52c is perpendicular to the main current direction D1 and extends in the ±Y directions in
The semiconductor device 1b according to variation 2 is formed by connecting a semiconductor unit 10a to a set of semiconductor units 10a and 10b in the -Y direction in
Variation 3 in which the semiconductor units 10a and 10b illustrated in
As illustrated in
As is the case with the semiconductor units 10a and 10b illustrated in
The semiconductor units 10a and 10b of the semiconductor device 1c may be structured without the sense coupling circuit patterns 23e and the gate coupling circuit patterns 23f. In this case, the control coupling wires 44a and 44b and the sense coupling wires 45a and 45b are not needed, either. In this way, the individual board area is further reduced, and the size of the semiconductor device 1c is further reduced.
In the case of the semiconductor device 1c, for example, the input terminal areas 23a2 of the semiconductor unit 10a are structured to correspond to the connection point C1 in
Alternatively, for example, the input terminal areas 23a2 of the semiconductor units 10a and 10b are structured to correspond to the connection point C1 in
The semiconductor device 1c is obtained by connecting a set of semiconductor units 10a and 10b vertically. As needed, a plurality of sets of semiconductor units 10a and 10b may be connected to each other in the Y direction in
For example, the semiconductor device 1d illustrated in
In addition, in the case of the semiconductor device 1d, the semiconductor units 10a and 10a (X11 and X21) are connected to each other by busbars 50a and 50c1. In addition, the semiconductor units 10b and 10b (X12 and X22) are connected to each other by busbars 50b and 50c2.
Leg portions 51a of the busbar 50a are bonded to the input terminal areas 23a2 of the circuit patterns 23a of the semiconductor units 10a (X11 and X21). A wiring portion 52a is mechanically connected to the leg portions 51a. In addition, the wiring portion 52a is perpendicular to the main current direction D1 and extends in the ±Y directions in
Leg portions 51b of the busbar 50b are bonded to the output terminal areas 23b2 of the circuit patterns 23b of the semiconductor units 10b (X12 and X22). A wiring portion 52b is mechanically connected to the leg portions 51b. In addition, the wiring portion 52b is perpendicular to the main current direction D1 and extends in the ±Y directions in
The busbar 50c1 includes leg portions 51c1 and a wiring portion 52c1. The leg portions 51c1 are bonded to the output terminal areas 23b2 of the circuit patterns 23b of the semiconductor units 10a (X11 and X21). This bonding of the leg portions 51c is also performed by soldering or ultrasonic bonding, for example. In addition, the wiring portion 52c1 is perpendicular to the main current direction D1 and extends in the ±Y directions in
The busbar 50c2 includes leg portions 51c2 and a wiring portion 52c2. The leg portions 51c2 are bonded to the input terminal areas 23a2 of the circuit patterns 23a of the semiconductor units 10b (X12 and X22). This bonding of the leg portions 51c2 is also performed by soldering or ultrasonic bonding, for example. In addition, the wiring portion 52c2 is perpendicular to the main current direction D1 and extends in the ±Y directions in
Variation 4 in which the semiconductor units 10 of the semiconductor device 1c illustrated in
As illustrated in
As is the case with the semiconductor units 10a and 10b illustrated in
As illustrated in
As is the case with the semiconductor units 10b and 10a illustrated in
The semiconductor units 10a and 10b of the semiconductor devices 1e1 and 1e2 may be structured without the sense coupling circuit pattern 23e and the gate coupling circuit pattern 23f. In this case, the control coupling wires 44a and 44b and the sense coupling wires 45a and 45b are not needed, either. In this way, the individual board area is further reduced, and the sizes of the semiconductor devices 1e1 and 1e2 are further reduced.
In addition, in the case of each of the semiconductor devices 1e1 and 1e2, for example, the input terminal areas 23a2 of the semiconductor unit 10a are structured to correspond to the connection point C1 in
Alternatively, for example, the input terminal areas 23a2 of the semiconductor units 10a and 10b are structured to correspond to the connection point C1 in
The semiconductor device 1e1 or 1e2 may be connected in plurality in the Y direction in
In addition, in the case of the semiconductor device 1e, a busbar 50a is connected to the semiconductor units 10a and 10b (X11 and X12) located in the -Y direction, as illustrated in
Leg portions 51a of the busbar 50a are bonded to the input terminal areas 23a2 of the circuit patterns 23a of the semiconductor units 10a and 10b (X11 and X12) located in the -Y direction. A wiring portion 52a is mechanically connected to the leg portions 51a. However, the wiring portion 52a is formed in a U shape, depending on the locations of the semiconductor units 10a and 10b.
Leg portions 51b of the busbar 50b are bonded to the output terminal areas 23b2 of the circuit patterns 23b of the semiconductor units 10b and 10a (X21 and X22) located in the +Y direction. A wiring portion 52b is mechanically connected to the leg portions 51b. This wiring portion 52b is also formed in a U shape, depending on the locations of the semiconductor units 10b and 10a.
Leg portions 51c1 of the busbar 50c1 are bonded to the output terminal areas 23b2 of the circuit pattern 23b of the semiconductor unit 10a (X11) and to the input terminal area 23a2 of the circuit patterns 23a of the semiconductor unit 10b (X21), the semiconductor unit 10a (X11) and the semiconductor unit 10b (X21) being located in the +X direction. This bonding of the leg portions 51c is also performed by soldering or ultrasonic bonding, for example. In addition, a wiring portion 52c1 is perpendicular to the main current direction D1 and extends in the ±Y directions in
Leg portions 51c2 of the busbar 50c2 are bonded to the output terminal areas 23b2 of the circuit pattern 23b of the semiconductor unit 10b (X12) and to the input terminal areas 23a2 of the circuit pattern 23a of the semiconductor unit 10a (X22), the semiconductor unit 10b (X12) and the semiconductor unit 10a (X22) being located in the -X direction. This bonding of the leg portions 51c2 is also performed by soldering or ultrasonic bonding, for example. In addition, a wiring portion 52c2 is perpendicular to the main current direction D1 and extends in the ±Y directions in
Variation 5 in which the semiconductor unit 10 illustrated in
The semiconductor device 1f includes the two semiconductor units 10a and 10a whose main current directions D1 match the +X direction. That is, the semiconductor device 1f is obtained by disposing the semiconductor units 10a and 10a (Y1 and Y2) in a line in the Y direction and by mechanically and electrically connecting the semiconductor units 10a and 10a (Y1 and Y2) to each other. That is, the semiconductor unit 10a (Y2) is disposed adjacent to the semiconductor unit 10a (Y1) in the direction (+Y direction) perpendicular to the main current direction D1.
As is the case with the semiconductor units 10a and 10a (Y1 and Y2) illustrated in
The semiconductor device 1f as described above is obtained by the semiconductor units 10a, each of which has the same main current direction D1. The number of semiconductor units 10a included in the semiconductor device 1f is not limited to 2. One semiconductor unit 10a or three or more semiconductor units 10a may be included in the semiconductor device 1f.
While the main current direction D1 of the semiconductor device 1f matches the +X direction, the main current direction D1 of the semiconductor device 1g matches the -X direction, as illustrated in
The semiconductor device 1g as described above is obtained by the semiconductor units 10b, each of which has the same main current direction D1. In addition, the input and output of the semiconductor device 1g are opposite to those of the semiconductor device 1f. The number of semiconductor units 10b included in the semiconductor device 1g is not limited to 2. One semiconductor unit 10b or three or more semiconductor units 10b may be included in the semiconductor device 1g. The semiconductor units 10a and 10b of the semiconductor devices 1f and 1g may be structured without the sense coupling circuit patterns 23e and the gate coupling circuit patterns 23f. In this case, the control coupling wires 44a and 44b and the sense coupling wires 45a and 45b are not needed, either. In this way, the individual board area is further reduced, and the sizes of the semiconductor devices 1f and 1g are further reduced.
A second embodiment in which two kinds of semiconductor chips, which are switching elements and diode elements, are used in place of the RC-IGBTs as the semiconductor chips according to the first embodiment will be described with reference to
The semiconductor chips 30a and 30b are disposed in two columns in the -X direction on the circuit pattern 23a of the semiconductor unit 11. Each of the semiconductor chips 30a and 30b is also made of silicon or silicon carbide as its main component.
The individual semiconductor chip 30a is a switching element. The switching element is, for example, an IGBT or a power MOSFET. When the individual semiconductor chip 30a is an IGBT, the semiconductor chip 30a has an input electrode (a collector electrode) on its rear surface and a control electrode 31 (a gate electrode) and an output electrode 32 (an emitter electrode) on its front surface. When the individual semiconductor chip 30a is a power MOSFET, the semiconductor chip 30a has an input electrode (a drain electrode) on its rear surface and has a control electrode 31 (a gate electrode) and an output electrode 32 (a source electrode) on its front surface. The rear surface of the individual semiconductor chip 30a is mechanically and electrically bonded to the circuit pattern 23a via solder. The individual semiconductor chip 30a is bonded to the circuit pattern 23a, with its control electrode 31 facing in the -X direction. The semiconductor chips 30a may be disposed such that their respective control electrodes 31 face each other, as is the case with the semiconductor chips 30 in
In addition, the individual semiconductor chip 30b is a diode element. The diode element is, for example, an FWD such as a Schottky barrier diode (SBD) or a P-intrinsic-N (PiN) diode. The individual semiconductor chip 30b has an output electrode (a cathode electrode) on its rear surface and has an input electrode (an anode electrode) on its front surface. The rear surface of the semiconductor chip 30b is mechanically and electrically bonded to the circuit pattern 23a via solder.
In addition, the main current wires 41 are connected to the output electrodes on the front surfaces of the semiconductor chips 30a and to the input electrodes on the front surfaces of the semiconductor chips 30b by stitch bonding and are also connected to the circuit pattern 23b. The control wires 42 mechanically and electrically connect the contact area 23c1 located in a center portion of the circuit pattern 23c and the control electrodes 31 of the semiconductor chips 30a.
A semiconductor device having a half-bridge circuit is obtained by disposing two semiconductor units 11, each of which is the above semiconductor unit 11, in a line in the Y direction such that their respective main current directions D1 are opposite to each other and by connecting these semiconductor units to each other as in
In addition, because the two semiconductor units 11 included in the semiconductor device have their respective ceramic circuit boards 20, the insulating property between the semiconductor units is maintained, and short-circuiting between the semiconductor units is prevented. Thus, expansion of the area of the individual ceramic plate 21 is prevented, and expansion of the individual semiconductor unit 11 is thereby prevented. In addition, downsizing of the individual semiconductor unit 11 is achieved, and downsizing of the semiconductor device is achieved.
A third embodiment in which circuit patterns different from those of the semiconductor unit 10 according to the first embodiment are used will be described with reference to
First, the semiconductor chips 30 of the semiconductor unit 12 are bonded to the circuit pattern 23a, with their control electrodes 31 facing outside (in the directions of the third and fourth sides 21c and 21d).
In addition, the circuit pattern 23a has an approximately rectangular shape and includes a projecting area 23a3 projecting in the lower direction in
On the circuit pattern 23a, the semiconductor chips 30 are disposed in an area including a center line (a dashed-dotted line X-X). In
The circuit pattern 23d is formed outside and adjacent to the circuit pattern 23a (on the side opposite to the main current direction D1). In other words, the circuit pattern 23d is provided closer to the first side 21a than is the circuit pattern 23a. In addition, the circuit pattern 23d is formed in a U shape in plan view along the projecting area 23a3 of the circuit pattern 23a. Two end portions of the circuit pattern 23d are mechanically and electrically connected to the output electrodes 32 of the semiconductor chips 30 by sense wires 46. The circuit pattern 23c is formed outside and adjacent to the circuit pattern 23d. That is, the circuit pattern 23c is also formed in a U shape in plan view along the circuit pattern 23d. Two end portions of the circuit pattern 23c are mechanically and electrically connected to the control electrodes 31 of the semiconductor chips 30 by control wires 42.
In addition, the locations of the circuit pattern 23e and the circuit pattern 23f of the semiconductor unit 12 are opposite to those of the semiconductor unit 10. That is, the circuit pattern 23e (a second sense circuit pattern) may be electrically connected to the output electrodes 32 of the semiconductor chips 30. The circuit pattern 23e has a linear shape and is formed outside and adjacent to the circuit pattern 23b (in the main current direction D1). In other words, the circuit pattern 23e is closer to the second side 21b than is the circuit pattern 23b. The (±Y direction) end portions of the circuit pattern 23e are formed to correspond to the (±Y direction) end portions of the circuit pattern 23f. The circuit pattern 23f (a second control circuit pattern) may be electrically connected to the control electrodes 31 of the semiconductor chips 30. The circuit pattern 23f has a linear shape and is formed outside and adjacent to the circuit pattern 23e (in the main current direction D1). The (±Y direction) end portions of the circuit pattern 23f are formed to correspond to the (±Y direction) end portions of the circuit pattern 23b.
In addition, these circuit patterns 23d and 23e are formed symmetrically with respect to the center line (the dashed-dotted line X-X) perpendicular to the main current direction D1 of the ceramic circuit board 20. In addition, the circuit patterns 23d and 23e are equally distanced from the first and second sides 21a and 21b of the ceramic plate 21, respectively. The semiconductor unit 12 may be structured without the sense coupling circuit pattern 23e and the gate coupling circuit pattern 23f. In this way, the board area is further reduced.
A semiconductor device having a half-bridge circuit is obtained by disposing two semiconductor units 12, each of which is the above semiconductor unit 12, in a line in the Y direction such that their respective main current directions D1 are opposite to each other and by connecting these semiconductor units to each other as in
In addition, because the two semiconductor units 12 included in the semiconductor device have their respective ceramic circuit boards 20, the insulating property between the semiconductor units 12 is maintained, and short-circuiting between the semiconductor units 12 is prevented. Thus, expansion of the area of the individual ceramic plate 21 is prevented, and expansion of the individual semiconductor unit 12 is thereby prevented. In addition, downsizing of the individual semiconductor unit 12 is achieved, and downsizing of the semiconductor device is achieved.
According to the technique disclosed herein, because short-circuiting is prevented and expansion of a ceramic plate is reduced, downsizing of a semiconductor unit and a semiconductor device is achieved.
All examples and conditional language provided herein are intended for the pedagogical purposes of aiding the reader in understanding the invention and the concepts contributed by the inventor to further the art, and are not to be construed as limitations to such specifically recited examples and conditions, nor does the organization of such examples in the specification relate to a showing of the superiority and inferiority of the invention. Although one or more embodiments of the present invention have been described in detail, it should be understood that various changes, substitutions, and alterations could be made hereto without departing from the spirit and scope of the invention.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2020-210958 | Dec 2020 | JP | national |
This application is a continuation application of International Application PCT/JP2021/040283 filed on Nov. 1, 2021, which designated the U.S., which claims priority to Japanese Patent Application No. 2020-210958, filed on Dec. 21, 2020, the entire contents of which are incorporated herein by reference.
| Number | Date | Country | |
|---|---|---|---|
| Parent | PCT/JP2021/040283 | Nov 2021 | US |
| Child | 17994116 | US |
