Patent Application
20150137187
The contents of the following patent applications are incorporated herein by reference:
1. Technical Field
The present invention relates to a semiconductor wafer, a method for manufacturing a semiconductor wafer, and a method for manufacturing a composite wafer.
2. Related Art
Group III-V compound semiconductors such as GaAs, InGaAs and InP have high electron mobility. On the other hand, Group IV semiconductors such as Ge and SiGe have high hole mobility. Therefore, a highly advanced CMOSFET (complementary metal-oxide-semiconductor field effect transistor) can be realized if the Group III-V compound semiconductors are used to form an N-channel MOSFET (metal-oxide-semiconductor field effect transistor) (hereinafter, may be simply referred to as nMOSFET) and the Group IV semiconductors are used to form a P-channel MOSFET (hereinafter, may be simply referred to as “pMOSFET”). Non-Patent Document 1 discloses a CMOSFET structure in which an N-channel MOSFET having a channel made of a Group III-V compound semiconductor and a P-channel MOSFET having a channel made of Ge are formed on a single wafer.
To form heterogeneous materials of a Group III-V compound semiconductor crystal layer and a Group IV semiconductor crystal layer on a single wafer (for example, a silicon wafer), a technique is known to transfer onto the transfer target wafer a semiconductor crystal layer that has been formed on a semiconductor crystal growth wafer. For example, Non-Patent Document 2 discloses a technique according to which an AlAs layer is formed as a sacrificial layer on a GaAs wafer and a Ge layer is formed on the sacrificial layer (AlAs layer) and transferred onto a silicon wafer.
To form on a single wafer an N-channel MISFET (metal-insulator-semiconductor field effect transistor) (hereinafter, may be simply referred to as “nMISFET”) having a channel made of a Group III-V compound semiconductor and a P-channel MISFET (hereinafter, may be simply referred to as “pMISFET”) having a channel made of a Group IV semiconductor, it is necessary to develop a technique of forming the Group III-V compound semiconductor crystal layer for the n-MISFET and the Group IV semiconductor crystal layer for the p-MISFET on the single wafer. Furthermore, taking into consideration that the nMISFET and the pMISFET are manufactured as a LSI (large scale integration), a semiconductor crystal layer for an nMISFET or a pMISFET is preferably formed on a silicon wafer that allows utilization of existing manufacturing devices and existing steps. By using the technique of Non-Patent Document 2, a Group III-V compound semiconductor crystal layer and a Group IV semiconductor crystal layer can be formed on a single wafer, and these semiconductor crystal layers can be formed on a silicon wafer that is advantageous in terms of manufacturing.
However, in the technique of Non-Patent Document 2, a semiconductor crystal layer is separated from a semiconductor crystal layer forming wafer by etching and removing a sacrificial layer. Accordingly, when separating the semiconductor crystal layer, it is necessary to use an etching agent that has a high etching selection ratio of the sacrificial layer with respect to the etching selection ratio of the semiconductor crystal layer, that is, an etching agent that substantially does not etch away the semiconductor crystal layer, but provides a high etching rate of the sacrificial layer. Because it is assumed that a semiconductor crystal layer can be formed on the sacrificial layer by epitaxial growth, both of the requirements that the semiconductor crystal layer can be grown epitaxially, and that the etching selection ratio is sufficient need to be met, and depending on the material of the semiconductor crystal layer, selection of the sacrificial layer and the etching agent sometimes becomes difficult. In particular, when the semiconductor crystal layer is a Group III-V compound semiconductor, an electronic device is often created by using hetero-junction, and a semiconductor crystal layer is often a laminate including a plurality of layers. Because even in such a case, the requirement about the etching selection ratio of the sacrificial layer needs to be met with respect to all of the plurality of semiconductor crystal layers constituting the laminate, selection of the etching agent tends to become more difficult, and sometimes an appropriate etching agent does not exist.
An object of the present invention is to provide a technique that, when separating a semiconductor crystal layer from a wafer by using a sacrificial layer, allows selection of an appropriate combination of the sacrificial layer and an etching agent, irrespective of the material or structure of the semiconductor crystal layer.
In order to solve the problem, a first aspect of the present invention provides a semiconductor wafer comprising, on a semiconductor crystal layer forming wafer, a first semiconductor crystal layer, a second semiconductor crystal layer, and a third semiconductor crystal layer, the semiconductor crystal layer forming wafer, the first semiconductor crystal layer, the second semiconductor crystal layer, and the third semiconductor crystal layer being positioned in the order of the semiconductor crystal layer forming wafer, the first semiconductor crystal layer, the second semiconductor crystal layer, and the third semiconductor crystal layer, wherein both the etching rate of the first semiconductor crystal layer by a first etching agent and the etching rate of the third semiconductor crystal layer by the first etching agent are higher than the etching rate of the second semiconductor crystal layer by the first etching agent, and both the etching rate of the first semiconductor crystal layer by a second etching agent and the etching rate of the third semiconductor crystal layer by the second etching agent are lower than the etching rate of the second semiconductor crystal layer by the second etching agent.
The semiconductor wafer may further comprise a fourth semiconductor crystal layer, the semiconductor crystal layer forming wafer, the first semiconductor crystal layer, the second semiconductor crystal layer, the third semiconductor crystal layer, and the fourth semiconductor crystal layer being positioned in the order of the semiconductor crystal layer forming wafer, the first semiconductor crystal layer, the second semiconductor crystal layer, the third semiconductor crystal layer, and the fourth semiconductor crystal layer, wherein both the etching rate of the first semiconductor crystal layer by the first etching agent and the etching rate of the third semiconductor crystal layer by the first etching agent may be higher than the etching rate of the fourth semiconductor crystal layer by the first etching agent, and both the etching rate of the first semiconductor crystal layer by the second etching agent and the etching rate of the third semiconductor crystal layer by the second etching agent may be lower than the etching rate of the fourth semiconductor crystal layer by the second etching agent. The etching rate of the semiconductor crystal layer forming wafer by the first etching agent may be equivalent to the etching rate of the second semiconductor crystal layer by the first etching agent, and the etching rate of the semiconductor crystal layer forming wafer by the second etching agent may be equivalent to the etching rate of the second semiconductor crystal layer by the second etching agent.
The semiconductor crystal layer forming wafer may be made of InP, the first semiconductor crystal layer and the third semiconductor crystal layer may be made of InGaAs or InAs, and the second semiconductor crystal layer is made of InP. In this case, when the semiconductor wafer further comprises the fourth semiconductor crystal layer, the fourth semiconductor crystal layer may be made of InP. The third semiconductor crystal layer may have a semiconductor laminate structure, and the semiconductor laminate structure preferably consists of a plurality of semiconductor layers that lattice-match or pseudo-lattice-match InP.
When the semiconductor crystal layer forming wafer is made of GaAs or Ge, the first semiconductor crystal layer and the third semiconductor crystal layer are made of SiGe, and the second semiconductor crystal layer is made of Ge. In this case, when the semiconductor wafer further comprises the fourth semiconductor crystal layer, the fourth semiconductor crystal layer may be made of Ge.
A second aspect of the present invention provides a method for manufacturing a semiconductor wafer comprising forming, on a semiconductor crystal layer forming wafer, a first semiconductor crystal layer, a second semiconductor crystal layer, and a third semiconductor crystal layer in the order of the first semiconductor crystal layer, the second semiconductor crystal layer, and the third semiconductor crystal layer by epitaxial growth, wherein the first semiconductor crystal layer, the second semiconductor crystal layer, and the third semiconductor crystal layer are such that both the etching rate of the first semiconductor crystal layer by a first etching agent and the etching rate of the third semiconductor crystal layer by the first etching agent are higher than the etching rate of the second semiconductor crystal layer by the first etching agent, and both the etching rate of the first semiconductor crystal layer by a second etching agent and the etching rate of the third semiconductor crystal layer by the second etching agent are lower than the etching rate of the second semiconductor crystal layer by the second etching agent.
A third aspect of the present invention provides a method for manufacturing a semiconductor wafer comprising forming, on a semiconductor crystal layer forming wafer, a first semiconductor crystal layer, a second semiconductor crystal layer, a third semiconductor crystal layer, and a fourth semiconductor crystal layer in the order of the first semiconductor crystal layer, the second semiconductor crystal layer, the third semiconductor crystal layer, and the fourth semiconductor crystal layer by epitaxial growth, wherein the first semiconductor crystal layer, the second semiconductor crystal layer, the third semiconductor crystal layer, and the fourth semiconductor crystal layer are such that both the etching rate of the first semiconductor crystal layer by a first etching agent and the etching rate of the third semiconductor crystal layer by the first etching agent are higher than both the etching rate of the second semiconductor crystal layer by the first etching agent and the etching rate of the fourth semiconductor crystal layer by the first etching agent, and both the etching rate of the first semiconductor crystal layer by a second etching agent and the etching rate of the third semiconductor crystal layer by the second etching agent are lower than both the etching rate of the second semiconductor crystal layer by the second etching agent and the etching rate of the fourth semiconductor crystal layer by the second etching agent.
A fourth aspect of the present invention provides a method for manufacturing a composite wafer, the method comprising: forming a pattern of a first cover layer on the above-described semiconductor wafer; performing first etching to etch away the third semiconductor crystal layer by using the first cover layer as a mask; forming a pattern of a second cover layer to cover the third semiconductor crystal layer patterned by the first etching; performing second etching to etch away the second semiconductor crystal layer by using the second cover layer as a mask and by using the second etching agent; and removing the first semiconductor crystal layer by performing etching by using the first etching agent, and separating, from the semiconductor crystal layer forming wafer, the second semiconductor crystal layer and the third semiconductor crystal layer that are covered with the second cover layer. The first etching may include etching away the third semiconductor crystal layer by using the first etching agent.
A fifth aspect of the present invention provides a method for manufacturing a composite wafer, the method comprising: forming a pattern of a first cover layer on the above-described semiconductor wafer; performing first etching to etch away the third semiconductor crystal layer by using the first cover layer as a mask; performing second etching to etch away the second semiconductor crystal layer by using, as a mask, the first cover layer or the third semiconductor crystal layer patterned in the first etching and using the second etching agent; forming a pattern of a third cover layer to cover the third semiconductor crystal layer patterned in the first etching and the second semiconductor crystal layer patterned in the second etching; and removing the first semiconductor crystal layer by performing etching by using the first etching agent, and separating, from the semiconductor crystal layer forming wafer, the second semiconductor crystal layer and the third semiconductor crystal layer that are covered with the third cover layer. The first etching may include etching away the third semiconductor crystal layer by using the first etching agent.
A sixth aspect of the present invention provides a method for manufacturing a composite wafer, the method comprising: forming a pattern of a first cover layer on the above-described semiconductor wafer having the fourth semiconductor crystal layer; performing first etching to etch away the fourth semiconductor crystal layer by using the first cover layer as a mask; performing second etching to etch away the third semiconductor crystal layer by using, as a mask, the first cover layer or the fourth semiconductor crystal layer patterned by the first etching; forming a pattern of a fourth cover layer to cover the fourth semiconductor crystal layer patterned in the first etching and the third semiconductor crystal layer patterned in the second etching; performing third etching to etch away the second semiconductor crystal layer by using the fourth cover layer as a mask and by using the second etching agent; and removing the first semiconductor crystal layer by performing etching by using the first etching agent, and separating, from the semiconductor crystal layer forming wafer, the second semiconductor crystal layer, the third semiconductor crystal layer, and the fourth semiconductor crystal layer that are covered with the fourth cover layer. The first etching may include etching away the fourth semiconductor crystal layer by using the second etching agent, and the second etching may include etching away the third semiconductor crystal layer by using the first etching agent
A seventh aspect of the present invention provides a method for manufacturing a composite wafer, the method comprising: forming a pattern of a first cover layer on the above-described semiconductor wafer having the fourth semiconductor crystal layer; performing first etching to etch away the fourth semiconductor crystal layer and the third semiconductor crystal layer by using the first cover layer as a mask and to further etch away the second semiconductor crystal layer by using the second etching agent; forming a pattern of a fifth cover layer to cover the fourth semiconductor crystal layer, the third semiconductor crystal layer, and the second semiconductor crystal layer that are patterned in the first etching; and removing the first semiconductor crystal layer by performing etching by using the first etching agent, and separating, from the semiconductor crystal layer forming wafer, the second semiconductor crystal layer, the third semiconductor crystal layer, and the fourth semiconductor crystal layer that are covered with the fifth cover layer.
In each of the fourth to seventh aspects, the second cover layer, the third layer, the fourth layer, and the fifth layer may respectively cover the third semiconductor crystal layer or the like depending their aspects, and may cover the back surface and side surface of the semiconductor crystal layer forming wafer.
In each of the fourth to seventh aspects, the further may further comprise: prior to the separation, bonding the semiconductor wafer and a transfer target wafer, with the front surface of the semiconductor wafer on which the third semiconductor crystal layer is formed being caused to face the front surface of the transfer target wafer; and during the separation, separating the semiconductor wafer and the transfer target wafer in a state that a semiconductor crystal layer including the second semiconductor crystal layer and the third semiconductor crystal layer is left on the transfer target wafer.
An eighth aspect of the present invention provides a method for manufacturing a composite wafer, the method comprising: forming a sixth cover layer to cover the above-described entire surface of the semiconductor wafer; patterning and removing a part of the sixth cover layer on the third semiconductor crystal layer; etching away the third semiconductor crystal layer by using the sixth cover layer on the third semiconductor crystal layer as a mask; and removing the second semiconductor crystal layer by performing etching by using the second etching agent, and separating the third semiconductor crystal layer from the semiconductor crystal layer forming wafer that is covered with the sixth cover layer and the first semiconductor crystal layer.
The method may further comprise: after etching away the third semiconductor crystal layer and prior to the separation, bonding the semiconductor wafer and a transfer target wafer, with the front surface of the third semiconductor crystal layer being caused to face the front surface of the transfer target wafer; and during the separation, separating the semiconductor wafer and the transfer target wafer in a state that the third semiconductor crystal layer is left on the transfer target wafer. The method may further comprise, after etching away the third semiconductor crystal layer and prior to the bonding, etching away the second semiconductor crystal layer by using the sixth cover layer as a mask and by using the second etching agent.
A ninth aspect of the present invention provides a method for manufacturing a composite wafer by using a semiconductor wafer having, on a semiconductor crystal layer forming wafer, a first semiconductor crystal layer, a second semiconductor crystal layer, and a third semiconductor crystal layer, the semiconductor crystal layer forming wafer, the first semiconductor crystal layer, the second semiconductor crystal layer, and the third semiconductor crystal layer being positioned in the order of the semiconductor crystal layer forming wafer, the first semiconductor crystal layer, the second semiconductor crystal layer, and the third semiconductor crystal layer, both the etching rate of the semiconductor crystal layer forming wafer by a second etching agent and the etching rate of the second semiconductor crystal layer by the second etching agent being higher than both the etching rate of the first semiconductor crystal layer by the second etching agent and the etching rate of the third semiconductor crystal layer by the second etching agent, the method comprising forming a sixth cover layer to cover the entire surface of the semiconductor wafer; patterning and removing a part of the sixth cover layer on the third semiconductor crystal layer; etching away the third semiconductor crystal layer by using the sixth cover layer on the third semiconductor crystal layer as a mask; and removing the second semiconductor crystal layer by performing etching by using the second etching agent, and separating the third semiconductor crystal layer from the semiconductor crystal layer forming wafer that is covered with the sixth cover layer and the first semiconductor crystal layer.
The summary clause does not necessarily describe all necessary features of the embodiments of the present invention. The present invention may also be a sub-combination of the features described above.
Hereinafter, (some) embodiment(s) of the present invention will be described. The embodiment(s) do(es) not limit the invention according to the claims, and all the combinations of the features described in the embodiment(s) are not necessarily essential to means provided by aspects of the invention.
The semiconductor crystal layer forming wafer 102 is a wafer for forming a high quality third semiconductor crystal layer 108. A preferred material for the semiconductor crystal layer forming wafer 102 depends on the material, formation method, and the like of the third semiconductor crystal layer 108. In general, the semiconductor crystal layer forming wafer 102 is desirably made of a material that lattice-matches or pseudo-lattice-matches the third semiconductor crystal layer 108 to be formed. For example, when an InP layer is formed as the third semiconductor crystal layer 108 by epitaxial growth, the semiconductor crystal layer forming wafer 102 is preferably an InP single crystal wafer, and a GaAs wafer, a Si wafer, or the like can be selected. For example, a GaAs layer or a Ge layer is formed as the third semiconductor crystal layer 108 by epitaxial growth, the semiconductor crystal layer forming wafer 102 is preferably a GaAs single crystal wafer, and a single crystal wafer of InP, sapphire Ge, or SiC can be selected. When the semiconductor crystal layer forming wafer 102 is a GaAs single crystal wafer or an InP single crystal wafer, the plane on which the third semiconductor crystal layer 108 is formed may be the (100) plane or (111) plane.
The first semiconductor crystal layer 104 is a sacrificial layer for separating the semiconductor crystal layer forming wafer 102 from the second semiconductor crystal layer 106 and the third semiconductor crystal layer 108. When the first semiconductor crystal layer 104 is removed by etching, the semiconductor crystal layer forming wafer 102 is separated from the second semiconductor crystal layer 106 and the third semiconductor crystal layer 108. When an InP single crystal wafer is selected as the semiconductor crystal layer forming wafer 102, and an InP layer is selected as the second semiconductor crystal layer 106, an InGaAs layer or an InAs layer can be selected as the first semiconductor crystal layer 104, and an InAs layer or an InxGa1-xAs layer (1>x>0.53) is preferable. When a GaAs single crystal wafer or a Ge single crystal wafer is selected as the semiconductor crystal layer forming wafer 102, and a Ge layer is selected as the second semiconductor crystal layer 106, the first semiconductor crystal layer 104 is preferably a SiGe layer. When a GaAs single crystal wafer is selected as the semiconductor crystal layer forming wafer 102, and a GaAs layer is selected as the second semiconductor crystal layer 106, the first semiconductor crystal layer 104 is preferably an AlAs layer, and an InAlAs layer, an InGap layer, an InAlP layer, an InGaAlP layer, or an AlSb layer can be selected. Because as the thickness of the first semiconductor crystal layer 104 becomes larger, the crystallinity of the third semiconductor crystal layer 108 tends to be lower, the thickness of the first semiconductor crystal layer 104 is preferably as small as possible as long as the functionality as a sacrificial layer can be ensured. The thickness of the first semiconductor crystal layer 104 can be selected from within the range of 0.1 nm to 10 μm.
The second semiconductor crystal layer 106 is an etching stopper layer to be used when etching away the first semiconductor crystal layer 104 which is a sacrificial layer. The second semiconductor crystal layer 106 suffices as long as the etching selection ratio with respect to the first semiconductor crystal layer 104 is ensured. Specific examples of the second semiconductor crystal layer 106 include, as exemplified above, an InP layer, a Ge layer, and a GaAs layer. Because as the thickness of the second semiconductor crystal layer 106 becomes larger, the crystallinity of the third semiconductor crystal layer 108 tends to be lower, the thickness of the second semiconductor crystal layer 106 is preferably as small as possible as long as the functionality as an etching stopper layer can be ensured. In the present example, the functionality of the etching stopper layer is to protect the third semiconductor crystal layer 108 when etching away the first semiconductor crystal layer 104. The thickness of the second semiconductor crystal layer 106 can be selected from within the range of 0.1 nm to 10 μm.
The third semiconductor crystal layer 108 is a transfer layer that is to be separated from the semiconductor crystal layer forming wafer 102 when the first semiconductor crystal layer 104 is etched away and to be transferred onto a transfer target wafer or the like. The third semiconductor crystal layer 108 is utilized for an active layer or the like of a semiconductor device. When the third semiconductor crystal layer 108 is formed on the semiconductor crystal layer forming wafer 102 by epitaxial growth or the like, high quality crystallinity of the third semiconductor crystal layer 108 is realized. Furthermore, when the third semiconductor crystal layer 108 is transferred onto a transfer target wafer, it becomes possible to form the third semiconductor crystal layer 108 on a given transfer target wafer without considering lattice-matching and the like with the transfer target wafer.
Examples of the third semiconductor crystal layer 108 include a crystal layer made of a Group III-V compound semiconductor, a crystal layer made of a Group IV semiconductor, and a crystal layer made of a Group II-VI compound semiconductor. Examples of the Group III-V compound semiconductor include AluGavIn1-u-vNmPnAsqSb1-m-n-q (0≦u≦1, 0≦v≦1, 0≦m≦1, 0≦n≦1, 0≦q≦1), for example, GaAs, InyGa1-yAs (0<y<1), InP and GaSb. Examples of the Group IV semiconductor include Ge and GexSi1-x (0<x<1). Examples of the Group II-VI compound semiconductor is ZnO, ZnSe, ZnTe, CdS, CdSe, and CdTe. When the Group IV semiconductor is GexSi1-x, the Ge ratio x is preferably equal to or higher than 0.9. When the Ge ratio x is equal to or higher than 0.9, the Group IV semiconductor can have similar semiconductor characteristics to Ge. If the third semiconductor crystal layer 108 is one of the above-described crystal layers and laminate, the third semiconductor crystal layer 108 can be used to form an active layer of a field effect transistor with high mobility, in particular, of a complementary field effect transistor having high mobility.
The third semiconductor crystal layer 108 is not limited to those exemplified above, but a semiconductor layer other than those exemplified is also applicable. Also, the third semiconductor crystal layer 108 may be a semiconductor laminate in which a plurality of types of semiconductor layers are laminated. Examples of a structure of a semiconductor laminate obtained in the present invention include, for example, a HEMT (High Electron Mobility Transistor) structure having a AlGaAs buffer layer, an n-type AlGaAs electron introducing layer, an InxGa1-xAs (0<x≦0.4) channel layer, an n-type AlGaAs electron introducing layer, and an n-type AlGaAs contact layer. Also, examples of a structure of a semiconductor laminate obtained in the present invention include a HBT (Heterojunction Bipolar Transistor) structure having a p-type GaAs base layer, an n-type GaAs contact layer, and an n-type InGaP emitter layer. Also, examples of a structure of a semiconductor laminate obtained in the present invention include a MESFET (Metal-Semiconductor Field Effect Transistor) structure, a VCSEL (Vertical Cavity Surface Emitting LASER) structure, a red LED (Light Emitting Diode) structure, a semiconductor laser structure, a photodiode structure, and a solar cell structure. Note that the structures listed here are examples, and the present invention can be applied to device structures in general that use Group III-V compound hetero-junction.
The thickness of the third semiconductor crystal layer 108 can be appropriately selected from within the range of 0.1 nm to 500 μm. The thickness of the third semiconductor crystal layer 108 is preferably no less than 0.1 nm and less than 1 μm. When the third semiconductor crystal layer 108 is less than 1 μm, for example, it can be used for a composite wafer suited to manufacturing of a high performance transistor such as a ultrathin-body MISFET.
To cause the first semiconductor crystal layer 104 to serve as a sacrificial layer, cause the second semiconductor crystal layer 106 to serve as an etching stopper layer, and separate the third semiconductor crystal layer 108 from the semiconductor crystal layer forming wafer 102, the relationship among the etching rates of the semiconductor crystal layer forming wafer 102, the first semiconductor crystal layer 104, the second semiconductor crystal layer 106, and the third semiconductor crystal layer 108 are required to meet the following conditions. That is, both the etching rate of the first semiconductor crystal layer 104 by a first etching agent and the etching rate of the third semiconductor crystal layer 108 by the first etching agent are higher than the etching rate of the second semiconductor crystal layer 106 by the first etching agent. Also, both the etching rate of the first semiconductor crystal layer 104 by a second etching agent and the etching rate of the third semiconductor crystal layer 108 by the second etching agent are lower than the etching rate of the second semiconductor crystal layer 106 by the second etching agent. When the etching rates have the relationship like these, in a method for manufacturing a composite wafer described below, it is possible to cause the first semiconductor crystal layer 104 to serve as a sacrificial layer, cause the second semiconductor crystal layer 106 to serve as an etching stopper layer, and separate the third semiconductor crystal layer 108 from the semiconductor crystal layer forming wafer 102.
Note that the etching rate of the semiconductor crystal layer forming wafer 102 by the first etching agent may be equivalent to the etching rate of the second semiconductor crystal layer 106 by the first etching agent. Also, the etching rate of the semiconductor crystal layer forming wafer 102 by the second etching agent may be equivalent to the etching rate of the second semiconductor crystal layer 106 by the second etching agent. The “etching agent” includes both an “etching solution” and “etching gas”. That is, etching in the present specification includes both wet etching and dry etching.
Also, the semiconductor crystal layer forming wafer 102 may be made of InP, the first semiconductor crystal layer 104 and the third semiconductor crystal layer 108 may be made of InGaAs or InAs, and the second semiconductor crystal layer 106 may be made of InP. InGaAs or InAs used for the first semiconductor crystal layer 104 or the third semiconductor crystal layer 108 lattice-matches InP. When InGaAs is used, it is preferably InxGa1-xAs (1>x>0.53). The semiconductor crystal layer forming wafer 102 may be made of GaAs or Ge, the first semiconductor crystal layer 104 and the third semiconductor crystal layer 108 may be made of SiGe, and the second semiconductor crystal layer 106 may be made of Ge.
When the semiconductor crystal layer forming wafer 102 is an InP single crystal wafer, the third semiconductor crystal layer 108 may have a semiconductor laminate structure. In this case, the semiconductor laminate structure is preferably made of a plurality of semiconductor layers that lattice-match or pseudo-lattice-match InP. The semiconductor laminate structure may constitute a quantum well. Also, the semiconductor laminate structure may be a strained super lattice structure that is designed to have a lattice constant that gradually increases or decreases in the thickness direction of the third semiconductor crystal layer 108. In this case, even when a crystal layer is formed on the third semiconductor crystal layer 108, it becomes unnecessary to cause the crystal layer to lattice-match or pseudo-lattice-match InP.
The first semiconductor crystal layer 104, the second semiconductor crystal layer 106, and the third semiconductor crystal layer 108 are formed sequentially on the semiconductor crystal layer forming wafer 102 by epitaxial growth, CVD (Chemical Vapor Deposition), sputtering, or ALD (Atomic Layer Deposition). Epitaxial growth may be MOCVD (Metal Organic Chemical Vapor Deposition), or MBE (Molecular Beam Epitaxy). When a Group III-V compound semiconductor crystal layer is formed as the first semiconductor crystal layer 104, the second semiconductor crystal layer 106, or the third semiconductor crystal layer 108 by MOCVD, TMGa (trimethylgallium), TMA (trimethylaluminum), TMIn (trimethylindium), AsH3 (arsine), PH3 (phosphine), or the like may be used as the source gas. When a Group IV semiconductor crystal layer is formed as the first semiconductor crystal layer 104, the second semiconductor crystal layer 106, or the third semiconductor crystal layer 108 by CVD, GeH4 (germane), SiH4 (silane), Si2H6 (disilane), or the like may be used as the source gas. Hydrogen may be used as the carrier gas. A compound in which a part of a plurality of hydrogen atom groups of the source gas is substituted with a chlorine atom or a hydrocarbon group may be used. The reaction temperature may be appropriately selected from within the range of 300° C. to 900° C. and preferably within the range of 400 to 800° C. By appropriately selecting the source gas flow rate or the reaction duration, the thickness of the first semiconductor crystal layer 104, the second semiconductor crystal layer 106, or the third semiconductor crystal layer 108 can be controlled.
As illustrated in
Next, as illustrated in
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Next, as illustrated in
Lastly, as illustrated in
In the method for manufacturing a composite wafer in the present second embodiment, when the third semiconductor crystal layer 108 is to be separated from the semiconductor crystal layer forming wafer 102, the third semiconductor crystal layer 108 is surrounded by the second cover layer 130 and the second semiconductor crystal layer 106, and thus is never exposed to the first etching agent. Accordingly, a material that is similar to that of the first semiconductor crystal layer 104 can be used as the third semiconductor crystal layer 108, and an etching agent (first etching agent) can be selected without being limited by the material of the third semiconductor crystal layer 108 to be utilized as an active layer. Accordingly, the degree of freedom of manufacturing a composite wafer is enhanced, and the manufacturing becomes easy. Note that the etching agent used in etching of the third semiconductor crystal layer 108 may not be the first etching agent.
Note that, after the step illustrated in
Next, as illustrated in
Effects similar to those of the second embodiment can be attained in the method for manufacturing a composite wafer like this. Note that as in the second embodiment, the transfer target wafer 220 can be applied to the third embodiment.
The material of the fourth semiconductor crystal layer 210 is similar to that of the second semiconductor crystal layer 106. However, the fourth semiconductor crystal layer 210 constitutes hetero-junction together with the third semiconductor crystal layer 108, and is to be utilized as an active layer of a semiconductor device. Note that the method for manufacturing the fourth semiconductor crystal layer 210 is similar to the method for manufacturing the second semiconductor crystal layer 106.
That is, the semiconductor wafer 200 further has the fourth semiconductor crystal layer 210, and the semiconductor crystal layer forming wafer 102, the first semiconductor crystal layer 104, the second semiconductor crystal layer 106, the third semiconductor crystal layer 108, and the fourth semiconductor crystal layer 210 are positioned in the order of the semiconductor crystal layer forming wafer 102, the first semiconductor crystal layer 104, the second semiconductor crystal layer 106, the third semiconductor crystal layer 108, and the fourth semiconductor crystal layer 210. Both the etching rate of the first semiconductor crystal layer 104 by a first etching agent and the etching rate of the third semiconductor crystal layer 108 by the first etching agent are higher than the etching rate of the fourth semiconductor crystal layer 210 by the first etching agent. Also, both the etching rate of the first semiconductor crystal layer 104 by the second etching agent and the etching rate of the third semiconductor crystal layer 108 by the second etching agent are lower than the fourth semiconductor crystal layer 210 by the second etching agent. In the present example, the etching rate of the second semiconductor crystal layer 106 and the etching rate of the fourth semiconductor crystal layer 210 are equivalent to each other irrespective of the etching agent.
The semiconductor crystal layer forming wafer 102 may be made of InP, the first semiconductor crystal layer 104 and the third semiconductor crystal layer 108 may be made of InGaAs or InAs, and the second semiconductor crystal layer 106 and the fourth semiconductor crystal layer 210 may be made of InP, for example. Alternatively, the semiconductor crystal layer forming wafer 102 may be made of GaAs or Ge, the first semiconductor crystal layer 104 and the third semiconductor crystal layer 108 may be made of SiGe, and the second semiconductor crystal layer 106 and the fourth semiconductor crystal layer 210 may be made of Ge, for example.
As illustrated in
Because according to the above-mentioned method for manufacturing a composite wafer, even when the third semiconductor crystal layer 108 and the fourth semiconductor crystal layer 210 are made of different materials, and selection of the etching agent is significantly limited, the third semiconductor crystal layer 108 and the fourth semiconductor crystal layer 210 are surrounded by the fourth cover layer 150 and the second semiconductor crystal layer 106, the third semiconductor crystal layer 108 and the fourth semiconductor crystal layer 210, especially the third semiconductor crystal layer 108 that is easily corroded by the first etching agent, are never exposed to the first etching agent at the time of etching away the first semiconductor crystal layer 104. Also, because the fourth semiconductor crystal layer 210 is surrounded by the fourth cover layer 150 and the third semiconductor crystal layer 108, the fourth semiconductor crystal layer 210 that is easily corroded by the second etching agent is never exposed to the second etching agent at the time of etching away the second semiconductor crystal layer 106. Accordingly, a material that is similar to that of the first semiconductor crystal layer 104 can be used as the third semiconductor crystal layer 108, and an etching agent (first etching agent) can be selected without being limited by the material of the third semiconductor crystal layer 108 to form hetero-junction with the fourth semiconductor crystal layer 210. Accordingly, the degree of freedom of manufacturing a composite wafer is enhanced, and the manufacturing becomes easy. Note that as in the second embodiment, the transfer target wafer 220 can be applied to the fifth embodiment.
Effects similar to those of the fifth embodiment can be attained in the method for manufacturing a composite wafer like this. Note that as in the second embodiment, the transfer target wafer 220 can be applied to the sixth embodiment.
Note that, in the above-mentioned embodiment, a plurality of the set of the first semiconductor crystal layer 104, the second semiconductor crystal layer 106, and the third semiconductor crystal layer 108, or a plurality of the set of the first semiconductor crystal layer 104, the second semiconductor crystal layer 106, the third semiconductor crystal layer 108, and the fourth semiconductor crystal layer 210 may be repeatedly laminated on the semiconductor crystal layer forming wafer 102. In this case, the above-mentioned method for manufacturing a composite wafer may be applied to the uppermost set of layers to transfer the second semiconductor crystal layer 106, the third semiconductor crystal layer 108, and the like onto the transfer target wafer 220, and subsequently, transfer of the second semiconductor crystal layer 106, the third semiconductor crystal layer 108, and the like may be performed similarly on the second uppermost set. Thereby, the epitaxial growth step on the semiconductor crystal layer forming wafer 102 can be shortened.
Also, in the above-mentioned embodiment, the second cover layer 130, the third cover layer 140, the fourth cover layer 150, and the fifth cover layer 160 respectively may cover the third semiconductor crystal layer 108 or the like depending their aspects, and may cover the back surface and side surface of the semiconductor crystal layer forming wafer 102. For example, an example in which, in the fifth embodiment, the fourth cover layer 150 covers the back surface and side surface of the semiconductor crystal layer forming wafer 102 is described.
After patterning the fourth semiconductor crystal layer 210 and the third semiconductor crystal layer 108 by dry etching, as illustrated in
As illustrated in
Note that the method of forming the cover layer 302 illustrated in
As illustrated in
As illustrated in
(Example of Seventh Embodiment)
A 100-nm In0.53Ga0.47As layer (the first semiconductor crystal layer 104 to serve as a cover layer), a 100-nm InP layer (the second semiconductor crystal layer 106 to serve as a sacrificial layer), and a 200-nm In0.53Ga0.47As layer (the third semiconductor crystal layer 108 to serve as an active layer) were sequentially formed, by epitaxial growth by low-pressure MOCVD, on a 2-inch InP wafer which is the semiconductor crystal layer forming wafer 102 to fabricate a multilayer wafer. Thereafter, the multilayer wafer was introduced into an ALD device, and was coated with Al2O3 (the cover layer 402) of approximately 33 nm by ALD. The deposition conditions of ALD-Al2O3 were as follows: 300° C.; 300 cycles; the aluminum material was TMA (trimethylaluminum); and the oxidant was H2O. Uniform Al2O3 could be deposited on the front surface/back surface/side surface of the multilayer wafer by using ALD. Here, to enhance the coating effect of the ALD-Al2O3 layer (resistance against an acid solution), post-annealing in nitrogen was performed at 600° C. for 90 seconds.
Note that the coating effect of the Al2O3 layer was separately confirmed with an InP wafer (wafer on which the semiconductor crystal layer was not grown epitaxially). That is, after Al2O3 was coated on the InP wafer under the same conditions as the above-mentioned ones, the InP wafer was immersed in hydrochloric acid, but etching did not proceed even after the elapse of five hours or longer, and the state before the immersion was maintained.
In the present example, a positive resist film having a line/space pattern (LS pattern) of 300-μm line width/200-μm pitch was formed on the multilayer wafer, and the ALD-Al2O3 layer was etched away by performing dry etching by using the resist film as a mask and by using CHF3 gas. The resist film was removed by acetone washing and ashing, the step that was formed by etching was measured by using a contact-type step gauge to obtain a measurement of approximately 40 nm. This is slightly larger than the designed value of the Al2O3 layer which was 33 nm, but this is because a part of the In0.53Ga0.47As layer that was lying under the Al2O3 layer was etched away. Next, the In0.53Ga0.47As layer was subjected to an etching process by using the patterned Al2O3 layer as a mask and by using phosphoric acid:hydrogen peroxide solution (3:1:50). Because this etchant does not dissolve InP almost at all, the etching stopped when it reached the InP layer (the sacrificial layer, the second semiconductor crystal layer 106). The Al2O3/In0.53Ga0.47As layer (the active layer, the third semiconductor crystal layer 108) was divided into a plurality of divided pieces by the etching. Next, a process to bond the Al2O3 layer of the processed multilayer wafer front surface and a 4-inch Si wafer was performed. By irradiating the front surface of the Al2O3 layer and the front surface of the Si wafer which was a transfer target wafer with argon ion beam, the front surfaces were activated. Thereafter, the front surface of the Al2O3 layer and the front surface of the Si wafer were caused to face each other, and the processed multilayer wafer and the Si wafer were bonded with each other. The attachment under pressure was performed at normal temperature.
Lastly, an etching solution was introduced into a cavity formed by grooves between adjacent divided pieces of the Al2O3/In0.53Ga0.47As layer, the InP layer (the second semiconductor crystal layer 106) which was the sacrificial layer was removed by etching, and the multilayer wafer and the Si wafer were separated from each other in a state that the Al2O3/In0.53Ga0.47As layer was left on the Si wafer. The etching of the InP layer was performed by immersing the side surface of the bonded wafer into a 23° C. etching solution whose HCl concentration was 10% by mass (10% hydrogen chloride solution), introducing the etching solution into the cavity by the capillary phenomenon, and maintaining this state. The In0.53Ga0.47As layer is not dissolved by the above-mentioned HCl etchant almost at all. Also, the InP wafer was protected by the Al2O3 layer and the In0.53Ga0.47As layer (the cover layer), and thus was never exposed to the HCl etchant, but was protected. In the above-described manner, a semiconductor crystal layer forming wafer having a 200-nm thickness and 300/200-μm LS pattern In0.53Ga0.47As layer on the 4-inch Si wafer was obtained.
When it is described in the present specification that a second element is located “on” a first element such as a layer or a wafer, such description includes a case where the second element is disposed directly on the first element, and also a case where the second element is disposed indirectly on the first element with another element being interposed between the second element and the first element. When the second element is formed “on” the first element also, similarly, the second element may be formed directly or indirectly on the first element. Also, the terms like “on” or “under” that indicate directions indicate relative directions within a semiconductor wafer, a composite wafer, and a device, and may not indicate absolute directions with respect to an external reference surface such as the ground.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2012-164213 | Jul 2012 | JP | national |
| Number | Date | Country | |
|---|---|---|---|
| Parent | PCT/JP2013/004439 | Jul 2013 | US |
| Child | 14602448 | US |
