Signal Routing in a Multilayered Printed Circuit Board

Abstract

A signal routing technique for a multilayered printed circuit board is provided. The multilayered printed circuit board comprises a top layer, a bottom layer and at least one internal layer. Signals for a first subset of a plurality of higher speed buses are routed in stripline on the first internal layer. Signals for a second subset of said plurality of higher speed buses in microstrip on the top layer.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is an enlarged cross-sectional view of a multilayered PCB according to an embodiment of the invention.

FIG. 2 is a schematic diagram of a system comprising several multilayered PCBs shown in FIG. 1 according to an embodiment of the invention.

FIGS. 3-5 are enlarged images of a portion of a top layer of a multilayered PCB according to an embodiment of the invention.

FIG. 6 is an enlarged image of a portion of an internal layer of a multilayered PCB according to an embodiment of the invention.

FIG. 7 is a graphical plot showing a comparison of crosstalk simulation results for two adjacent high speed signal bus lines routed using microstrip techniques and the same two adjacent lines routed using stripline techniques according to an embodiment of the invention.

Claims

1. A circuit board, comprising: a. a top layer, a bottom layer and at least one internal layer;b. lines for a first subset of higher speed signals being routed on said internal layer, wherein the lines for said first subset of the higher speed signals are longer in physical length among the lines for said plurality of higher speed signals; andc. partial vias making connection to said lines for the first subset of higher speed signals on said internal layers, said partial vias extending between said internal layer and said top layer.

2. The circuit board of claim 1, wherein the lines for said first subset of the plurality of higher speed signals are in stripline on said internal layer.

3. The circuit board of claim 2, and further comprising lines for a second subset of said plurality of higher speed signals routed on said top layer in microstrip.

4. The circuit board of claim 3, wherein the lines for said second subset of said plurality of higher speed signals are shorter in physical length than the lines for said first subset of higher speed signals.

5. A multilayered circuit board, comprising: a. a top layer, a bottom layer and at least a first internal layer;b. signal lines for a first subset of a plurality of higher speed buses implemented in stripline on said first internal layer; andc. signal lines for a second subset of said plurality of higher speed buses implemented in microstrip on said top layer.

6. The circuit board of claim 5, and further comprising a second internal layer, and signal lines for a third subset of said plurality of higher speed signals being routed on said second internal layer.

7. The circuit board of claim 6, and further comprising plated-through vias extending between the top layer and the bottom layer, said plated-through vias making electrical connection with said signals lines for said third subset of the plurality of higher speed buses on said second internal layer.

8. The circuit board of claim 7, wherein said signal lines for said third subset of the plurality of higher speed buses extending from a first area on said second internal layer where connection is made to first plated-through vias to a second area on said second internal layer where connection is made to second plated-through vias.

9. The circuit board of claim 5, and further comprising partial vias making electrical connection to the signals for said first subset of the plurality of higher speed buses on said first internal layer, said partial vias extending between said first internal layer and said top layer.

10. The circuit board of claim 9, wherein said signal lines for said first subset of the plurality of higher speed buses extending from a first area on said first internal layer where connected is made to first partial vias to a second area on said first internal layer where connection is made to second plated-through vias.

11. The circuit board of claim 9, and further comprising at least one power supply plane on said top layer and at least one decoupling capacitor positioned within a region of and connected to said power supply plane.

12. The circuit board of claim 11, wherein end portions of the partial vias at the top layer are positioned in a region outside of said power supply plane.

13. The circuit board of claim 12, and further comprising a second internal layer, and signal lines for a third subset of said plurality of higher speed signals being routed on said second internal layer; and plated-through vias extending between the top layer and the bottom layer, said plated-through vias making electrical connection with said signals lines for said third subset of the plurality of higher speed buses on said second internal layer, wherein end portions of the plated-through vias at said top layer being positioned within a region of said power supply plane.

14. The circuit board of claim 13, and further comprising power supply vias extending from said top layer into said circuit board, and wherein end portions of said power supply vias at said top layer are positioned between end portions of the plated-through vias and end portions of said partial vias.

15. A system comprising a plurality of multilayered circuit boards according to claim 5 and a device controller, wherein said plurality of multilayered circuit boards are arranged in daisy-chain organization and wherein one of said plurality of multilayered circuit boards is connected to said device controller.

16. A method for routing signals on a multilayered circuit board having a top layer, bottom layer and at least a first internal layer, comprising: a. routing signals for a first subset of a plurality of higher speed buses in stripline on the first internal layer; andb. routing signals for a second subset of said plurality of higher speed buses in microstrip on the top layer.

17. The method of claim 16, and further comprising routing signal lines for a third subset of said plurality of higher speed signals on a second internal layer.

18. The method of claim 17, and further comprising communicating said signals for the third subset of higher speed buses between said second internal layer and said top layer and between said second internal layer and said bottom layer by vias that extend from the top layer to the bottom layer.

19. The method of claim 18, and further comprising communicating said signals for the first subset of higher speed buses between said top layer and said first internal layer by vias extending between the top layer and said first internal layer.

20. The method of claim 16, wherein (a) routing comprises routing the signals for the first subset of higher speed buses on conductive lines that are longer in length than conductive lines used for routing the signals for the second subset of higher speed buses on the top layer.