Patent Application
20080237750
The present invention relates generally to the field of semiconductor devices, and more particularly relates to a PMOS device having a fully-silicided metal gate that may be used advantageously, for example in a multi-threshold IC (integrated circuit) application, and to a method for fabricating such a device.
Small electronic appliances are today used in a wide variety of applications and have become a ubiquitous part of modern society. These applications include computers, telephones, and home entertainment system components, among many others. One reason for the widespread use of these appliances is that recent advances in technology have expanded their capabilities while at the same time lowering their cost. A key part of this advancing technology has been the development of improved semiconductor devices and the processes for making them.
Semiconductors are materials that after being properly treated conduct electricity when placed under certain conditions, which often include the presence of a small electrical charge. This enables the manufacture of solid-state switches—those that have no moving parts. Other standard (and new) electrical devices can be created out of semiconductors as well. In addition to having no moving components parts that are subject to fatigue or other mechanical failure, solid-state devices can be fabricated in extremely small sizes. Very small, even microscopic electrical components are now used to provide the multitude of resistors, switches, and capacitors necessary for today's electronics applications.
The processes used to fabricate these tiny semiconductor devices are numerous, but the basic process may be described generally. A material, such as silicon, is produced for use as a base, or substrate, upon which various electrical components will be built. This material is then formed into an appropriate shape, usually a thin slice called a wafer. The pure silicon is then selectively treated with one or more materials called dopants, such as ionized boron or phosphorus. The introduction of these impurities begins the process of creating the desired semiconductive properties. Various structures may then be formed at or near one surface of the wafer to construct the desired components.
An exemplary semiconductor device, in this case a transistor, is shown in
All of the transistors in a particular application need not be, and usually are not identical. For example, a MOSFET having a source region and drain region doped with boron ions creates a p-channel device (having positive charge carriers and activated by a negative gate voltage), often referred to as a PMOS device. An NMOS device, on the other hand, has a source region and drain region created with an n-type dopant such as phosphorous ions. These two types of MOSFETs may be use to advantage in pairs, creating a CMOS (complimentary-MOS) device. CMOS devises, combined with appropriate logic configurations, result in significant power savings and are currently widely used throughout the semiconductor industry.
As another example, MOSFETs may be fabricated to have either a higher or a lower threshold voltage, relative to each other. A multi-threshold device has both, and these may be used to advantage where application logic is available to choose the most appropriate type for a given operation. Multiple threshold voltage processes offer a way to reduce total power consumption while maintaining performance. A low transistor threshold voltage may be used on critical-path operations to meet timing constraints. Other operations may be assigned a higher threshold voltage to reduce the sub-threshold leakage component of static power consumption. Multiple threshold voltage transistor devices are becoming popular and are frequently used.
These MOSFET transistors are very small, for example, gate length (distance between the source and the drain) of MOSFET 10 may be no more than 100 nm in width. As gates become smaller, certain undesirable characteristics become more pronounced. Problems caused in this manner are sometimes labeled short-channel effects (SCE). In some cases, these SCE problems may be mitigated or avoided through the use of new types of materials. The gate electrode, for example, has traditionally been made out of polysilicon, though many metals may be used instead and has better performance characteristics in certain areas. On the other hand, metals may present more challenges in the fabrication process.
One material that is now used in an attempt to optimize gate performance is referred to as a silicide. A silicide is basically an alloy of poly and a metal such as nickel, titanium, or cobalt. Silicides are sometimes used to create contacts, typically at the top of a gate electrode or a source or drain. They may, however, be used for the entire gate electrode. One way to fabricate such a gate electrode is to begin with a conventional poly gate, and then overlay the poly gate electrode with one or more metal layers after the remaining features have been masked with a dielectric or photoresist. The entire structure is then annealed, that is sufficiently heated for a sufficient length of time in order to combine all of the poly with the metal, down to the gate dielectric. A gate constructed in this or similar fashion is sometimes referred to as a fully-silicided (FUSI) gate because all of the poly material is consumed in the process.
These FUSI metal gates perform satisfactorily in many respects, but sometimes present a problem with attaining the proper work function, especially in PMOS devices. The work function basically describes the energy needed to move an electron in the solid atom from an initial Fermi energy level to vacuum level, that is, to outside the atom. Work function is a metric commonly applied to gate structures in transistors. An un-silicided poly gate, for example, commonly has a work function of approximately 5.0 eV. The work function in effect determines the threshold voltage at which the device will turn on or turn off. Silicided PMOS devices are frequently not able to obtain an acceptably high work function of, for example, 4.8 eV. This may result in a higher device threshold voltage, for example 0.2V, which may frustrate applications involving low-threshold-voltage logic.
Needed then is a way to achieve the advantages gained through the use of FUSI metal gates in semiconductor devices such as transistors while at the same time achieving a desirable work function that will permit exploitation of multi threshold voltage applications without the need for more (or more extensive) pocket or channel implants. The present invention provides just such a solution.
These and other problems are generally solved or circumvented, and technical advantages are generally achieved, by preferred embodiments of the present invention, which are directed to a PMOS device that uses a fully-silicided (FUSI) metal gate having a desirable work function value.
In accordance with a preferred embodiment of the present invention, a PMOS device includes a gate structure fabricated on a substrate, adjacent to a source region and a drain region that are formed in or on the substrate. The gate structure includes a gate electrode separated from the substrate by a dielectric material. The gate electrode, which is preferably less than 1000 Å in thickness, comprises a boron-doped silicide to form a low threshold voltage gate. The silicide is an alloy of polycrystalline silicon (poly), nickel and platinum. The silicide is formed in rapid thermal anneal (RTA) process that leaves a peak platinum region at or near the interface between the gate dielectric and the gate electrode. In one multi-threshold embodiment, the PMOS device also includes a second gate structure fabricated on the substrate adjacent to a second source region and a second drain region. The second gate structure is fabricated identically or similar to the first gate structure described above, except that the gate electrode is not boron doped. In this embodiment, the first or sole gate forms a low threshold voltage MOSFET, and the second gate forms a high threshold voltage MOSFET.
In accordance with another preferred embodiment of the present invention, a method for fabricating a semiconductor device comprises providing a substrate, fabricating a gate structure on the substrate, the gate structure having a gate dielectric and a gate electrode, wherein the gate electrode comprises a boron-doped silicide to form a low threshold voltage gate. The silicide is formed by forming a poly gate portion, doping the poly gate portion with boron, forming a metal layer of nickel and 5% platinum over the poly portion, and forming a layer of titanium nitrate over the nickel-platinum layer. The process continues with performing a first RTA, removing any un-reacted metal, and performing a second RTA to form a fully-silicided (FUSI) gate electrode. A source region and a drain region are formed in the substrate adjacent to the gate structure. The method may also include forming on the substrate a second PMOS gate structure having a nickel-rich platinum silicon gate electrode having a platinum peak at or near the interface of the second gate structure and a gate dielectric layer that separates the second gate structure from the substrate. A second source region and a second drain region are formed adjacent to the second gate structure to create a high threshold voltage PMOS device.
An advantage of a preferred embodiment of the present invention is the PMOS device may be used in a multi threshold environment, using a high threshold voltage PMOS device similar or identical to the low threshold voltage device except that it is not boron doped.
As more complete appreciation of the present invention and the scope thereof can be obtained from the accompanying drawings that are briefly summarized below, the following detailed description of the presently preferred embodiments of the present invention, and the appended claims.
For a more complete understanding of the present invention, and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawing, in which:
a though 5d are a series of drawings illustrating in cross-section selected stages in the fabrication of PMOS device according to an embodiment of the present invention.
The making and using of the presently preferred embodiments are discussed in detail below. It should be appreciated, however, that the present invention provides many applicable inventive concepts that can be embodied in a wide variety of specific contexts. The specific embodiments discussed are merely illustrative of specific ways to make and use the invention, and do not limit the scope of the invention.
The present invention will be described with respect to preferred embodiments in a specific context, namely a PMOS device having a nickel-rich fully silicided (FUSI) metal gate. A nickel-rich FUSI metal gate is one in which substantially all of the original poly has been consumed in the silicidation process, and where the resulting gate electrode material has more nickel than silicon. The invention may also be applied, however, to PMOS devices made of similar material as well. The PMOS device may, for example, be one of the transistors in a CMOS (complementary metal-oxide semiconductor) device, which typically also includes an NMOS device as well. Although the present invention provides little or no advantage for NMOS devices, it is of advantage to the overall CMOS device in which the two (or more) transistors are incorporated.
In one embodiment the present invention is a low threshold voltage device. As explained above, many semiconductor devices include both high and low threshold voltage devices in view of the power-saving advantages that may be obtained through their application. On such low voltage threshold device is illustrated in
In this embodiment, the source region 112 includes a shallow extension 113 that extends under the gate electrode 125 and, correspondingly, the drain region 116 includes a shallow extension 117 that extends under the gate electrode 125. The source and drain regions, including their respective extensions, define a channel 115 across which current may flow when PMOS device 100 has been activated. In the illustrated embodiment, silicon germanium (SiGe) portions 114 and 118 have been created in, source region 112 and drain region 116, respectively. This may be done to impose a physical stress region affecting surrounding materials and improving their desirable characteristics. Nickel silicide contact regions 111 and 119 have, in this embodiment, each been formed over a respective one of silicon germanium portion 114 or 118.
In the embodiment of
In accordance with this embodiment the gate electrode is also boron-doped. In one embodiment, a peak boron region is also formed (but not shown in
A multi threshold-voltage embodiment will now be discussed.
In the embodiment of
In this embodiment, the source region 212 includes a shallow extension 213 that extends under the gate electrode 225 and, correspondingly, the drain region 216 includes a shallow extension 217 that extends under the gate electrode 225. The source and drain regions, including their respective extensions, define a channel 215 across which current may flow when PMOS device 201 has been activated. In the illustrated embodiment, silicon germanium portions 214 and 218 have been created in, of source region 212 and drain region 216, respectively. This may be done to impose a physical stress region affecting surrounding materials and improving their desirable characteristics. Nickel silicide contact regions 211 and 219 have, in this embodiment, been each formed over a respective one of silicon-germanium portions 214 or 218.
In the embodiment of
In accordance with this embodiment of the present invention, the gate electrode 225 is not boron-doped. It has been found that a the non-boron-doped nickel-rich platinum silicon metal fabricated in accordance with the parameters above may achieve a work function of about 4.93 eV and have a threshold voltage of about −0.41 volts, making it very suitable as the high voltage threshold device in a multi-threshold application. Note again, however, that no particular result is a requirement of the present invention unless explicitly recited. A method of fabricating a device according to the present invention will now be described.
A poly re-oxidation is then performed (step 412) to form an oxide layer about 30 Å in thickness. The oxide layer may simply be deposited or may be formed through oxidation of the surface of the existing poly material. A second poly layer may then be formed (step 415), preferably to about 800 Å in thickness. A gate hard mask layer is then deposited (step 418), and a photoresist layer is formed and patterned (step 421). The photoresist structures that remain after patterning protect those portions of the gate stack layers that are to remain to form the gate stacks themselves. The gate stacks may now be created by an etching process (step 424).
In the embodiment of
In the embodiment of
At this point the poly gates may now be silicided. This may involve, as for example in the embodiment of
In this embodiment, a photoresist mask is formed and patterned to cover one of the two gate electrode (step 454), and second sacrificial oxide layer is formed (step 457), preferably to a thickness of about 40 Å. This second sacrificial layer remains in place for the boron doping of the exposed gate electrode (step 460). The boron doping is preferably done at an energy level of about 350 eV at a concentration of approximately 3×1015. In another embodiment (not shown) gate electrode doping may be performed prior to silicidation.
Returning to the embodiment of
Another illustration of the present invention is provided in
As should be apparent, the configuration of
In the embodiment of
In this embodiment, a first and a second RTA are then performed, with any excess that is un-reacted metal being removed in between the first RTA and the second RTA. A photoresist mask 645 (see
A photoresist layer is then, in this embodiment, formed and pattered to protect the gate structures during source and drain silicidation. The silicidation of the source and drain regions may then be undertaken. Source and drain silicidation proceeds similarly to the process described above in regard to gate silicidation, with the deposit of one or more metal layers, an RTA, and removal of excess metal. It is not necessary or even desirable, however, to silicide the entire source or drain region. The remaining photoresist layer is then removed; resulting configuration is illustrated in
Although the present invention and its advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims. For example, other materials consistent with the devices and methods of the present invention may be used in place of those mentioned above. And method steps may be performed in any logically consistent order.
Moreover, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification. As one of ordinary skill in the art will readily appreciate from the disclosure of the present invention, processes, machines, manufacture, compositions of matter, means, methods, or steps, presently existing or later to be developed, that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized according to the present invention. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, or steps.
