Patent Application
20070243722
The foregoing advantages and features of the invention will become apparent upon reference to the following detailed description and the accompanying drawings, of which:
In Example 1, the manufacturing method of an n-type SiC-MOS capacitor according to the invention will be explained. Change in conduction type allows a p-type SiC-MOS capacitor to be manufactured in the same way as that in Example 1 explained below. Furthermore, by forming parts such as a drain, a source electrode and a gate electrode with a publicly known method, a device such as an n-channel or a p-channel MOSFET can be easily manufactured.
First, an alumina boat is prepared. Upstream from the boat, a SiC dummy substrate (which is not necessarily a single crystal) is disposed on which a 5 mm thick SiO2 has been deposited. The width of the dummy substrate sample to a gas flow is taken as at least wider than the width (50.8 mm in diameter) of a later described SiC substrate sample to be originally processed, 55 mm square, for example. Downstream from the boat, the SiC substrate sample is disposed for manufacturing the n-type SiC-MOS capacitor according to the invention.
In Example 1, for SiC substrate samples for forming n-type SiC-MOS capacitors according to the invention, an n-type 4H—SiC (0001)Si, (000
The heat treatment system used for forming the n-type SiC-MOS capacitor according to the invention by using the SiC substrate samples with the SiO2 formed thereon has a structure in which a reaction tube of alumina passes through a cylinder-like resistance wire heating region surrounded with thermal insulation. Except that the reaction tube is made of alumina that allows temperature to be elevated up to 1800° C., the structure is similar to an oxidation furnace and a diffusion furnace used generally in a wafer process of a Si substrate. However, both ends of the reaction tube are sealed by flanges so that no air (particularly oxygen) is mixed in. The SiC substrate samples are mounted on an alumina boat and inserted into the reaction tube. For loading and unloading the boat, an alumina rod is used. The alumina rod is sealed by an O-ring provided at an opening at the end of the reaction tube so that no air is mixed in the reaction tube. While high purity Ar or another inert gas such as He at atmospheric pressure flows at 0.1 slm, for example, the temperature of the heating section at the center of the reaction tube is raised to a specified temperature (1740° C.). During this, the alumina boat with the SiC substrate samples mounted thereon is held while being preheated at a low temperature section downstream of the reaction tube (outside the heating section). The temperature at this time is on the order of 600° C. or less.
When the temperature of the heating section of the reaction tube becomes a specified temperature, the boat is inserted into the heating section and the Ar flow rate is immediately reduced to 0.01 slm. This is because when a temperature is high a high vapor pressure of SiO2 causes all of the SiO2 disposed upstream to be evaporated unless the Ar flow rate is reduced. After the temperature of the boat is raised to near a specified temperature, the boat is held for another 5 minutes at the temperature to bring the SiO2 formed on the surface of the SiC substrate sample into a molten state. Then, with the Ar flow rate increased to 0.1 slm, the boat is immediately taken out to the low temperature section to be rapidly cooled. While the boat is being cooled, the set temperature of the heating section is reduced to 1140° C. When the temperature of the heating section is 1140° C., the boat is inserted into the heating section again and kept at 1140° C. for 15 minutes. In this case, no Ar flow rate control is necessary. Thereafter, the temperature is reduced to 600° C. at a rate of 5° C./min. When the temperature becomes 600° C., the boat is returned to the low temperature section downstream from the reaction tube to be naturally cooled until the temperature is low enough to allow the boat to be taken out. In this way, the SiC substrate samples heat treated according to the invention were formed. An Al film was deposited by sputtering on a SiO2 on both the heat treated SiC substrate samples and SiC substrate samples that were not heat treated. The deposited Al films were then subjected to patterning by wet etching, by which a MOS capacitor was formed.
A comparison was made between SiC substrate samples subjected to heat treatment and comparison SiC substrate samples that were not subjected to heat treatment by carrying out the following analysis. The comparison was made to ascertain to what extent suboxides and carbon clusters due to carbon are removed and to what extent an interface state density is decreased at a SiO2/SiC interface of the n-type SIC-MOS capacitor according to the invention by carrying out the heat treatment. The analysis was carried out by cross section observation under a TEM (Transmission Electron Microscope) and composition analysis with EELS (Electron Energy Loss Spectroscopy). As a result, the following was found.
In a SiC substrate sample for comparison with SiO2 being formed by dry oxidation and wet oxidation but without being subjected to the heat treatment, there were observed regions with the presence of a mixture of Si atoms, C atoms and O atoms (suboxides) at the SiO2/SiC interface and, on the SiO2 side near the interface, there were observed deposits of carbon. In a SiC substrate sample for comparison with SiO2 being formed by using TEOS, but without being subjected to the heat treatment, mixing of carbon was observed over the whole SiO2, but no suboxides were found. Furthermore, in a SiC substrate sample for comparison with a SiO2 being formed with an HTO and a LTO but without being subjected to the heat treatment, neither the mixing of C (carbon) nor suboxides were recognized. The above results were approximately the same as those generally well-known.
In the SiC substrate sample heat treated at 1740° C. according to the invention, neither the mixing of C (carbon) nor suboxides were recognized in any of the cases of using the methods of forming the SiO2 regardless of the method of forming the SiO2 itself. However, from the whole SiO2, Na and transition metals were detected. They are regarded as metal impurities due to the use of the boat and reaction tube of alumina.
For comparison, an observation was made about a SiC substrate sample for comparison prepared by a method not included in the invention in which only heat treatment temperatures were changed from those in the heat treatment method according to the invention to be lower as 1290° C. and 1440° C. The result was rather similar to the result about the SiC substrate sample for comparison without being subjected to heat treatment. Namely, in the SiC substrate sample for comparison without being subjected to heat treatment in which the mixing of carbon and suboxides were observed, the mixing of carbon and suboxides were also observed even though the substrate sample was subjected to heat treatment at 1290° C. However, there was a difference in that the amounts of the mixing of carbon and suboxides were lower than those observed when the substrate sample was subjected to no heat treatment. Moreover, the substrate sample subjected to heat treatment at 1440° C. was different in that the mixing of carbon and suboxides was further lowered. However, partial deposition of SiO2 microcrystals was also observed therein. This causes degradation in insulation strength. Therefore, the heat treatment carried out at the temperature is not included in the manufacturing method according to the invention.
Next, current to voltage characteristics were measured for a MOS capacitor formed by the manufacturing method according to the invention and a MOS capacitor formed by a manufacturing method that was not according to the invention. The MOS capacitor according to the invention, in which the heat treatment temperature was kept at 1740° C. to convert SiO2 to a molten state before rapidly decreasing the temperature to rapidly cool the capacitor, had an insulation breakdown electric field strength of the order of 10 to 11 MV/cm. In a MOS capacitor in which the heat treatment temperature was kept at 1440° C., and SiO2 was not converted to a molten state before the temperature was rapidly reduced to rapidly cool the capacitor, the insulation breakdown electric field strength was low, of the order of 5 to 8 MV/cm or less. This was due to deposition of microcrystals as explained before. In a MOS capacitor in which the heat treatment temperature was 1290° C., the insulation breakdown electric field strength was high, of the order of 8 to 10 MV/cm for the capacitor with a thermal oxide film formed by either dry oxidation or wet oxidation. For the capacitor with a deposited thermal oxide film formed by CVD, the insulation breakdown electric field strength was low, of the order of 3 to 7 MV/cm, regardless of deposition method. It is considered that a deposited oxide film has a tensional stress applied thereto in many cases by the SiC semiconductor substrate and the stress is insufficiently relaxed by a short time heat treatment in a non-oxidizing atmosphere making it impossible to obtain sufficient insulation strength.
Hysteresis due to mobile ions such as Na ions was observed regardless of heat treatment temperatures in the measurement of capacitance to voltage characteristics for the MOS capacitor subjected to the heat treatment according to Example 1 of the invention. In other respects, favorable characteristics were obtained with interface state densities obtained by Terman's method being below the minimum detectable value of Terman's method (taken as being on the order of 1012 cm−3). It is considered that the interface state is neutralized by mobile ions such as Na ions.
As was explained in the foregoing, when heat treatment was carried out by using a reaction tube of alumina an unfavorable interface state may become favorable as a result of neutralization by metal impurities due to alumina. Thus, the favorable interface state is not necessarily caused by the effect of the heat treatment according to the invention. However, it can be said that high insulation strength evidently can be obtained by heating crystalline SiO2 above the melting point thereof. Moreover, it is evident from the result of the above-explained analysis that carbon clusters and suboxides are removed in the SiO2/SiC interface.
In Example 2, a manufacturing method of an n-type SiC-MOS capacitor according to the invention will be also explained. As in the Example 1, a modification in the conductivity type of a SiC substrate of course allows a p-type MOS capacitor and n-channel or p-channel MOSFET to be formed. In the following, explanations will be made with particular emphasis on the difference from Example 1.
In Example 2, a double tube of silica glass is used as a heat treatment system. The system has a structure in which cooling water is made to flow between the outer tube and the inner tube of the double tube. A SiC substrate sample with the SiO2 according to the invention formed thereon and a dummy sample are mounted on a high purity graphite susceptor coated with polycrystalline SiC. The susceptor is set on a susceptor holder of silica glass with a thick felt of high purity porous graphite put between so that the susceptor does not make direct contact with the double tube of silica glass. The susceptor holder is set in the inner tube of the double tube. In the heat treatment system, there is a danger that the graphite susceptor heated at an elevated temperature causes a steam explosion if the susceptor makes direct contact with the double tube. This is because the susceptor is set on the susceptor holder of silica glass with the felt of graphite put between. The heating of the graphite susceptor is carried out by induction heating in high purity Ar gas or another inert gas such as He at atmospheric pressure by feeding a high frequency current to a coil wound on the double tube. Since the graphite susceptor has a sufficiently small heat capacity, rapid increase or decrease in temperature is possible with sufficiently large electric power. For a graphite susceptor being on the order of several centimeters both in width and in length and on the order of 1 cm in thickness, high frequency power of as much as 30 kW can elevate the temperature of the susceptor from room temperature to 1750° C. within 3 minutes by selecting an adequate frequency. Temperature reduction is also characterized in that the temperature reduction from 1750° C. to 1140° C. can be carried out within 3 minutes. The heat treatment profile is the same as that in Example 1 except that the heat treatment temperature is kept at the specified heat treatment temperature (1740° C.) for 5 minutes before being set at 1140° C. with the high frequency power reduced and kept as being reduced.
The SiO2 in the SiC substrate sample subjected to the heat treatment by the method in Example 2 according to the invention was the same as that in Example 1 except that no Na or other metal impurities were detected in the composition analysis. There was no big difference in the current to voltage characteristics from those in Example 1.
The effect due to the high temperature heat treatment system according to Example 2 was definitely observed in the capacitance to voltage characteristics about the MOS capacitor subjected to the heat treatment by the method according to Example 2. There was observed little hysteresis due to mixing of Na as was observed in Example 1. Even though some hysteresis was observed, it was hysteresis due to electron trap (caused in the reverse direction to the direction of hysteresis due to mobile ions such as Na ions). An interface state density obtained by Hi-Lo method, the accuracy of which is higher than the accuracy in Terman's method, had a tendency to decrease as the heat treatment temperature was raised as 1290° C., 1440° C. and 1740° C. With a heat treatment temperature of 1740° C., the interface state density at 0.1 to 0.6 eV below the conduction band was 2×1011 cm−2/eV or less and, particularly at 0.2 to 0.6 eV below the conduction band, was 1×1011 cm−2/eV or less. These values are smaller by nearly two figures than the values of interface state densities reported for ordinary thermal oxide films.
The SiO2 can be solidified from a liquefied state under conditions under which no Na or other metal impurities are incorporated into the SiO2 by the method according to Example 2. Thus, the method according to Example 2 is excellent in that an interface state density can be decreased without relying on Na ions and the other mobile ions. Moreover, it was found that the insulation strength of the SiO2 was also high.
In Example 3, the manufacturing method of an n-type SiC-MOS capacitor according to the invention will be explained. As in Examples 1 and 2, a p-type MOS capacitor and n-channel or p-channel MOSFET can be formed. For Example 3, explanations will be made with particular emphasis on the difference from Examples 1 and 2.
The heat treatment system used in Example 3 is a system in which a hollowed heat insulator of high purity graphite is placed in a reaction tube of silica glass of a SiC epitaxial growth system and a high purity graphite susceptor coated with polycrystalline SiC is set inside the insulator to be provided as the heat treatment system for the SiO2 according to the invention. The graphite susceptor is horizontally grooved. Along the groove, a polycrystalline SiC substrate is placed. On the polycrystalline SiC substrate, a SiC substrate sample according to the invention and a dummy substrate are mounted (the dummy substrate is mounted upstream). The graphite susceptor is surrounded by a heat insulator with a large heat capacity, so that the temperature thereof is not decreased easily. Only the polycrystalline SiC substrate is pulled out by means of tongs, for example. The polycrystalline SiC substrate, having considerably smaller heat capacity compared with that of the graphite susceptor, is rapidly cooled. The heat treatment profile in Example 3 is the same as that in Example 1.
The composition, current to voltage characteristics and capacitance to voltage characteristics of the SiC-MOS capacitor subjected to the heat treatment in a non-oxidizing atmosphere such as that with high purity Ar or another inert gas such as He at atmospheric pressure with the profile being the same as that in Example 1 were approximately equal to those in Example 2.
In the heat treatment in Example 3, the SiO2 can be solidified from a liquefied state under conditions under which no Na or other metal impurities are incorporated into SiO2. Thus, the interface state density can be decreased without relying on Na ions and the other mobile ions. Moreover, the insulation strength of the SiO2 is also high. Furthermore, the heat treatment system is very practical, because it is capable of simultaneously processing a number of samples without danger of steam explosion as compared with the system in Example 2.
In Example 4, the manufacturing method of an n-type SiC-MOS capacitor according to the invention will be explained. As in Examples 1 to 3, a p-type MOS capacitor and n-channel or p-channel MOSFET can be formed. In Example 4, explanations will be made with particular emphasis on the difference from Examples 1 to 3. In each of the methods in the previous Examples 1 to 3, the SiC substrate sample is subjected to heat treatment with the heat treatment profile of raising a temperature to liquefy the SiO2 and then rapidly decreasing the temperature to rapidly cool the SiO2. In the method in Example 4, there is a significant difference from Examples 1 to 3 in that the SiO2 is heated up to a temperature lower than the temperature that liquefies SiO2 and then rapidly cooled. This will be explained in the following.
In Example 4, a heat treatment system similar to that in Example 3 is used. The difference from the system in Example 3 is that SiH4 flows together with Ar as non-oxidizing atmospheric gases at heat treatment. An excessive SiH4 flow rate causes either deposition of polycrystalline Si or adhesion of fluid Si depending on temperature (referred together to as adhesion of Si). This, however, is not a fatal problem. This is because adhered Si can be selectively removed by using intermediate pressure plasma producing fluorine radials without causing ion irradiation onto a formed SiO2 and, when the formed SiO2 is used as a gate insulator film for a device such as a MOSFET, can also be used as gate polysilicon. As in Example 3, the dummy substrate is mounted upstream from the sample.
In Example 4, by using a heat treatment system similar to that used in Example 3, the temperature of the SiC substrate sample is raised up to 1440° C. while making Ar, for example, flow at a flow rate of 0.1 slm and, along with this, making SiH4 flow at a flow rate of 0.1 to 1.0 slm. The SiC substrate sample, after being kept at 1440° C. for a specified time, is once pulled out to a lower temperature section and is rapidly cooled. Thereafter, the SiC substrate sample is inserted again into the heating section the temperature of which is reset at 1140° C. for gradually cooling. The treatment of the SiC substrate sample after being kept for 15 minutes at the gradual cooling temperature of 1140° C. is similar to that in Example 1.
The upper limit of the heat treatment temperature in Example 4 is 1450° C. This is because a heat treatment temperature exceeding 1450° C. unfavorably causes the vapor pressure of SiO2 to be excessively high. The lower limit of the heat treatment temperature is 1250° C. This is because a heat treatment temperature less than 1250° C. causes the diffusion velocity of Si in the SiO2 to be too small, which provides no practicality in the aspect of efficiency.
In Example 4, even in the SiC substrate sample heat treated at 1440° C., neither mixing of C (carbon), nor the presence of suboxides, nor further generation of SiO2 microcrystal as was explained in Example 1 can be recognized regardless of the methods of forming the SiO2. Moreover, a comparison of the interface state densities of the SiC substrate samples with those obtained at the same treatment temperature in Example 3 showed that each of the SiC sample substrates subjected to the heat treatment in Example 4, including the SiC substrate sample heat treated with the temperature 1440° C. changed to 1290° C., had a smaller interface state density. In other words, the method according to Example 4 is characterized in that an interface state density can be decreased without carrying out heat treatment at an elevated temperature such as 1740° C. as in the case of Example 3.
In Example 4, silane gas was used as a silicon producing gas. However, other hydrogenated silicon gases can be used. For the other silicon producing gases, when the gases cause no oxidation of SiC, gases such as evaporated gas of Si and Si oxide gases that causes no oxidation of SiC can be used.
It is considered that according to Example 4, diffusion of Si atoms in SiO2 causes no production of such SiO2 microcrystals as to increase the interface state density and the diffused Si atoms are removed by reacting with carbon impurities and suboxides to result in a decrease in interface state density. Moreover, the method according to Example 4, compared with the methods according to Examples 1 to 3, has the advantage of decreasing an interface state density without using such an abnormally high temperature as 1740° C.
In Example 5, an n-channel lateral MOSFET, a cross sectional view of the principal part of which is shown in
The manufacturing method of the n-channel lateral MOSFET will be explained. A 4H—SiC (0001)Si and (000
Next, gate oxide film 6 is formed by using any one of the methods of forming SiO2 described in Examples 2 to 4 and the heat treatment method according to the invention. The thickness of gate oxide film 6 was made uniform to on the order of 80 nm. Subsequently, polysilicon doped with highly concentrated phosphorus is deposited on gate oxide film 6 (phosphorus may be driven in after undoped silicon is deposited) and then etched back, by which gate electrode 7 is formed. In forming gate oxide film 6 by the method described in Example 4, when polysilicon is deposited from the beginning, the polysilicon may be used to form gate electrode 7. The specified sections of gate oxide film 6 are etched to provide opening sections, in which Ni is deposited by sputtering. The deposited Ni is then patterned to provide source electrode 8 and drain electrode 9, which are thereafter heated at 1000° C. in an Ar atmosphere to obtain ohmic contact. Note that the above-described values such as those of directions of crystal planes (including the off angle), the doping densities, film thicknesses and the implantation depths are only exemplified ones.
The value of channel mobility of the formed n-channel lateral MOSFET shown in
Example 6 relates to an n-channel vertical MOSFET, a cross sectional view of the principal part of which is shown in
The manufacturing method of the n-channel vertical MOSFET will be explained. A 4H—SiC (0001)Si and (000
Following this, the surface of n-type drift layer 13 is covered with an appropriate mask material, which is then appropriately patterned. Then, ion implantation with phosphorus ions is carried out into a region to a depth of 0.4 μm from the surface of n-type drift layer 13 together with layers 12 and 13 and the mask material to form n+-type source contact region 15, with SiC substrate 11 heated at 800° C., for example, so that the implanted ions form a box profile with an averaged density of 1×1021 cm−3. Similarly, ion implantation with aluminum ions is carried out with the use of an appropriately patterned mask material into a region to a depth of 0.4 μm from the surface of n-type drift layer 13 together with the layers 12 and 13 and the mask material, with SiC substrate 11 heated at 500° C., for example, to form p+-type body contact region 16, so that the implanted ions form a box profile with an averaged density of 1×1021 cm−3. After the mask materials are removed, annealing to activate the implanted ions is carried out in an Ar atmosphere at 1800° C. to form p-type body region 14, n+-type source contact region 15, and p+-type body contact region 16. At this time, the surface of n-type drift layer 13 is preferably capped with carbon to prevent the surface from becoming rough.
Next, the specified sections of gate oxide film 18 are etched to provide opening sections in which Ni is deposited by sputtering. The deposited Ni is then patterned to be provided as source electrode 23. Also on the principal surface on the opposite side of SiC substrate 11, with an oxide film being removed, Ni is deposited by sputtering as drain electrode 22. Electrodes 22 and 23 are thereafter heated at 1000° C. in an Ar atmosphere to obtain ohmic contact. Note that the above-described values such as those of directions of crystal planes (including the off angle), the doping densities, film thicknesses and the implantation depths are only exemplified ones. The design breakdown voltage of the MOSFET in Example 6 is 1.2 kV.
The on-resistance of the formed vertical MOSFET was 8.8 to 9.0 mΩcm2. While, the resistance obtained from a TEG (Test Element Group) for evaluation, formed together with the MOSFET in the same wafer at the same time, was on the order of 8.5 mΩcm2 about the sections other than MOS channel 20. Therefore, the value of the channel resistance of the MOSFET becomes 0.3 to 0.5 mΩcm2 which is calculated by subtracting the value 8.5 mΩcm2 from the on-resistance of the MOSFET of 8.8 to 9.0 mΩcm2. Thus, it is known that the ratio of the channel resistance component to the whole on-resistance can be reduced down to on the order of 0.5%.
In a previous vertical SiC MOSFET, the channel resistance component occupied 30 to 50% of the on-resistance. Therefore, in the MOSFET in Example 6 according to the invention, the channel resistance ratio can be largely reduced.
As was explained above, according to Example 6, carbon impurities and suboxides that cause interface states are removed, by which channel mobility is enhanced, channel resistance is reduced and, as a whole, on-resistance can be decreased.
In Example 7, an n-channel trench MOSFET, a cross sectional view of the principal part of which is shown in
Source electrode 46 is provided on the surface of n+-type source contact region 36 in the direction along the surface of the substrate, so as to make ohmic contact with the surface. Source electrode 46, while covering the interlayer insulator film 44, is in contact with n+-type source contact region 36 in the adjacent cell. A part of source electrode 46 is in contact with p+-type body contact region 37 with a high impurity concentration, which region enters p-type body region 35. A drain electrode is in ohmic contact with the bottom surface of SiC substrate 31. Furthermore, in an actual device, an electric field limiting structure is provided at an end of the device (not shown). The explanation of this is not required for understanding the invention and will be omitted. About the manufacturing method of the vertical trench MOSFET previously shown in
N-type 4H—SiC substrate 31 with a (0001)Si 8° off plane taken as a principal surface thereof or n-type 4H—SiC substrate 31 with a (000
N+-type field stopping layer 32, n-type drift layer 33, n-type current spreading layer 34, p-type body region 35 and an n+-type source contact layer are deposited in order by epitaxial growth on substrate 31. After the epitaxial growth process, SiO2 with a thickness of approximately 2 μm is deposited on the surface on the source contact layer side by plasma CVD with TEOS and O2 used as source gases. The deposited SiO2 is formed as a SiO2 mask for ion implantation by photolithography process and plasma etching. Thermal oxidation is then carried out in a wet atmosphere at 1000° C. to 1200° C. for a specified time, for example 30 minutes, to form a screen oxide film with a thickness of approximately 10 nm.
Ion implantation with aluminum ions is carried out to a depth of 0.4 μm from the undersurface of the screen oxide film, with the substrate sample heated at 500° C., so that the implanted ions form a box profile with an averaged density of 1.5×1021 cm−3. Then a photoresist is applied again, which is heated at 800° C. in an Ar flow to carbonize and provide a carbon cap. In this state, by keeping the substrate sample at 1800° C. for 5 minutes in an Ar flow, aluminum ions introduced by ion implantation are activated. The substrate sample is kept at 800° C. in an O2 flow to remove the carbon cap.
By the processes up to this point, p+-type body contact region 37 is formed in a part of the source contact layer. The remaining part of the source contact layer becomes n+-type source contact region 36.
After SiO2 with a thickness of approximately 3.7 μm is deposited on p+-type body contact region 37 side surface of the substrate sample by plasma CVD, a mask pattern of the SiO2 for forming the trench is formed by a photolithography process and plasma etching. By ICP (Inductively Coupled Plasma) etching (RIE: Reactive Ion Etching) with SF6 and O2 taken as reactive gases, trench 38 is formed which reaches n+-type field stopping layer 32. A maximum of the ratio of the etching rate of SiC to that of SiO2 (selective ratio) is on the order of 2.3. Therefore, with SiO2 with a thickness of approximately 3.7 μm used as a mask, trench 8 reaching n+-type field stopping layer 32 at a depth of a little less than 8 μm can easily be formed. By forming a sacrifice oxide film with a thickness of approximately 40 nm and subsequently removing it, the inside surface of trench 38 is cleaned.
Trench 38 is filled with a SiO2 or an insulator including SiO2 as the main component. After trench 38 is filled with the SiO2, the SiO2 is heated to convert it into a molten state and make it dense. Therefore, in the step of forming the SiO2, it is necessary only that the whole volume of SiO2 is larger than the whole volume of trench 38. Thus, it is not necessary for the SiO2 to be uniformly and densely deposited in trench 38, so that a simplified deposition method can be employed.
Next, the deposited SiO2 is heated up to 1740° C. by the heat treatment method described in Example 2 or 3. At this time, the SiO2, is liquefied and flows into trench 38. When the temperature is lowered, the SiO2 solidifies to uniformly fill trench 38. Subsequent to this, polishing is carried out for planarization with the principal surface of the SiC used as an etching termination surface. The use of silica as abrasives causes the SiO2 to be shaved, but SiC, being far harder than silica, is barely shaved. However, when the temperature of SiC is raised by polishing, the surface of SiC is oxidized to allow the surface to be shaved. Therefore, care must be taken so as not to excessively raise the temperature.
When the SiO2 remaining on the SiC surface is sufficiently flat with the thickness thereof known by a detection method of some kind, the SiO2 may be polished by RIE (Reactive Ion Etching) with an etching gas such as CHF3 used without carrying out polishing. Finally, the SiO2 is etched back to a specified depth, by which burial of insulator 47 in trench 38 is completed. For the etching back, plasma etching may be carried out with CHF3 used as a reactive gas. Because of the presence of some conditions under which the selectivity of SiO2 to SiC becomes 40 or more, the SiC can be safely made exposed on the principal surface. However, in some cases, CHF3 forms a polymerized film on the surface of a SiC. In this case, the polymerized film must be removed later by O2 plasma.
By plasma CVD with TEOS and O2 used as source gases, a SiO2 is formed on the sidewall of trench 38 with a thickness of approximately 10 nm. By carrying out high temperature heat treatment at 1300° C. for 1 hour with 10% N2O diluted with N2, the SiO2 on the sidewall surface is provided as gate oxide film 39.
The high temperature heat treatment at 1300° C. is preferable because the treatment brings the advantages of enhanced breakdown voltages and improved interface characteristics to not only the gate insulator film but also to the SiO2 buried in the trench, namely the buried insulator and a SiO2 left on the principal surface before the gate oxide film is deposited.
The processes after this are almost the same as those of forming a Si trench MOSFET except that the contact with SiC is made with Ni and high temperature annealing of the order of 1000° C. is carried out. Following the gate oxide film forming process, the trench is filled by depositing polysilicon including phosphorus with a high concentration. The polysilicon is then etched back to a specified depth to be formed as gate electrode 40. Thereafter, interlayer insulator film 44 is deposited, a contact hole is formed, and Ni is deposited on both of interlayer insulator film 44 and the bottom surface of substrate 31, by which source electrode 46 and drain electrode 45 are formed. By forming Al films on a gate pad and source electrode 46, the trench MOSFET is made completed.
The thus formed trench MOSFET can enhance averaged breakdown voltage due to a reduction in negative fixed charges, apparently possessed by insulator 47 buried in trench 38, which reduction is caused by a decrease in the interface state density at the SiO2/SiC in the sidewall surface of trench 38.
As described above, according to Example 7, the decrease in the interface state density at the SiO2/SiC in the sidewall surface of trench 38 enhances breakdown voltage. Moreover, the process of burying insulator 47 in trench 38 is simplified.
While the present invention has been particularly shown and described with reference to preferred embodiments thereof, it will be understood by those skilled in the art that the foregoing and other changes in form and details can be made therein without departing from the spirit and scope of the present invention.
| Number | Date | Country | Kind |
|---|---|---|---|
| JP 2006-114793 | Apr 2006 | JP | national |
