Patent Grant
11056562
The present invention relates to silicon carbide semiconductor devices.
Patent Document 1 discloses a power semiconductor device that suppresses dielectric breakdown between a gate electrode and a source electrode while a metal-oxide-semiconductor field-effect transistor (MOSFET) switches. Changing a voltage applied to the gate (gate pad) of the MOSFET so that the MOSFET switches from ON to OFF abruptly raises a voltage applied to the drain (drain electrode) of the MOSFET from substantially zero volts to several hundred volts. As indicated by an arrow in FIG. 7, the voltage rise causes a displacement current to flow through both p-type and n-type impurity regions, thus producing a potential difference under the gate pad. Patent Document 1 describes electrically connecting a second well region to a source pad via a second well contact hole that reaches the second well region within a drift layer below the gate pad, to thus feed the displacement current, which flows through the second well region, into the source pad.
The second well contact hole can suppress the potential difference under the gate pad. For a large gate pad or for rapid switching, however, the second well contact hole cannot sufficiently suppress the potential difference, thus possibly involving the dielectric breakdown of an insulating film under the gate pad.
A semiconductor device using a wide-bandgap semiconductor, especially a silicon carbide semiconductor device includes a p-type region under a gate pad, the p-type region being commonly formed through implantation of aluminum (Al) or boron (B) ions. Al or B, when injected into silicon carbide, has a deep impurity level; in addition, the recovery of a defect resulting from ion implantation is difficult. For this reason, the dose of Al or B is difficult to increase. In addition, a p-type region of a silicon carbide semiconductor device has a larger resistance than a p-type region of a silicon (Si) semiconductor device. As such, the silicon carbide semiconductor device tends to involve the dielectric breakdown of the insulating film under the gate pad when compared to the Si semiconductor device.
To solve this problem, it is an object of the present invention to provide a silicon carbide semiconductor device that suppresses the dielectric breakdown of an insulating film under a gate pad.
A silicon carbide semiconductor device according to the present invention includes the following: a semiconductor substrate of silicon carbide; a first impurity region having a second conductivity type and selectively disposed in the upper layer of the semiconductor layer; a second impurity region having the first conductivity type and selectively disposed in the upper layer of the first impurity region; a gate insulating film provided to be continuously in contact with the second impurity region, the first impurity region, and the semiconductor layer; a gate electrode disposed in a position facing the second impurity region, the first impurity region, and the semiconductor layer via at least the gate insulating film; a third impurity region having the second conductivity type, the third impurity region being disposed in the upper layer of the semiconductor layer in an outer peripheral region that is the outer periphery of a cell arrangement region in which a unit cell including the first and second impurity regions is disposed; a field insulating film that is disposed on the semiconductor layer in the outer peripheral region, and is thicker than the gate insulating film; an interlayer insulating film disposed on the field insulating film, the gate electrode, and the gate insulating film; a first main electrode disposed on the interlayer insulating film; a second main electrode disposed across the semiconductor substrate from the semiconductor layer; and a gate wire and a gate pad electrically connected to each other via the gate electrode disposed on the field insulating film. The third impurity region includes a fourth impurity region having the second conductivity type, selectively disposed in the upper layer of the third impurity region, and having a higher impurity concentration than the third impurity region. The gate wire and the gate pad are disposed in the outer peripheral region. The fourth impurity region is provided to be adjacent to the cell arrangement region and to surround at least a region below the gate pad, and is electrically connected to the first main electrode.
The present invention suppresses the dielectric breakdown of the insulating film under the gate pad.
<Note>
A long ago, the term, “MOS” is used in a structure in which metal, an oxide, and a semiconductor are joined together, and is an abbreviation for a “metal oxide semiconductor”. In view of recent-year integration, improvement in fabrication processes, and other things, a field-effect transistor having a MOS structure (hereinafter simply referred to as a “MOS transistor”), in particular, includes a gate insulating film and a gate electrode that are made of improved material.
For instance, the MOS transistor includes a gate electrode of polycrystalline silicon instead of metal in order to form its source and drain in a self-aligned manner. Moreover, to improve electrical properties, the gate insulating film is made of a high-permittivity material, which is not always limited to an oxide.
As such, the term, “MOS” is not always used in only a stacked structure of metal, an oxide, and a semiconductor. Thus, the Description does not use this term based on such a limitation. That is, as a matter of technical common sense, the term, “MOS” herein is not only an abbreviation for its etymology, but also widely means a stacked structure of an electric conductor, an insulator, and a semiconductor.
Reference is made to conductivity types of impurity. N-type is generally defined as a “first conductivity type”; and p-type, as a “second conductivity type” in the following description. These definitions are reversible.
In the following description, the wording, “A and B are electrically connected to each other” means that a current flows between component A and component B.
<Device Configuration>
As illustrated in
A source electrode 10 (first main electrode) is disposed in most part of a main surface of the silicon carbide MOSFET 100 except in the locations where the gate pad 11 and the gate wire are disposed. The gate pad 11 is an island surrounded by the source electrode 10. Part of the source electrode 10 extends along two of the four sides of the gate pad 11 at a corner of the silicon carbide MOSFET 100. This part is called a source wire 13.
Disposed below the source electrode 10 is a cell arrangement region, identified as cell arrangement region C in
Various MOSFETs have various gate pads 11 with regard to position and number, have various gate wires 12 with regard to shape, and have various source electrodes 10 with regard to shape and number. Although the present invention is applicable to any form, the gate wire 12 needs to be disposed along any of the sides of the gate pad 11 that does not face the cell arrangement region in plan view.
A plurality of gate contact holes 23 are arranged under the gate pad 11 and the gate wire 12. Moreover, a plurality of source contact holes 22 are arranged under the source electrode 10 over the cell arrangement region so as to conform with the unit cell arrangement.
The following describes the configuration of a cross-section taken along line A-A in
The SiC substrate 1 has a front main surface provided with a semiconductor layer 2 containing a relatively low concentration (n) of n-type impurities. The semiconductor layer 2 is an epitaxial growth layer for instance, and is hereinafter called a drift layer 2 (semiconductor layer).
The drift layer 2 has an upper layer provided with a plurality of well regions 3 (first impurity regions) that contain p-type (second conductivity type) impurities in the cell arrangement region and that are selectively arranged. The well regions 3 have upper layers provided with contact regions 5 (fifth impurity regions) that contain a relatively high concentration (p+) of p-type impurities and that are selectively arranged. The contact regions 5 are surrounded by n+ source regions 4 (second impurity regions). The contact regions 5, although provided for reducing a contact resistance, are not essential components.
The well regions 3 and the source regions 4 each concentrically surround the contact region 5 in plan view; moreover, the depth of the well region 3 from the uppermost surface of the drift layer 2 is greater than the depth of the source region 4 and contact region 5 from the uppermost surface of the drift layer 2. The details will be described later on.
In an outer peripheral region, identified as outer peripheral region P in
In the cell arrangement region, a gate insulating film 6 is disposed on the drift layer 2; moreover, disposed on the gate insulating film 6 is a gate electrode 7. That is, a junction-field-effect-transistor (JFET) region is disposed between the edges on the upper surfaces of the adjacent well regions 3; moreover, the gate electrode 7 is disposed on the gate insulating film 6 extending from the JFET region to the edge of the well region 3.
In a region on the periphery of the cell arrangement region, disposed on the drift layer 2 is a field insulating film 14 with a thickness of 0.5 to 2 μm that is thicker than the gate insulating film 6. The gate electrode 7 is disposed also on the field insulating film 14.
The gate insulating film 6 covers almost the enter main surface of the drift layer 2 in the cell arrangement region. Not the gate insulating film 6, but a source contact film 19 is disposed in the upper part of the contact region 5 and part of the upper part of the surrounding source region 4.
An interlayer insulating film 15 having a thickness of 0.5 to 2 μm is disposed on the gate electrode 7, the gate insulating film 6, and the field insulating film 14. The source contact hole 22 is disposed in the cell arrangement region so as to extend through the interlayer insulating film 15 to the source contact film 19. The well contact hole 21 is disposed in the outer-periphery well region 9, in a region where the outer-periphery contact region 8 is disposed so as to extend through the interlayer insulating film 15 and the field insulating film 14 to the outer-periphery well contact film 18. The gate contact hole 23 is disposed in the outer peripheral region so as to extend through the interlayer insulating film 15 to the gate electrode 7 on the field insulating film 14.
The source electrode 10, the gate pad 11, and the source wire 13 are selectively disposed on the interlayer insulating film 15. The source electrode 10 fills the source contact hole 22 and the well contact hole 21 that is adjacent to the cell arrangement region. The gate pad 11 fills the gate contact hole 23. The source wire 13 fills the well contact hole 21 at the edge of the outer peripheral region. Accordingly, the source region 4 is electrically connected to the source electrode 10 via the source contact hole 22. Further, the outer-periphery well region 9 is electrically connected to the source electrode 10 (the source wire 13) via the well contact hole 21. Still further, the gate electrode 7 is electrically connected to the gate pad 11 via the gate contact hole 23.
Although not shown, a protective film of polyimide or nitride is disposed on the interlayer insulating film 15 so as to cover at least the source electrode 10.
The SiC substrate 1 has a back main surface (opposite the main surface provided with the drift layer 2) provided with a drain electrode 20 (second main electrode).
The following describes the configuration of a cross-section taken along line B-B in
Here, the shape of each impurity region in plan view will be described with reference to
As illustrated in
The outer-periphery contact region 8 also surrounds a region (not shown) below the gate pad 11. The outer-periphery contact region 8 in
The outer-periphery contact region 8 may be in any form. A plurality of discontinuous, local impurity regions may be disposed, as the outer-periphery contact regions 8, around the cell arrangement region and around the region (not shown) below the gate pad 11. In this case, the well contact holes 21 need to be provided to correspond to the respective outer-periphery contact regions 8.
With reference to
As illustrated in
The following describes an effect of the silicon carbide MOSFET 100. As earlier described with reference to
Let the silicon carbide MOSFET 100 switch from ON to OFF in such a configuration. Then, the displacement current, generated in the outer-periphery well region 9, also enters the outer-periphery contact region 8 below the source wire 13, and thus has a short path, as indicated by an arrow VC in
Here, as illustrated in
Furthermore, since the gate pad 11 in
<Modification>
As illustrated in
As earlier described with reference to
It is noted that the silicon carbide MOSFET 100A, which does not include the source wire 13 and the well contact holes 21 thereunder, can include the gate wire 12 that extends to be directly connected to the gate pad 11.
<Manufacture Method>
The following describes a method for manufacturing the silicon carbide MOSFET 100 with reference to
As illustrated in
The SiC substrate 1 is 50 to 500 μm thick, and contains n-type impurities in a range of 1×1019 to 1×1021 cm−3. The drift layer 2 is 1 to 60 μm thick, and contains the n-type impurities in a range of 1×1015 to 1×1017 cm−3. The thickness of the drift layer 2 is one example, and depends on a breakdown voltage (voltage to be uses) necessary for the silicon carbide MOSFET 100.
Formed onto the drift layer 2 is a resist mask (not shown) having openings so that regions to be the well regions 3 and the outer-periphery well region 9 are exposed, through photolithography. This resist mask is used as a mask for preventing impurity injection.
The resist mask, after formed, undergoes ion implantation of p-type impurities from above to thus selectively form the well regions 3 in the upper layer of the drift layer 2 in the cell arrangement region and to form the outer-periphery well region 9 in the upper layer of the drift layer 2 in the outer peripheral region. Here, the well region 3 and the outer-periphery well region 9 are 0.5 to 1.0 μm deep (thick) from the outermost surface of the drift layer 2. In addition, the p-type impurity is made of Al or B, and has a concentration ranging from 1×1017 to 5×1019 cm3.
After resist mask removal, another new resist mask (not shown) is formed that has openings so that regions to be the source regions 4 are exposed, through photolithography. This resist mask is also used as a mask for preventing impurity injection.
The resist mask, after formed, undergoes ion implantation of n-type impurities from above to thus form the source regions 4 in the upper layer of the well regions 3. Here, the source region 4 is 0.2 to 0.5 μm deep (thick) from the outermost surface of the drift layer 2. In addition, the n-type impurity is made of nitrogen (N) or phosphorus (P), and has a concentration ranging from 5×1018 to 5×1020 cm−3.
After resist mask removal, another new resist mask (not shown) is formed that has openings so that regions to be the contact regions 5 and the outer-periphery contact region 8 are exposed, through photolithography. This resist mask is also used as a mask for preventing impurity injection.
The resist mask, after formed, undergoes ion implantation of p-type impurities from above to thus form the contact regions 5 in the middle of the source regions 4 in the cell arrangement region and to form the outer-periphery contact region 8 in the outer peripheral region. Here, the contact region 5 and the outer-periphery contact region 8 are 0.2 to 0.5 μm deep (thick) from the outermost surface of the drift layer 2. In addition, the p-type impurity is made of Al or B, and has a concentration ranging from 1×1018 to 5×1020 cm−3.
After resist mask removal, another new resist mask (not shown) is formed that has openings so that regions to be the guard ring regions GR are exposed, through photolithography. This resist mask is also used as a mask for preventing impurity injection.
The resist mask, after formed, undergoes ion implantation of p-type impurities from above to thus form the guard ring regions GR in the upper layer of the drift layer 2 on the further outside of the outer-periphery well region 9. Here, the guard ring region GR is 0.5 to 1.0 μm deep (thick) from the outermost surface of the drift layer 2. In addition, the p-type impurity is made of Al or B, and has a concentration ranging from 1×1016 to 1×1018 cm3.
After resist mask removal, the drift layer 2 undergoes high-temperature annealing at 1500° C. or higher to activate the n-type and p-type impurities as injected.
Next, an oxide film (SiO2) is formed onto the drift layer 2 through, for instance, CVD. The subsequent step is forming, through photolithography, an etching mask having an opening so that the cell arrangement region is exposed, followed by removing the oxide film in the cell arrangement region through etching with the etching mask. This forms, as illustrated in
Then, in a process step illustrated in
It is noted that the gate insulating film 6, although being a thermally oxidized film in the above description, may be an oxide film formed through CVD.
The next step is forming a polycrystalline silicon film containing 1×1019 to 1×1021 cm−3 of phosphorus (P) onto the gate insulating film 6 and the field insulating film 14 through CVD. The polycrystalline silicon film is 0.3 to 1 μm thick. It is noted that the polycrystalline silicon film may be formed of a p-type polycrystalline silicon film containing B.
Subsequently, formed through photolithography is an etching mask having an opening where the polycrystalline silicon film above the source regions 4 and the contact regions 5 is exposed in the cell arrangement region, and having an opening where the polycrystalline silicon film below the gate pad 11 is exposed in the outer peripheral region. Then, the polycrystalline silicon film, exposed from these openings, is removed through etching with the etching mask. As illustrated in
The next step is forming a silicon oxide film having a thickness of 0.5 to 2 μm onto the enter surface of the SiC substrate 1 (including the aforementioned components) through, for instance, CVD. This silicon oxide film is the interlayer insulating film 15. Subsequently, an etching mask is formed that has openings so that the interlayer insulating film 15 above the contact regions 5 and the surrounding source regions 4 are exposed in the cell arrangement region. The following step is removing the interlayer insulating film 15, exposed in these openings, and the gate insulating film 6 under the interlayer insulating film 15 through etching with the etching mask. This removal forms the source contact holes 22 (
After etching-mask removal, a Ni film having a thickness of 30 to 100 nm is formed onto the front main surface of the SiC substrate 1 through, for instance, sputtering, followed by annealing. This forms a metal silicide film (herein, a NiSi2 film) in the upper parts of each source region 4 and each contact region 5, which are exposed to the bottom surface of the source contact hole 22, and in the upper part of the outer-periphery contact region 8, which is exposed to the bottom surface of the well contact hole 21.
Here, the Ni film undergoes heating at 300 to 800° C. for 1 to 3 minutes using a method, such as rapid thermal annealing (RTA). The heating at this range of temperature causes Ni in the Ni film to react to SiC in contact with the Ni film, thus forming the source contact film 19 (
After the silicide film formation, the SiC substrate 1 is cleaned in an acid solution containing sulfuric acid or hydrochloric acid. This cleaning process removes the Ni film that remains unreacted in the reaction for conversion into a silicide. Removing the unreacted Ni film obtains a configuration illustrated in
Subsequently, formed through photolithography is an etching mask having a plurality of openings so that the interlayer insulating film 15 above the gate electrode 7 in regions where the gate pad 11 (
After that, the front main surface of the SiC substrate 1 undergoes sputtering or vapor deposition to form an Al film having a thickness of 1 to 5 μm, followed by filling the well contact holes 21, the source contact holes 22, and the gate contact holes 23.
Next, formed through photolithography is an etching mask having openings in portions other than the upper parts of regions in which the source electrode 10, the gate pad 11, the gate wire 12, and the source wire 13 are to be formed. Then, the Al film undergoes etching using the etching mask to form the source electrode 10, the gate pad 11, the gate wire 12, and the source wire 13.
Finally, the back main surface of the SiC substrate 1 undergoes sputtering or vapor deposition to form a Ni film having a thickness of 0.1 to 5 μm. This Ni film is the drain electrode 20. Through these process steps, the silicon carbide MOSFET 100 in
As illustrated in
Such a configuration lowers the sheet resistance of the outer-periphery well region 9, thereby further suppressing the potential gradient when the displacement current flows.
The outer-periphery contact region 8, which has the same concentration and the same depth as the contact regions 5 in the cell arrangement region, is formed simultaneously with the contact regions 5. This simplifies the process steps in manufacture. It is noted that the terms, “the same concentration” and “the same depth” do not limited to an exact match; these terms include a margin of error ranging from −20 to +20%.
The silicon carbide MOSFET 100 in
A silicon carbide MOSFET 90 in
That is, the silicon carbide MOSFET 90 is configured such that the source wire 13 surrounds the outermost periphery of the SiC substrate 1, thus connecting the gate wire 12 to the gate pad 11, and that the source wire 13 extends along two of the four sides of the gate wire 12, at the corner of the silicon carbide MOSFET 90. As a matter of course, the outer-periphery contact region 8 is disposed below the source wire 13, and is electrically connected to the source wire 13 via the well contact holes 21.
The source wire 13 surrounds the outermost periphery of a chip including the silicon carbide MOSFET 90. Here, let the sum of W3 and W4 be 50 μm, where W3 denotes the width of the source wire 13, where W4 denotes the width of a gap between the gate wire 12 and the source wire 13. For a chip size of 1 cm×1 cm, the area of an invalid region is 50 μm×10 mm×4=2 mm2; thus the invalid region needs to make up about 2% of the entire chip. For a chip size of 3 mm×3 mm, the area of the invalid region is 50 μm×3 mm×4=0.6 mm2; and thus the invalid region needs to make up about 6.7% of the entire chip. SiC wafers, which are more expensive than Si wafers, involve an increase in invalid region, thus highly increasing manufacture cost. Hence, the invalid region should be as small as possible.
The silicon carbide MOSFET 100 in
That is, rapid operation, which is an advantage of a silicon carbide MOSFET, can cause a disadvantage, such as a noise generation phenomenon. In this case, integrating a gate resistor can regulate switching speed. This integration involves a gate resistor between a gate pad and a gate wire. The configuration in which the gate pad 11 is not directly connected to the gate wire 12 facilitates the integration of a gate resistor having a high resistance.
As illustrated in
That is, the gate pad 111 is adjacent to one corner of the silicon carbide MOSFET 300. In addition, the gate pad 112 is remote from the corner, and has an L-shape extending to face two orthogonal sides of the gate pad 111. The gate electrode 7 is disposed below the gate pad 111 and the gate pad 112 so as to extend between both. This gate electrode 7 is an integrated gate resistor.
As illustrated in
Width and length regulation or number regulation in the protrusion PP of the gate electrode 7 sets the resistance of the integrated gate resistor and regulates switching speed.
As a matter of course, the silicon carbide MOSFET 300, in addition to the aforementioned effect, reduces the potential difference under the gate pad resulting from the displacement current during switching, and thus suppresses the dielectric breakdown of the insulating film under the gate pad.
<Other Applications>
The first to third embodiments each disclose that a semiconductor device is a vertical MOSFET. As illustrated in
A SiC substrate of p-type instead of the SiC substrate 1 of n-type can achieve an IGBT.
The present invention, although applied to a planar-gate MOSFET in the first to third embodiments, is applicable to a trench-gate MOSFET and a trench-gate IGBT.
While the invention has been shown and described in detail, the foregoing description is in all aspects illustrative and not restrictive. It is therefore understood that numerous modifications and variations can be devised without departing from the scope of the invention.
It is noted that in the present invention, the individual embodiments can be freely combined, or can be modified and omitted as appropriate, within the scope of the invention.
| Filing Document | Filing Date | Country | Kind |
|---|---|---|---|
| PCT/JP2016/077944 | 9/23/2016 | WO | 00 |
| Publishing Document | Publishing Date | Country | Kind |
|---|---|---|---|
| WO2018/055719 | 3/29/2018 | WO | A |
| Number | Name | Date | Kind |
|---|---|---|---|
| 20130020587 | Hino | Jan 2013 | A1 |
| 20130026494 | Oritsuki | Jan 2013 | A1 |
| 20130175549 | Okumura | Jul 2013 | A1 |
| 20130313576 | Nakano | Nov 2013 | A1 |
| 20160163703 | Kaguchi | Jun 2016 | A1 |
| 20170092743 | Okumura | Mar 2017 | A1 |
| 20180308973 | Ebiike | Oct 2018 | A1 |
| Number | Date | Country |
|---|---|---|
| 2012-109602 | Jun 2012 | JP |
| 2011125274 | Oct 2011 | WO |
| Entry |
|---|
| International Search Report issued in PCT/JP2016/077944; dated Dec. 27, 2016. |
| An Office Action; “Notice of Reasons for Refusal,” issued by the Japanese Patent Office dated Jul. 9, 2019, which corresponds to Japanese Patent Application No. 2018-540551 and is related to U.S. Appl. No. 16/331,992; with English language translation. |
| An Office Action issued by the German Patent Office dated Aug. 17, 2020, which corresponds to German Patent Application No. 11 2016 007 257.0 and is related to U.S. Appl. No. 16/331,992 with English translation. |
| Number | Date | Country | |
|---|---|---|---|
| 20190259845 A1 | Aug 2019 | US |
