Embodiments of the invention relate to a silicon carbide semiconductor substrate, a method of manufacturing a silicon carbide semiconductor substrate, a silicon carbide semiconductor device, and a method of manufacturing a silicon carbide semiconductor device.
Single crystal silicon (Si) is conventionally used as a material of power semiconductor devices that control high voltages and large currents. Silicon power semiconductor devices include various types that are selectively used according to purpose. For example, PiN diodes (P-intrinsic-N diodes), bipolar transistors, and insulated gate bipolar transistors (IGBTs) are so-called bipolar devices. While these devices have a high current density, high-speed switching is not possible and, for example, the frequency usage limit is several kHz for bipolar transistors and about 20 KHz for IGBTs. On the other hand, while power metal oxide semiconductor field effect transistors (MOSFETs) can be used at high speeds up to several MHz, MOSFETs cannot handle large currents. Nonetheless, there is a strong demand in the market for large-current, high-speed power semiconductor devices and thus, IGBTs and power MOSFETs have been intensively developed and improved, and the performance of power devices has nearly reached the theoretical limit determined by the silicon material.
Further, other materials for power semiconductor devices have been investigated and silicon carbide (SiC) has recently attracted particular attention for next-generation power semiconductor devices excelling in terms of having low ON voltage, high-speed characteristics, and high-temperature characteristics. The reason why is that SiC is an extremely stable material chemically, has a wide band gap of 3.26 eV in an instance of 4H-SiC, may be used very stably as a semiconductor even at high temperatures, and further has a critical field strength that is at least one order of magnitude greater than that of silicon. SiC has a good possibility of exceeding the material limits of silicon and therefore, future growth in power semiconductor applications is expected to be significant.
As for silicon carbide semiconductor devices, Schottky barrier diodes (SBDs), planar gate structure and trench gate structure vertical metal oxide semiconductor field effect transistors (MOSFETs) have been commercialized.
In such silicon carbide semiconductor devices, an n−-type silicon carbide epitaxial layer is deposited on a front surface of an n+-type silicon carbide substrate as a drift layer. For example, on the n+-type silicon carbide substrate doped with nitrogen (N) of about 5×1018/cm3, an n−-type silicon carbide epitaxial layer having a dopant concentration of 1×1016/cm3 and thickness of about 10 μm is deposited using a thermal CVD apparatus. In the n−-type silicon carbide epitaxial layer, at a first surface thereof opposite to a second surface thereof facing the n+-type silicon carbide substrate, a surface structure of silicon carbide semiconductor device such as a MOS structure is formed.
Further, a technique has been proposed in which a distribution of the film thickness of a semiconductor epitaxial layer of a first conductivity type and a distribution of dopant concentration of the semiconductor epitaxial layer have a positive correlation, whereby variation of device characteristics in a plane parallel to a main surface of a semiconductor wafer is suppressed (for example, refer to Patent Document 1).
The distribution of the film thickness of a conventional n−-type silicon carbide epitaxial layer is normally 5% or less, but the distribution of the doping concentration is about 10% or less, which is worse than the distribution of the film thickness. Here,
In
As depicted in
This is due to factors such as the dopant gas concentration and wafer temperature as well as complex factors that change the dopant take-up efficiency depending on the ratio of C elements and Si elements (C/Si ratio) close to the growth surface. When a surface structure is formed on the n−-type silicon carbide epitaxial layer with such distribution of doping concentration, a problem arises in that variation of the breakdown voltage and on-resistance of the silicon carbide semiconductor device is exacerbated.
To solve the problems associated with the conventional techniques, one object of the present invention is to provide a silicon carbide semiconductor substrate, a method of manufacturing a silicon carbide semiconductor substrate, a silicon carbide semiconductor device, and a method of manufacturing a silicon carbide semiconductor device that suppress variation of the distribution of the net carrier concentration of the n−-type silicon carbide epitaxial layer.
To solve the problems described above and achieve an object of the present invention, a silicon carbide semiconductor substrate according to the present invention has the following features. The silicon carbide semiconductor substrate has a silicon carbide semiconductor substrate of a first conductivity type and a first semiconductor layer of the first conductivity type, provided at a front surface of the silicon carbide semiconductor substrate, the first semiconductor layer having a doping concentration lower than that of the silicon carbide semiconductor substrate. A portion of the first semiconductor layer contains a dopant of a second conductivity type and the dopant of the second conductivity type has a difference in concentration in a direction parallel or orthogonal to an orientation flat that indicates a crystal axis direction.
To solve the problems described above and achieve an object of the present invention, a method of manufacturing a silicon carbide semiconductor substrate according to the present invention has the following features. First, a first process is performed in which, at a front surface of a silicon carbide semiconductor substrate of a first conductivity type, a first semiconductor layer of the first conductivity type is formed, the first semiconductor layer having a doping concentration lower than that of the silicon carbide semiconductor substrate. Next, a second process is performed in which distribution of the doping concentration of the first semiconductor layer is measured. Next, a third process is performed in which a dopant of a second conductivity type is implanted in the first semiconductor layer. In the third process, an amount of the dopant of the second conductivity type is reduced for a region of the first semiconductor layer where the doping concentration is relatively low, and the amount of dopant of the second conductivity type is increased for a region of the first semiconductor layer where the doping concentration is relatively high.
Further, the method of manufacturing the silicon carbide semiconductor substrate according to the present invention is characterized in that, in the invention described above, in the third process, the dopant of the second conductivity type is implanted in a predetermined region from an interface between the silicon carbide semiconductor substrate and the first semiconductor layer.
Further, the method of manufacturing the silicon carbide semiconductor substrate according to the present invention is characterized in that, in the invention described above, in the third process, the dopant of the second conductivity type is implanted in a predetermined region of the first semiconductor layer, from a surface thereof opposite that facing the silicon carbide semiconductor substrate.
To solve the problems described above and achieve an object of the present invention, a silicon carbide semiconductor device according to the present invention has the following features. At a front surface of a silicon carbide semiconductor substrate of a first conductivity type, a first semiconductor layer of the first conductivity type is provided, the first semiconductor layer having a doping concentration lower than that of the silicon carbide semiconductor substrate. At a surface of the first semiconductor layer, opposite to a surface thereof facing the silicon carbide semiconductor substrate, a second semiconductor layer of a second conductivity type is provided. At the surface of the second semiconductor layer, first semiconductor regions of the first conductivity type are selectively provided. Trenches penetrating through the second semiconductor layer and the first semiconductor regions and reaching the first semiconductor layer are provided. In the trenches, gate electrodes are provided via gate insulating films. A first electrode in contact with the first semiconductor regions and the second semiconductor layer is provided. At a back surface of the silicon carbide semiconductor substrate, a second electrode is provided. A portion of the first semiconductor layer contains a dopant of the second conductivity type, the dopant of the second conductivity type having a difference in concentration in a direction parallel to or orthogonal to a crystal axis direction indicted by an orientation flat.
To solve the problems described above and achieve an object of the present invention, a method of manufacturing a silicon carbide semiconductor device according to the present invention has the following features. First, a first process is performed in which, at a front surface of a silicon carbide semiconductor substrate of a first conductivity type, a first semiconductor layer of the first conductivity type is formed, the first semiconductor layer having a doping concentration lower than that of the silicon carbide semiconductor substrate. Next, a second process is performed in which a distribution of the doping concentration of the first semiconductor layer is measured. Next, a third process is performed in which a dopant of a second conductivity type is implanted in the first semiconductor layer. Next, a fourth process is performed in which, at a surface of the first semiconductor layer, opposite a surface thereof facing the silicon carbide semiconductor substrate, a second semiconductor layer of the second conductivity type is formed. Next, a fifth process is performed in which, at the surface of the second semiconductor layer, first semiconductor regions of the first conductivity type are selectively formed. Next, a sixth process is performed in which trenches penetrating through the second semiconductor layer and the first semiconductor regions and reaching the first semiconductor layer are formed. Next, a seventh process is performed in which, in the trenches, gate electrodes are formed via gate insulating films. Next, an eighth process is performed in which a first electrode in contact with the first semiconductor regions and the second semiconductor layer is formed. Next, a ninth process is performed which, at a back surface of the silicon carbide semiconductor substrate, a second electrode is formed. In the third process, in a region of the first semiconductor layer where the doping concentration is low, an amount of the dopant of the second conductivity type is reduced and in a region of the first semiconductor layer where the doping concentration is high, the amount of dopant of the second conductivity type is increased.
According to the invention described above, in the first semiconductor layer of the first conductivity type, for a region thereof where the doping concentration is low, the dose is reduced and in the first semiconductor layer of the first conductivity type, for a region thereof where the doping concentration is high, the dose is increased, counter-doping is performed by p-type ion implantation, and thus the distribution of the net carrier concentration of the first semiconductor layer is improved. As a result, variation of the breakdown voltage and variation of the on-resistance of the MOSFET may be improved. Further, hole injection to the drift layer is suppressed by defects generated by ion implantation, whereby expansion of stacking faults may be suppressed even when a body diode conducts.
The silicon carbide semiconductor substrate, the method of manufacturing the silicon carbide semiconductor substrate, the silicon carbide semiconductor device, and the method of manufacturing the silicon carbide semiconductor device achieve an effect in that variation of the distribution of the net carrier concentration of the n−-type silicon carbide epitaxial layer may be suppressed to be 5% or less.
Embodiments of a silicon carbide semiconductor device and a method of manufacturing a silicon carbide semiconductor device according to the present invention are described in detail with reference to the accompanying drawings. In the present description and accompanying drawings, layers and regions prefixed with n or p mean that majority carriers are electrons or holes. Additionally, + or − appended to n or p means that the doping concentration is higher or lower, respectively, than layers and regions without + or −. Cases where symbols such as n's and p's that include + or − are the same indicate that concentrations are close and therefore, the concentrations are not necessarily equal. In the description of the embodiments below and the accompanying drawings, main portions that are identical are given the same reference numerals and will not be repeatedly described. Further, with consideration of variation in manufacturing, description indicating the same or equal may be within 5%.
In the n−-type silicon carbide epitaxial layer 2, as described in detail hereinafter, variation of the distribution of the net carrier concentration is compensated and improved by ion-implantation of a p-type dopant, which is of the opposite conductivity type. Thus, a portion or all of the n−-type silicon carbide epitaxial layer 2 contains a p-type dopant. In the x-axis direction (direction parallel to the OF, refer to
In the modification example described above, formation may be such that the n−-type silicon carbide epitaxial layer 2 is doped with a p-type dopant, for example, Al, and an n-type dopant, for example, N is ion-implanted to cause inversion to an n-type. In this instance, the entire n−-type silicon carbide epitaxial layer 2 contains an n-type dopant and the n-type doping concentration changes in the x-axis direction or in the y-axis direction of the n−-type silicon carbide epitaxial layer 2.
As described, variation of the distribution of the net carrier concentration in both directions (the x-axis direction and the y-axis direction) is suppressed and improved in the n−-type silicon carbide epitaxial layer 2. As a result, when a MOSFET is fabricated using the silicon carbide semiconductor substrate 60, variation of the breakdown voltage and variation of the on-resistance of the MOSFET may be improved. Further, hole injection to the drift layer is suppressed by defects generated by ion-implantation, whereby expansion of stacking faults may be suppressed even when a body diode conducts.
Next, a method of manufacturing the silicon carbide semiconductor substrate according to the embodiment is described.
First, as depicted in
Next, the distribution of doping concentration of the n−-type silicon carbide epitaxial layer 2 doped with N is obtained by capacitance voltage (CV) measurement. As a result, positions of the n−-type silicon carbide epitaxial layer low-concentration region 21 and the n−-type silicon carbide epitaxial layer high-concentration region 22 may be identified.
Next, a p-type dopant is ion-implanted in the n−-type silicon carbide epitaxial layer 2. At the wafer surface, a dose (dopant implantation amount) is changed to thereby improve the distribution of the net carrier concentration of the n−-type silicon carbide epitaxial layer 2. For example, in the n−-type silicon carbide epitaxial layer low-concentration region 21, the dose is lowered while in the n−-type silicon carbide epitaxial layer high-concentration region 22, the dose is increased, whereby the distribution of the net carrier concentration of the n−-type silicon carbide epitaxial layer 2 may be improved. The state up to here is depicted in
As described, in the method of manufacturing the silicon carbide semiconductor substrate according to the embodiment, the p-type ion implantation dose is set low with respect to a region of a low doping concentration in the n−-type silicon carbide epitaxial layer 2 while the p-type ion implantation dose is set high with respect to a region of a high doping concentration in the n−-type silicon carbide epitaxial layer 2, whereby the distribution of the net carrier concentration of the n−-type silicon carbide epitaxial layer 2 may be improved.
Further, an n-type ion implantation dose is set high with respect to a region of a low doping concentration in the n−-type silicon carbide epitaxial layer 2 and the n-type ion implantation dose is set low with respect to a region of a low doping concentration in the n−-type silicon carbide epitaxial layer 2, whereby the distribution of the concentration of the n−-type silicon carbide epitaxial layer 2 may be improved. In an instance of p-type Al ion-implantation, the mass is greater than that of n-type N ion-implantation and thus, damage may be increased in the crystal structure of the n−-type silicon carbide epitaxial layer 2 and hole injection to the drift layer may be suppressed by crystal defects generated by the damage.
In
In
For example, in an instance in which the n−-type silicon carbide epitaxial layer 2 of the embodiment is applied to the drift layer of a MOSFET with a 1.2 kV class breakdown voltage, the Al ion-implantation to the depth of 3.3 μm and epitaxial growth may be performed multiple times, for example, three times. In other words, the n−-type silicon carbide epitaxial layer 2 may be formed having multiple layers, for example, three layers.
Further, the n−-type silicon carbide epitaxial layer 2 may be doped with a p-type dopant, for example, Al and formed by epitaxial growth, and then, may be ion-implanted with an n-type dopant, for example, N and inverted to an n-type. In an instance of deep ion implantation by a high acceleration energy, N has an ion implantation range that is deep as compared to Al and thus, is preferable.
In the conventional n−-type silicon carbide epitaxial layer in
A semiconductor device according to an embodiment of the present invention is configured using a wide bandgap semiconductor. In the embodiment, a silicon carbide semiconductor device fabricated using, for example, silicon carbide (SiC), as the wide bandgap semiconductor is described taking a MOSFET as an example.
As depicted in
The n+-type silicon carbide substrate 1 is a monocrystalline silicon carbide substrate. The n−-type silicon carbide epitaxial layer 2 is, for example, a low-concentration n-type drift layer having a doping concentration lower than that of the n+-type silicon carbide substrate 1. Here, the n−-type silicon carbide epitaxial layer 2 is fabricated by the method of manufacturing the silicon carbide semiconductor substrate according to the embodiment; variation of the distribution of the net carrier concentration of the n−-type silicon carbide epitaxial layer 2 is compensated and improved by ion implantation of a dopant of the conductivity type opposite to that of the n−-type silicon carbide epitaxial layer 2.
At the first surface of the n−-type silicon carbide epitaxial layer 2 opposite to the second surface thereof facing the n+-type silicon carbide substrate 1, an n-type high-concentration region 6 may be provided. The n-type high-concentration region 6 is a high-concentration n-type drift layer having a doping concentration lower than that of the n+-type silicon carbide substrate 1 and higher than that of the n−-type silicon carbide epitaxial layer 2.
At a first surface of the n-type high-concentration region 6, opposite to a second surface thereof facing the n+-type silicon carbide substrate 1 (in an instance in which the n-type high-concentration region 6 is omitted, the n−-type silicon carbide epitaxial layer 2, hereinafter, simply “(2)”), a p-type layer (second semiconductor layer of a second conductivity type) 3 is provided. Hereinafter, the n+-type silicon carbide substrate 1, the n−-type silicon carbide epitaxial layer 2, and the p-type layer 3 combined are assumed to be a silicon carbide semiconductor base.
At a second main surface (a back surface, i.e., a back surface of the silicon carbide semiconductor base) of the n+-type silicon carbide substrate 1, a drain electrode constituting a back electrode 13 is provided. At a surface of the drain electrode 13, a drain electrode pad 15 is provided.
In the silicon carbide semiconductor base, at a first main surface (surface having the p-type layer 3) thereof, a trench structure is formed. In particular, trenches 16 penetrates through the p-type layer 3 from a first surface (the first main surface of the silicon carbide semiconductor base) of the p-type layer 3, opposite to a second surface thereof facing the n+-type silicon carbide substrate 1 and reach the n-type high-concentration region 6 (2). Further, the trenches 16 are provided in a striped pattern. Along inner walls of the trenches 16, a gate insulating film 9 is formed on bottoms and sidewalls of the trenches 16, and gate electrodes 10 are formed on the gate insulating film 9 in the trenches 16. The gate insulating film 9 insulates the gate electrodes 10 from the n-type high-concentration region 6 (2) and the p-type layer 3. A portion of each of the gate electrodes 10 may protrude from a top (side facing a later-described source electrode pad 14) of the trenches 16 in a direction to the source electrode pad 14.
In a surface layer of the n-type high-concentration region 6 (2), at the first surface thereof (the first main surface of the silicon carbide semiconductor base) opposite to the second surface thereof facing the n+-type silicon carbide substrate 1, first p+-type base regions 4 are selectively provided. The first p+-type base regions 4 are apart from the trenches 16 and reach deep positions closer to a drain than are the bottoms of the trenches 16.
At positions facing the bottoms of the trenches 16 in the depth direction, second p+-type base regions 5 are provided. A width of each of the second p+-type base regions 5 may be equal to or wider than a width of each of the trenches 16. The bottoms of the trenches 16 may reach the second p+-type base regions 5 or may be positioned in the n-type high-concentration region 6 (2), sandwiched between the p-type layer 3 and the second p+-type base regions 5. The first p+-type base regions 4 and the second p+-type base regions 5 are doped with, for example, aluminum (Al). The structure may be such that portions of each of the first p+-type base regions 4 extend toward the trenches 16 adjacent thereto to thereby be connected to the second p+-type base regions 5. A reason for this is that holes occurring when avalanche breakdown occurs at portions connecting the n-type high-concentration region 6 (2) and the second p+-type base regions 5 are efficiently migrated to a source electrode 12, whereby load on the gate insulating film 9 is decreased and reliability is increased.
The p-type layer 3 is in contact with the first p+-type base regions 4. In the p-type layer 3, at the first surface thereof, n+-type source regions (first semiconductor regions of the first conductivity type) 7 are provided. Further, p++-type contact regions 8 may be selectively provided. In this instance, the n+-type source regions 7 and the p++-type contact regions 8 are in contact with one another.
In a surface layer of the n−-type silicon carbide epitaxial layer 2, at the first surface thereof, the n-type high-concentration region 6 may be provided in regions sandwiched between the first p+-type base regions 4 and the second p+-type base regions 5 adjacent thereto and in regions sandwiched between the p-type layer 3 and the second p+-type base regions 5; the n-type high-concentration region 6 is formed to a position deeper than are the first p+-type base regions 4 and the second p+-type base regions 5. Thus, a depth (thickness) of the n-type high-concentration region 6 is greater than a depth (thickness) of each of the first p+-type base regions 4 and a depth (thickness) of each of the second p+-type base regions 5. Further, the first p+-type base regions 4 and the second p+-type base regions 5 may be formed to positions at a same depth. Further, the n-type high-concentration region 6 may be provided so as to surround the first p+-type base regions 4 and the second p+-type base regions 5 on a drain-side of the first p+-type base regions 4 and the second p+-type base regions 5.
In
At the entire first main surface of the silicon carbide semiconductor base, an interlayer insulating film 11 is provided so as to cover the gate electrodes 10 embedded in the trenches 16. The source electrode (first electrode) 12 in contact with the n+-type source regions 7 and the p++-type contact regions 8 via contact holes opened in the interlayer insulating film 11 is provided. The source electrode 12 is electrically insulated from the gate electrodes 10 by the interlayer insulating film 11. On the source electrode 12, the source electrode pad 14 is provided.
Next, a method of manufacturing the silicon carbide semiconductor device according to the embodiment is described.
First, as depicted in
Next, as depicted in
Next, the mask used to form the first p+-type regions 4a and the second p+-type base regions 5 is removed. Subsequently, an n-type dopant, for example, nitrogen atoms, may be ion-implanted by an ion implantation method. As a result, as depicted in
Next, as depicted in
Next, on the surface of the n−-type silicon carbide epitaxial layer 2, a non-depicted mask having predetermined openings is formed by photolithography using, for example, an oxide film. Subsequently, a p-type dopant, for example, aluminum atoms, is ion-implanted by an ion implantation method using the oxide film as a mask. As a result, as depicted in
Next, the mask used during the ion implantation for forming the second p+-type regions 4b is removed. Subsequently, an n-type dopant, for example, nitrogen atoms, is ion-implanted by an ion implantation method. As a result, as depicted in
Next, as depicted in
Next, on the surface of the p-type layer 3, a non-depicted mask having predetermined openings is formed by photolithography using, for example, an oxide mask. Subsequently, an n-type dopant, for example, phosphorus (P) is ion-implanted by an ion implantation method using the oxide film as a mask. As a result, as depicted in
Next, the mask used during the ion implantation for forming the n+-type source regions 7 is removed. Subsequently, on the exposed surface of the p-type layer 3, a non-depicted mask having predetermined openings is formed by photolithography using, for example, an oxide film and a p-type dopant, for example, aluminum, is ion-implanted into the surface of the p-type layer 3, using the oxide film as a mask. As a result, in the p-type layer 3, at the surface thereof, the p++-type contact regions 8 are formed. The dose during the ion implantation for forming the p++-type contact regions 8, for example, may be set so that the dopant concentration becomes higher than that of the second p+-type base regions 5. A sequence in which the ion implantation for forming the n+-type source regions 7 and the ion implantation for forming the p++-type contact regions 8 may be interchanged. The state up to here is depicted in
Next, a heat treatment (annealing) is performed, activating, for example, the first p+-type regions 4a, the second p+-type regions 4b, the n+-type source regions 7, and the p++-type contact regions 8. A temperature of the heat treatment may be, for example, about 1700 degrees C. A period of the heat treatment may be, for example, about two minutes. As described above, ion-implanted regions may be collectively activated by a single session of the heat treatment or may be activated by performing the heat treatment each time ion implantation is performed.
Next, as depicted in
Next, along the surfaces of the n+-type source regions 7 and the surfaces of the p++-type contact regions 8 as well as along the bottoms and sidewalls of the trenches 16, the gate insulating film 9 is formed. The gate insulating film 9 may be formed by thermal oxidation by a heat treatment of about 1000 degrees C. in an oxygen atmosphere. Further, the gate insulating film 9 may be formed by a deposition method by a chemical reaction such as that for a high temperature oxide (HTO).
Next, on the gate insulating film 9, a polycrystalline silicon layer doped with, for example, phosphorus atoms, is formed. The polycrystalline silicon layer is formed so as to be embedded in the trenches 16. The polycrystalline silicon layer is patterned and left in the trenches 16, whereby the gate electrodes 10 are formed. A portion of each of the gate electrodes 10 may protrude from a top (side facing the source electrode pad 14) of the trench 16 in a direction to the source electrode pad 14.
Next, for example, a phosphate glass is deposited so as to cover the gate insulating film 9 and the gate electrodes 10 and have a thickness of about 1 μm, whereby the interlayer insulating film 11 is formed. The interlayer insulating film 11 and the gate insulating film 9 are patterned and selectively removed, thereby, forming contact holes and exposing the n+-type source regions 7 and the p++-type contact regions 8. Thereafter, a heat treatment (reflow) is performed, thereby planarizing the interlayer insulating film 11.
Next, for example, by a sputtering method, the source electrode 12 that is in contact with the n+-type source regions 7 and the p++-type contact regions 8 is formed. Next, for example, by a sputtering method, for example, an aluminum film with a thickness of, for example, about 5 μm is formed so as to cover the source electrode 12 and the interlayer insulating film 11. Thereafter, the aluminum is selectively removed so that a portion is left covering the entire active region of the device, thereby, forming the source electrode pad 14.
Next, for example, by a sputtering method, at the second main surface of the n+-type silicon carbide substrate 1, the drain electrode 13 is formed. Next, on the surface of the drain electrode 13, for example, titanium (Ti), nickel (Ni), and gold (Au) are sequentially deposited, thereby forming the drain electrode pad 15. As described, the semiconductor device depicted in
As described, according to the embodiment, in the n−-type silicon carbide epitaxial layer, for a region thereof where the doping concentration is low, the dose is reduced and in the n−-type silicon carbide epitaxial layer, for a region thereof where the doping concentration is high, the dose is increased, p-type ion implantation is performed, and thus the distribution of the net carrier concentration of the n−-type silicon carbide epitaxial layer 2b is improved. As a result, variation of the breakdown voltage and variation of the on-resistance of the MOSFET may be improved. Further, hole injection to the drift layer may be suppressed by crystal defects generated by the ion implantation, whereby expansion of stacking faults may be suppressed even when a body diode conducts.
In the foregoing, the present invention may be variously modified within a range not departing from the spirit of the invention and in the embodiments described above, for example, dimensions, doping concentrations, etc. of regions, etc. are variously set according to necessary specifications. Further, in the embodiments, while the first conductivity type is assumed to be a p-type and the second conductivity type is assumed to be an n-type, the present invention is similarly implemented when the first conductivity type is an n-type and the second conductivity type is a p-type.
As described, the silicon carbide semiconductor device and the method of manufacturing the silicon carbide semiconductor device are useful for power semiconductor devices used in power converting equipment such as inverters, power source devices of various industrial machines, etc.
Number | Date | Country | Kind |
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2022-200640 | Dec 2022 | JP | national |