Claims
- 1. A chip stack for forming a circuit of a plurality of integrated circuits formed on discrete substrates, said chip stack comprising:
a first substrate having first and second faces and a first integrated circuit having one or more interconnection pads formed proximate to said first face of said first integrated circuit, wherein said substrate additionally comprises a plurality of interconnection pathways selected from the set of vias that pass directly through from said first face to said second face of said first substrate, vias that pass in a step-wise manner from said first face to said second face of said first substrate, and vias that pass from one or more of said first integrated circuit interconnection pads to pads at said second surface of said first substrate; a second substrate having first and second faces and a second integrated circuit having one or more interconnection pads formed proximate to said first face of said second integrated circuit, wherein said substrate additionally comprises a plurality of interconnection pathways selected from the set of vias that pass directly through from said first face to said second face of said second substrate, vias that pass in a step-wise manner from said first face to said second face of said second substrate, and vias that pass from one or more of said second integrated circuit interconnection pads to pads at said second surface of said second substrate; and wherein one or more of said interconnection pathways from said first substrate to said second substrate enable electrical interconnection between said first integrated circuit to said second integrated circuit when said first and second substrates are vertically stacked.
- 2. The chip stack of claim 1 wherein said stack of substrates are encapsulated with a coating to hermetically seal said integrated circuits contained within.
- 3. The chip stack of claim 2 wherein said encapsulation is alumina.
- 4. The chip stack of claim 2 wherein said hermetically sealed stack is suitable for implantation in a patient's body.
- 5. The chip stack of claim 1 additionally comprising:
a third substrate having first and second faces and a third integrated circuit having one or more interconnection pads formed proximate to said first face of said third integrated circuit, wherein said substrate additionally comprises a plurality of interconnection pathways selected from the set of vias that pass directly through from said first face to said second face of said second substrate, vias that pass in a step-wise manner from said first face to said second face of said third substrate, and vias that pass from one or more of said third integrated circuit interconnection pads to pads at the third surface of said third substrate; and wherein one or more of said interconnection pathways from said third substrate to said second substrate enable electrical interconnection between said third integrated circuit to integrated circuits selected from the set of said first and said second integrated circuits when said first, second and third substrates are vertically stacked.
- 6. The chip stack of claim 5 wherein said stack of substrates are encapsulated with a coating to hermetically seal said integrated circuits contained within.
- 7. The chip stack of claim 1 additionally comprising:
a fourth substrate having first and second faces, wherein said fourth substrate additionally comprises a plurality of interconnection pathways selected from the set of vias that pass directly through from said first face to said second face of said fourth substrate, and vias that pass in a step-wise manner from said first face to said second face of said fourth substrate; and wherein said fourth substrate is used within a chip stack of at least said first and said second substrates to facilitate electrical interconnection between said first and said second integrated circuits.
- 8. The chip stack of claim 7 wherein said stack of substrates are encapsulated with a coating to hermetically seal said integrated circuits contained within.
- 9. The chip stack of claim 1 wherein said substrates are essentially uniform in size.
- 10. The chip stack of claim 1 wherein said stack is formed of a plurality of differently-sized substrates stacked in an order to form a stacked shape having a non-rectangular cross section.
- 11. The chip stack of claim 10 wherein said stacked shape is configured to facilitate placement within a housing.
- 12. The chip stack of claim 10 wherein said stacked shape is configured to facilitate placement with an elongated housing having an axial dimension of less than 60 mm and a lateral dimension of less than 6 mm.
- 13. The chip stack of claim 10 wherein said stack is formed of a plurality of differently-sized substrates stacked in order to form a stacked shape having a non-rectangular cross section selection from the set of circular, semi-circular, triangular, diamond, and hexagonal.
- 14. The chip stack of claim 1 wherein said stack is formed of a plurality of differently-sized substrates stacked in order to cause a cavity to be formed with the chip stack, and wherein one or more surface mount devices are mounted on a face of at least one of the substrate faces within said cavity.
- 15. The chip stack of claim 14 wherein said surface mount devices are selected from the set of piezoelectric devices and capacitors.
- 16. The chip stack of claim 14 wherein at least one surface mount device comprises a crystal mounted on a face of at least one of the substrate faces within said cavity.
- 17. The chip stack of claim 14 wherein said stack of substrates are encapsulated with a coating to hermetically seal said integrated circuits contained within.
- 18. A method of forming a chip stack comprising:
forming a first substrate having first and second faces and a first integrated circuit having one or more interconnection pads formed proximate to said first face of said first integrated circuit, wherein said substrate additionally comprises a plurality of interconnection pathways selected from the set of vias that pass directly through from said first face to said second face of said first substrate, vias that pass in a step-wise manner from said first face to said second face of said first substrate, and vias that pass from one or more of said first integrated circuit interconnection pads to pads at said second surface of said first substrate; forming a second substrate having first and second faces and a second integrated circuit having one or more interconnection pads formed proximate to said first face of said second integrated circuit, wherein said substrate additionally comprises a plurality of interconnection pathways selected from the set of vias that pass directly through from said first face to said second face of said second substrate, vias that pass in a step-wise manner from said first face to said second face of said second substrate, and vias that pass from one or more of said second integrated circuit interconnection pads to pads at said second surface of said second substrate; and coupling said first and said second substrates together in a vertical stack wherein one or more of said interconnection pathways from said first substrate to said second substrate enable electrical interconnection between said first integrated circuit to said second integrated circuit.
- 19. The method of claim 18 additionally comprising:
forming a third substrate having first and second faces and a third integrated circuit having one or more interconnection pads formed proximate to said first face of said third integrated circuit, wherein said substrate additionally comprises a plurality of interconnection pathways selected from the set of vias that pass directly through from said first face to said second face of said second substrate, vias that pass in a step-wise manner from said first face to said second face of said third substrate, and vias that pass from one or more of said third integrated circuit interconnection pads to pads at the third substrate of said third substrate; and coupling said third substrate to said second substrate to form a stack of said first, second and third substrates wherein one or more of said interconnection pathways from said third substrate to said second substrate enable electrical interconnection between said third integrated circuit to integrated circuits selected from the set of said first and said second integrated circuits.
- 20. The method of claim 18 additionally comprising the step of encapsulating said stack of substrates with a coating to hermetically seal said integrated circuits contained within.
Parent Case Info
[0001] This application claims the benefit of U.S. Provisional Application No. 60/349,633, filed Jan. 16, 2002.
Provisional Applications (1)
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Number |
Date |
Country |
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60349633 |
Jan 2002 |
US |