Claims
- 1. A semiconductor structure having a semiconductor substrate (18/19) and completed the Master Slice processing steps, said structure having active regions (21) of devices (T1) formed therein and polysilicon lines (23-1) formed thereon, comprising the following successive elements:
- a first thick passivating layer, said first thick passivating layer including an etch stop layer of intrinsic polysilicon formed on said substrate, a layer of phosphosilicate glass (PSG) formed on said etch stop layer, a diffusion barrier layer on said PSG layer and said first passivating layer having a plurality of first metal contact studs (30-1) therein contacting at least one of said active regions (21) and at least one of said polysilicon lines (23-1);
- a surface of said first contact studs being coplanar with a surface of said first thick passivating layer; and
- a plurality of polysilicon lands (31-1) on the coplanar surface, at least one of said polysilicon lands being in contact with at least one of said first contact studs.
- 2. The semiconductor structure of claim 1 wherein at least one of said polysilicon lands is highly resistive.
- 3. The semiconductor structure of claim 1 or 2 further including:
- a second thick passivating layer (34/35) above the structure having a plurality of second metal contact-studs (37-1) therein contacting electrically at least one of said polysilicon lands and one of said first contact studs;
- a surface of said second contact studs being coplanar with a surface of said second thick passivating layer.
- 4. The semiconductor structure of claim 3 further including:
- a plurality of metal lands (38-1 . . . ) above said second thick passivating layer (34/35) in contact with said second contact studs; and
- a final insulating film (39).
- 5. The semiconductor structure of claim 1 wherein said devices are FETs and a plurality of said polysilicon lines are on an insulator, said insulator being on said substrate, said plurality of polysilicon lines forming gate electrodes of said FETs.
- 6. The semiconductor structure of claim 1 wherein at least one of said polysilicon lands is highly conductive.
- 7. The semiconductor structure of claim 2 wherein at least one of said polysilicon lands is highly conductive.
- 8. A semiconductor structure having a semiconductor substrate (18/19) and completed the Master Slice processing steps, said structure having active regions (21) of devices (T1) formed therein and polysilicon lines (23-1) formed thereon, comprising the following successive elements:
- a first thick passivating layer, said first thick passivating layer including an etch stop layer of Al.sub.2 O.sub.3 formed on said substrate, a layer of phosphosilicate glass (PSG) formed on said etch stop layer, a diffusion barrier layer on said PSG layer and said first passivating layer having a plurality of first metal contact studs (30-1) therein contacting at least one of said active regions (21) and at least one of said polysilicon lines (23-1);
- a surface of said first contact studs being coplanar with a surface of said first thick passivating layer; and
- a plurality of polysilicon lands (31-1) on the coplanar surface, at least one of said polysilicon lands being in contact with at least one of said first contact studs.
Priority Claims (1)
Number |
Date |
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Kind |
90480108.1 |
Jul 1990 |
EPX |
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Parent Case Info
This application is a continuation of Ser. No. 08/019488, filed 19 Feb. 1993 and now abandoned, which is a division of Ser. No. 07/28929, filed 12 Jul. 1991 and now U.S. Pat. No. 5,275,963.
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Divisions (1)
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Number |
Date |
Country |
Parent |
728929 |
Jul 1991 |
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Continuations (1)
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Number |
Date |
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Parent |
19488 |
Feb 1993 |
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