Patent Application
20250079190
The following description relates to substrates and methods of manufacturing the substrates.
When manufacturing electronic components, implementing the circuitry on a semiconductor wafer is called the Front-End (FE), and assembling the wafer into a product-ready state is called the Back-End (BE), which includes the Packaging process.
There are four core technologies in the semiconductor industry that have enabled the rapid development of electronic products in recent years: semiconductor technology, semiconductor packaging technology, manufacturing process technology, and software technology.
Semiconductor technology is advancing in various forms, including sub-micron to nano-scale line widths, more than 10 million cells, high-speed operation, and high heat dissipation, but the technology to package them perfectly is relatively weak. Therefore, the electrical performance of semiconductors is often determined by packaging technology and electrical connections rather than the performance of the semiconductor technology itself.
Packaging substrates can be made of ceramic or resin. Ceramic substrates have high resistivity or high dielectric constant, making it difficult to mount high-performance, high-frequency semiconductor devices. In the case of resin substrates, it is possible to mount relatively high-performance high-frequency semiconductor devices, but there are limitations in reducing the pitch of the wiring.
Recently, researchers have been exploring on the use of silicon or glass as high-end packaging substrates. By forming through-holes in the silicon or glass substrate and filling them with conductive materials, the wiring length between the device and the motherboard can be reduced, resulting in improved electrical performance.
A substrate according to one embodiment of the present disclosure includes a glass core having a top surface. The glass core top surface has a value of Rs/z, a ratio value of skewness to maximum height roughness as defined by Equation 1 below, of between −5 nm−2 and 50 nm−2.
In Equation 1 above, the Rsk is a skewness, and the Rz is a maximum height roughness (unit: nm).
The Rsk may be between −0.5 and 1.8.
The Rz may be from 3 nm to 30 nm.
The glass core top surface may have a total of three arbitrarily selected measurement zones.
A standard deviation of the Rsk values among each of the measurement regions may be 0.5 or less.
A standard deviation of the Rz values among each of the above measurement regions may be 1.5 nm or less.
The substrate may include an electrically conductive layer disposed on the glass core.
The electrically conductive layer may include a seed layer and a conductive layer disposed on the seed layer.
A thickness of the seed layer may be from 50 nm to 1500 nm.
The electrically conductive layer may have a patterned shape.
A width of the electrically conductive layer may be from 1 μm to 5 μm.
A thickness of the electrically conductive layer may be from 1 μm to 5 μm.
The electrically conductive layer may comprise a first electrically conductive layer formed in contact with the glass core top surface.
When observed in a cross-section of the first electrically conductive layer, Rz, a maximum height roughness of the interface formed between the first electrically conductive layer and the glass core, may be from 5 nm to 200 nm.
A bonding force between the first electrically conductive layer and the glass core, as measured by a 180° peel test, may be from 0.2 kgf to 3 kgf.
The substrate may have a semiconductor packaging use.
A method of manufacturing a substrate according to another embodiment of the present disclosure includes: a preparation operation of preparing a base glass plate; and a roughening operation of preparing a substrate comprising a glass core formed by roughening a top surface of the base glass plate.
The glass core has a top surface.
The values of Rs/z, a ratio value of skewness to maximum height roughness as defined by Equation 1 below for the glass core top surface, are −5 nm−2 to 50 nm−2.
In Equation 1 above, the Rsk is skewness, and the Rz is maximum height roughness (in nm).
The roughening operation may comprise plasma treating the top surface of the base glass plate to form the glass core.
For the substrate of an embodiment, an electrically conductive layer with substantially uniformly enhanced adhesion to the glass core can be implemented. Furthermore, the electrically conductive layer can efficiently transmit signals even when high frequency electric power is applied.
The present disclosure is hereinafter described in detail with reference to the accompanying drawings, which illustrate embodiments that will facilitate the practice by one having ordinary skill in the art to which the disclosure belongs. However, the disclosure may be implemented in many different forms and is not limited to the embodiments described herein. Throughout the specification, like parts are designated by the same drawing designations.
Throughout this specification, the term “combination thereof” as used in a Makushi-style representation means one or more mixtures or combinations selected from the group of components described in the Makushi-style representation and includes one or more selected from the group of components.
Throughout this specification, terms such as “first,” “second,” or “A,” “B,” are used to distinguish one and the same term from another. In addition, expressions in the singular include the plural unless the context clearly indicates otherwise.
As used herein, a “˜” group may mean that the compound includes a compound corresponding to “˜” or a derivative of “˜”.
As used herein, the reference to B being located on A means that B is located on A either directly abutting A or on A with another layer between them, and is not to be construed as limited to B being located abutting the surface of A.
For the purposes of this specification, a connection from A to B means a direct connection between A and B or a connection between A and B through another component and shall not be construed to be limited to a direct connection between A and B unless otherwise noted.
In this specification, singular expressions shall, unless otherwise indicated, be construed to include the singular or plural as construed from the context.
The shapes, relative sizes, angles, etc. of the configurations shown in the drawings in this specification are exemplary and may be exaggerated for purposes of illustration, and the rights are not to be construed as limited to the drawings.
As used herein, when A and B are adjacent, it means that A and B are placed in contact to each other, or that A and B are not placed in contact to each other but are close to each other. In this specification, the expression A and B are adjacent shall not be construed to mean that A and B are located in contact unless otherwise indicated.
As used herein, high frequency refers to a frequency of about 1 GHz to about 300 GHz. More specifically, it can mean a frequency of about 1 GHz to about 30 GHz, or it can mean a frequency of about 1 GHz to about 15 GHz.
As used herein, a fine line means a line having a width of 5 micrometers or less, unless otherwise specified, and exemplarily means a line having a width of 1 to 4 micrometers or less.
The inventors of the present disclosure have found that by controlling the roughness characteristics of the surface of the glass core, the electrically conductive layer has a substantially uniformly improved bonding force to the glass core, and the electrically conductive layer can efficiently transmit signals by suppressing excessive resistance increase of the electrically conductive layer during high-frequency power application.
Below, the present disclosure is described in detail.
A substrate 100 according to one embodiment of the present disclosure includes a glass core 10 having a top surface 11.
The glass core 10 serves as a support in the substrate 100. The glass core 10 is distinct from a core distribution layer (not shown) or bump (not shown) disposed above or below the glass core 10.
Embodiments may utilize a glass material core to suppress the development of parasitic elements in the core and power losses due to high frequency power application.
The material of the glass core 10 may be, for example, alkaline borosilicate, alkali-free borosilicate, alkali-free alkali earth metal borosilicate, and the like, and may be applied as long as it is a plate glass material applied to an electronic component.
A thickness of the glass core 10 may be 50 μm or more. The thickness may be 100 μm or more. The thickness may be 250 μm or more. The thickness may be 400 μm or more. The thickness may be 500 μm or more. The thickness may be 3000 μm or less. The thickness may be 2000 m or less. The thickness may be 1000 μm or less. When the glass core 10 having such a thickness is applied, it can have excellent utilization as a core for semiconductor packaging.
The glass core top surface 11 has values of Rs/z, a ratio value of skewness to maximum height roughness in Equation 1 below, ranging from −5 nm−2 to 50 nm−2.
In Equation 1 above, the Rsk value is skewness, and the Rz value is maximum height roughness (in nm).
If the roughness of the glass core top surface 11 is simply increased to improve the bonding force of the electrically conductive layer to the glass core top surface 11, the height deviation of the metal layer deposited on the core top surface may be excessively large, or the area in contact between the core top surface and the electrically conductive layer may be reduced. As a result, the electrically conductive layer formed on the top surface may exhibit an overall uneven bonding force.
Furthermore, the electrically conductive layer formed on the glass core top surface 11 of the glass core having the above characteristics may have an excessively high resistance when high-frequency power is supplied. Specifically, when high-frequency power is applied to the substrate 100 to improve the signal transmission speed and transmission volume, a skin effect may occur in the electrically conductive layer. As a result, current may flow concentrated on the surface of the electrically conductive layer.
When an electrically conductive layer is formed on the glass core top surface 11 with excessively high roughness, the cross-sectional profile of the electrically conductive layer may have a rough and amorphous shape. When a high-frequency current flows through an electrically conductive layer having such a shape, the area over which the current can substantially flow in the electrically conductive layer is reduced, and the resistance of the electrically conductive layer can be significantly increased. The magnitude of the increase in resistance of the electrically conductive layer due to the skin effect may be greater as the electrically conductive layer becomes finer.
Embodiments may control the value of Rs/z, which is the value of the ratio of skewness to roughness of the glass core top surface 11. In this case, a more stable interlocking structure can be formed between the glass core 10 and the electrically conductive layer without excessively increasing the roughness of the glass core top surface 11 on the glass core 10 and the bonding force of the electrically conductive layer is effectively improved. In addition, the substrate 100 having the above features can efficiently transmit signals without excessive heat generation even when high-frequency electric power is applied.
Rs/z values are measured in the following ways
A total of three randomly selected measurement areas (not shown) are designated on the glass core top surface 11 of the glass core. The measurement areas are areas of 5 μm in width and 5 μm in length, and each of the measurement areas is selected so that they do not overlap each other.
The skewness value Rsk and the maximum height roughness Rz are measured in non-contact mode using an Atomic Force Microscope according to the method specified in ISO 4287 in each of the above measurement areas. For example, XE-100 model from Park Systems may be used as an atomic force microscope.
The average value of the Rsk values in each of the above measurement areas is set as the Rsk value of the glass core top surface. The average value of the Rz values of each measurement area above is set as the Rz value of the top surface of the glass core.
From the calculated Rsk and Rz values of the glass core top surface, the value of Rs/z is calculated using Equation 1.
The Rs/z value of the glass core top surface 11 may be from −5 nm−2 to 50 nm−2. The Rs/z value may be −3 nm−2 or greater. The Rs/z value may be 0 nm−2 or greater. The value of Rs/z may be greater than or equal to 5 nm−2. The Rs/z value may be 45 nm−2 or less. The Rs/z value may be 40 nm−2 or less. The Rs/z value may be 30 nm−2 or less. The Rs/z value may be 20 nm−2 or less. The value of Rs/z may be 15 nm−2 or less. In such a case, when a fine electrically conductive layer is formed on the glass core 10, the bonding force of the electrically conductive layer to the glass core 10 might be improved substantially uniformly over the entire area of the glass core top surface 11 while suppressing the resistance of the electrically conductive layer from becoming excessively high upon application of high-frequency power.
In the surface profile, a peak is a portion located higher than the baseline (the average height of the surface profile), and a valley is a portion located lower than the baseline. The embodiment may control the shape and height distribution of the peaks and valleys distributed on the glass core top surface 11 by adjusting the value of the skewness Rsk of the glass core top surface 11 to within a range predetermined by the embodiment. When the glass core 10 has the above characteristics, it is possible to prevent the peaks and valleys from being formed relatively narrow and sharp in the profile of the glass core top surface 11. Thus, the surface area in contact with the glass core top surface 11 and the metal layer deposited on the glass core top surface 11 can be appropriately adjusted so that the metal layer can have a stable bonding force. Furthermore, a metal layer with a more even height distribution can be formed on the glass core top surface 11.
The glass core top surface 11 may have an Rsk value of −0.5 to 1.8. The Rsk value may be greater than or equal to −0.2. The Rsk value may be greater than or equal to 0. The Rsk value may be greater than or equal to 0.2. The Rsk value may be 1.5 or less. The Rsk value may be less than or equal to 1.2. The Rsk value may be 1.0 or less. The Rsk value may be 0.8 or less. The Rsk value may be 0.6 or less. In such a case, the shape of the lower surface of the electrically conductive layer abutting the upper surface of the glass core is adjusted so that smooth signal transmission is possible even if a skin effect occurs on the electrically conductive layer.
The Rz value of the glass core top surface 11 may be from 4 nm to 30 nm. The Rz value may be greater than or equal to 5 nm. The Rz value may be 20 nm or less. The Rz value may be 10 nm or less. In such a case, the peel resistance of the electrically conductive layer to the surface of the glass core 10 can be stably controlled. At the same time, it is possible to prevent the resistance characteristic of the electrically conductive layer from becoming excessively high even if a high-frequency power is applied to the electrically conductive layer.
Embodiments may control the variation in roughness characteristics of the plurality of different regions to help ensure that the bonding force and resistance characteristics of the electrically conductive layer to be formed on the glass core 10 appear evenly across the glass core top surface 11.
The standard deviation of the Rsk values in each of the above measurement areas may be 0.5 or less.
The standard deviation of the Rz values in each of the above measurement areas may be 1.5 nm or less.
The standard deviation above is the sample standard deviation.
The standard deviation of the Rsk values in each measurement area may be 0.5 or less. The standard deviation may be 0.4 or less. The standard deviation may be 0.3 or less. The standard deviation may be 0.2 or less. The standard deviation may be greater than or equal to 0.001.
The standard deviation of the Rz values in each measurement area may be 1.5 nm or less.
The standard deviation may be 1 nm or less. The standard deviation may be 0.5 nm or less. The standard deviation may be 0.3 nm or less. The standard deviation may be 0.15 nm or less. The standard deviation may be 0.08 nm or less. The standard deviation may be greater than or equal to 0.001 nm.
In such cases, an overall even roughness characteristic can be formed on the glass core top surface 11.
The glass core bottom surface may have a roughness characteristic such as the those of the glass core top surface 11 described above. In such a case, an electrically conductive layer may have an evenly enhanced bonding force throughout the bottom surface of the glass core, and the electrically conductive layer can efficiently transmit signals even when applying high-frequency power.
The description of the illumination characteristics of the underside of the glass core is redundant to the previous section.
The substrate 100 includes a glass core 10 having a top surface 11. The specific configurations of the substrate 100 described in
The substrate of the embodiment may include an electrically conductive layer 20 disposed on a glass core. The electrically conductive layer 20 may have a patterned shape. The electrically conductive layer 20 may be formed on and/or under the glass core 10 to function to transmit signals.
The width of the electrically conductive layer 20 may be from 1 μm to 5 μm. The width may be 4.5 μm or less. The width may be 4 μm or less.
The thickness of the electrically conductive layer 20 may be from 1 μm to 5 μm. The thickness may be 4.5 μm or less. The thickness may be 4 μm or less.
In such cases, a high-density pattern of electrically conductive layers 20 can be implemented on the substrate 100 and can help the electrically conductive layers 20 have stable resistive characteristics at high-frequency currents.
The substrate 100 includes a glass core 10 having a top surface 11. The specific configurations of the substrate 100 described in
The electrically conductive layer 20 may include a seed layer 21 and a conductive layer 22 disposed on the seed layer 21.
The seed layer 21 may exhibit above a certain level of adhesion to the surface to be bonded (in particular, the glass core top surface 11. The conductive layer 22 may be reliably bonded to the surface of the glass core 10 via the seed layer 21.
The seed layer 21 may comprise a different element from the metal element applied to the conductive layer 22. The seed layer 21 may comprise a metal element applied to the conductive layer 22 and a different metal element from the metal element applied to the conductive layer 22. The seed layer 21 may include a first seed layer (not shown) comprising an element different from the metal element applied to the conductive layer 22, and a second seed layer (not shown) disposed on the first seed layer and comprising the same element as the metal element applied to the conductive layer 22. For example, the first seed layer may comprise a material such as titanium, chromium, nickel, or the like, and the second seed layer may comprise a material such as copper, nickel, aluminum, gold, or silver, or the like.
At least a portion of the seed layer 21 may be formed via a sputtering process. The seed layer 21 may facilitate the formation of the conductive layer 22 on the glass core 10.
Embodiments may adjust a thickness of the seed layer 21 to form am interlocking structure between the seed layer 21 and the glass core top surface 11 with a controlled roughness characteristic reliably.
The thickness of the seed layer 21 may be from 50 nm to 1500 nm. The thickness may be 80 nm or more. The thickness may be 100 nm or more. The thickness may be more than 150 nm. The thickness may be 200 nm or more. The thickness may be 250 nm or more. The thickness may be 300 nm or more. The thickness may be 1200 nm or less. The thickness may be 1000 nm or less.
In such a case, the seed layer 21 can help the electrically conductive layer 20 to have good bonding force, and the electrically conductive layer 20 can be formed efficiently.
The conductive layer 22 may be formed by a plating process on the seed layer 21. Electrically conductive material may be applied as the material of the conductive layer 22. Exemplarily, the conductive layer 22 may comprise at least one of copper, nickel, aluminum, gold, or silver.
The substrate 100 includes a glass core 10 having a glass core top surface 11. The specific configurations of the substrate 100 described in
The substrate 100 may include a core distribution layer 50 disposed on the glass core 10. The core distribution layer 50 may include an electrically conductive layer 20 and an insulating layer 30 surrounding at least a portion of the electrically conductive layer 20.
In the core distribution layer 50, the insulating layer 30 and the electrically conductive layer 20 may be arranged in a mixed manner. The core distribution layer 50 may be formed with the electrically conductive layer 20 embedded within the insulating layer 30 at a predetermined location and shape. In at least a portion of the core distribution layer 50, the electrically conductive layers 20 may be formed in a fine wire.
The core distribution layer 50 may be formed by a process of repeatedly forming and removing the insulating layer 30 and the electrically conductive layer 20.
The insulating layer 30 can be any insulating layer that can be applied to a semiconductor device or packaging substrate as an insulating layer. The insulating layer 30 may be an epoxy-based resin including fillers, for example. The insulating layer 30 may be formed by, but is not limited to, a build-up layer material such as Ajinomoto Build-up Film (ABF) from Ajinomoto, an undercoat material, and the like.
The insulating layer 30 may be formed by laminating an uncured or semi-cured insulating film and then curing the uncured or semi-cured insulator film.
The electrically conductive layer 20 may include a first electrically conductive layer 25 disposed in contact to the surface of the glass core 10. The electrically conductive layer 20 may also include a second electrically conductive layer 26 that is not in contact to the surface of the glass core 10.
When observed in a cross-section of the first electrically conductive layer 25, the value of Rz, the maximum height roughness of the interface L formed between the first electrically conductive layer 25 and the glass core 10, may be from 5 nm to 200 nm.
Embodiments may control the roughness characteristics of the interface L formed between the first electrically conductive layer 25 and the glass core 10. This allows for stable control of the resistance and heat generation characteristics of the first electrically conductive layer 25 due to the skin effect, while further improving the adhesion of the first electrically conductive layer 25 to the glass core 10 due to the anchor effect.
The Rz value of the interface L is measured by the following method.
A cross-section of the first electrically conductive layer 25 is prepared for imaging using a transmission electron microscope (TEM). A cross-section of the first electrically conductive layer 25 means a cross-section in a direction perpendicular to the glass core top surface 11 of the glass core. If the first electrically conductive layer 25 has a patterned shape, a cross-section of the first electrically conductive layer 25 means a cross-section in a direction perpendicular to the glass core top surface 11 of the glass core and perpendicular to the longitudinal direction of the first electrically conductive layer 25. From the cross-sectional image of the first electrically conductive layer 25, a profile of the interface L formed between the first electrically conductive layer 25 and the glass core 10 is traced, and a value of Rz, the maximum height roughness of the interface L, is got from the traced profile.
The Rz value is measured according to the method specified in ISO 4287. Specifically, in the traced profile of the interface L, the sum of the height of the highest peak and the depth of the deepest valley is set as the Rz value.
The Rz value of the interface L formed between the first electrically conductive layer and the glass core may be 200 nm or less. The Rz value may be 180 nm or less. The Rz value may be 150 nm or less. The Rz value may be 100 nm or less. The Rz value may be greater than or equal to 5 nm. The Rz value may be greater than or equal to 10 nm. In such a case, a first electrically conductive layer 25 that has good peeling resistance and is suitable for applying high frequency power can be implemented on the surface of the glass core 10.
Embodiments may control the bonding force of the first electrically conductive layer 25 to the glass core surface to above a certain level, which may help prevent delamination of the first electrically conductive layer 25 during manufacturing and processing of the substrate.
The bonding force value between the first electrically conductive layer 25 and the glass core 10 as measured by a 1800 peel test is measured using a bond tester. The measuring speed (peel speed) is set to 10 mm/s and the measuring distance (peel distance) is set to 70 mm. Exemplarily, the bond force value can be measured with a Condor Sigma bond tester from XYZ TEC.
The bonding force between the first electrically conductive layer 25 and the glass core 10, as measured by a 180° peel test, may be 0.2 kgf or more. The bonding force may be 0.3 kgf or more. The bonding force may be 0.4 kgf or more. The bonding force may be 3 kgf or less. In such cases, the electrically conductive layer 20 can be reliably bonded to the surface of the glass core 10 during the manufacturing and processing of the substrate.
The glass core 10 may include a core via (not shown) that penetrates the glass core 10 in the thickness direction. A core distribution layer 50 may be formed on the glass core top surface 11 and within the core vias. The core distribution layer 50 may be formed over the glass core top surface 11, below the glass core bottom surface 12, and within the core via. In this case, the core distribution layer 50 may connect the glass core top surface 11 and the glass core bottom surface 12 of the glass core over a relatively short distance. Furthermore, electrical signals can be transmitted more quickly between the device disposed on the top surface of the substrate 100 and the motherboard disposed under the bottom surface of the substrate 100, and the occurrence of signal loss can be suppressed.
The core via may include an inner space and side surface surrounding the inner space. In the core via, an electrically conductive layer may be formed abutting the side surface of the core via. The electrically conductive layer may be formed by filling the inner space of the core via.
The core via may be formed by processing a predetermined area within the glass core 10. Specifically, it may be formed by etching the glass core 10 by physical and/or chemical methods. For example, a method of forming a core via may include forming defects on the surface of the glass core 10, such as by laser, followed by chemical etching, laser etching, or the like.
A cavity region (not shown) in which an element is received may be disposed in the glass core 10. The cavity region may include a receiving portion, which is a space formed by the removal of a portion of the glass core 10. The receiving portion may be formed by penetrating the glass core 10. The receiving portion may be formed by a removing a portion of the top or bottom of the glass core 10.
An element may be mounted in the receiving portion. The element is not only a semiconductor device such as a CPU, GPU, memory chip, etc. but also a capacitor device, transistor device, impedance device, other module, etc. In other words, any element mounted on a semiconductor component can be applied as the element without limitation.
The substrate 100 may further include a top layer (not shown) on above the core distribution layer 50 disposed on the glass core 10.
The top layer may include a top substrate layer and a top contact layer disposed on the top substrate layer. An element disposed in the substrate 100 may be electrically connected to the substrate 100 via the top surface contact layer.
The top distribution layer may include an electrically conductive layer and an insulating layer surrounding at least a portion of the electrically conductive layer. The electrically conductive layer and the insulating layer of the top layer may each be made of the same material as the electrically conductive layer and the insulating layer of the core distribution layer. The top distribution layer may electrically connect the device and the core distribution layer.
The substrate 100 may further include a bottom layer (not shown) below the core distribution layer 50 (not shown) disposed on the glass core bottom surface 12.
The bottom layer may include a bottom distribution layer and a bottom contact layer disposed below the bottom distribution layer. A main board disposed below the substrate 100 may be electrically connected to the substrate 100 via the bottom contact layer. The core distribution layer may be electrically connected to the main board via the bottom layer.
The bottom distribution layer may include an electrically conductive layer and an insulating layer surrounding at least a portion of the electrically conductive layer. The electrically conductive layer and the insulating layer of the bottom distribution layer may each be made of the same material as the electrically conductive layer and the insulating layer of the core distribution layer.
The substrate 100 may have semiconductor packaging use. The substrate 100 can be utilized for mounting semiconductor devices, protecting semiconductors, and providing electrical connections between the devices and the main board.
A semiconductor package according to another embodiment of the present disclosure includes a substrate 100 and a main board (not shown) electrically coupled to the substrate.
The substrate 100 may be mounted on a main board and electrically connected to the main board. The main board is not limited as long as it is commonly applied in the field of semiconductor component.
The description of the substrate 100 is redundant to the preceding and will be omitted.
A method of manufacturing a substrate according to another embodiment of the present disclosure includes a preparation operation of preparing a base glass plate and a roughening operation of preparing a substrate comprising a glass core formed by roughening the top surface of the base glass plate.
The glass core has a top surface, wherein the top surface of the glass core has a value of Rs/z, a ratio of skewness to maximum height roughness in Equation 1 below, between −5 nm−2 and 50 nm−2.
In Equation 1 above, the Rsk is skewness and the Rz is maximum height roughness (in nm).
In the preparation operation, a base glass plate can be processed to prepare the glass core.
The base glass plate can be any plate glass material applied to an electronic component. For example, the base glass plate can be an alkaline borosilicate glass plate, an alkali-free borosilicate glass plate, or an alkali-free alkali earth metal borosilicate glass plate, etc. Commercially available base glass plates include, for example, those manufactured by Corning, Schott, AGC, and others.
The operation of roughening in an embodiment may comprise plasma treating the top surface of the base glass plate to form a glass core. The roughening operation may comprise plasma treating the top surface of the base glass plate with an inert gas to form a glass core. This may result in a glass core having a top surface with controlled roughness characteristics such that the roughness is not excessively high and has a skewness in a predetermined range in the embodiment.
The inert gas may be anyone selected from the group consisting of helium gas, argon gas, xenon gas, krypton gas, and combinations thereof. The inert gas may be an argon gas. In such cases, the inert gas may help to form a glass core having the surface roughness characteristics desired in the embodiment while inhibiting chemical changes of the base glass plate top surface during the roughening operation.
In the roughening operation, the atmospheric pressure may be 100 mTorr or less. The atmospheric pressure may be 80 mTorr or less. The atmospheric pressure may be 50 mTorr or less. The atmospheric pressure may be 30 mTorr or less. The atmospheric pressure may be greater than or equal to 1 mTorr. In such a case, the inert gas ionized during the roughening operation may collide on the surface to be roughened without undue disturbance, thereby facilitating control of the roughness characteristics of the glass core top surface.
In the roughening operation, the flow rate of the inert gas introduced may be 100 sccm or more. The flow rate may be greater than or equal to 150 sccm. The flow rate may be greater than or equal to 200 sccm. The flow rate may be 1000 sccm or less. In such cases, enough ionized inert gas may be collide on the top surface of the base glass plate at a suitably controlled speed.
A source power may be 0.1 kW or more during the roughening operation. The source power may be 0.3 kW or more. The source power may be 0.5 kW or more. The source power may be 5 kW or less.
The bias power may be 0.1 kW or more during the roughening operation. The bias power may be 0.3 kW or more. The bias power may be 0.5 kW or more. The bias power may be greater than or equal to 1 kW. The bias power may be 8 kW or less. The bias power may be 5 kW or less.
In such cases, the kinetic velocity of the ionized inert gas can be controlled within a suitable range to help form a glass core with the desired surface roughness characteristics of the embodiment.
The roughening operation may be practiced for more than 10 seconds. The roughening operation may be practiced for more than 15 seconds. The roughening operation may be practiced for more than 30 seconds. The roughening operation may be practiced for 1000 seconds or less. This can help form a glass core top surface having a roughness and skewness within a predetermined range, in an embodiment.
The roughening operation might be performed not only on the top surface of the base glass, but also on the bottom surface. The roughening operations may be applied to the bottom surface of the base glass plate in same manner as described above.
If desired, a core via can be formed in the glass core. Specifically, defects can be formed at predetermined locations on the surface of the glass core. The defects may be subjected to physical or chemical etching to form core vias. A description of a method for forming a core via is omitted as it is redundant to the foregoing.
The method of manufacturing the substrate of an embodiment may further comprise the operation of forming a core distribution layer on the glass core.
The description of the core distribution layer is redundant to the previous section.
The operation of forming the core distribution layer may include forming an electrically conductive layer on the glass core; and forming an insulating layer surrounding at least a portion of the electrically conductive layer.
In the process of forming the electrically conductive layer, in an embodiment, predetermined conditions of the sputtering process can be applied to form a seed layer to suppress excessive deviation in the roughness characteristics of the glass core top surface due to the collision of the sputter particles against the glass core top surface. In this way, the seed layer formed by sputtering can form a stable interlocking structure with the glass core surface throughout the glass core top surface, which contributes to the improvement of the bonding force of the electrically conductive layer. In addition, it can help to effectively suppress the increase in resistance of the electrically conductive layer caused by the skin effect.
The seed layer may include a first seed layer comprising a metal element different from the metal element applied to the conductive layer, and a second seed layer disposed on the first seed layer and comprising the same metal element as the metal element applied to the conductive layer. For example, the first seed layer may comprise a material such as titanium, chromium, nickel, or the like, and the second seed layer may comprise a material such as copper, nickel, aluminum, gold, or silver, or the like.
The description of the seed layer is redundant and will be skipped.
In the sputtering process for seed layer formation, the atmospheric pressure may be 0.1 Pa or more. The pressure may be greater than or equal to 0.3 Pa. The pressure may be 5 Pa or less. In such a case, the seed layer can be formed at an improved deposition rate.
The sputter power applied in the sputtering process for forming the seed layer may be 10 kW or more. The sputter power may be 15 kW or more. The sputter power may be 20 kW or more. The sputter power may be 100 kW or less. The sputter power may be 50 kW or less. In such cases, the sputter particles may collide on the surface to be deposited with a controlled kinetic energy. This allows for more robust formation of the seed layer on the glass core while preventing excessive deviation in the roughness characteristics of the glass core surface.
In the sputtering process for forming the seed layer, the initial temperature of a bed, which is the substrate holder, may be 180° C. or less. The temperature may be 150° C. or less. The temperature may be 30° C. or more. In such a case, the migration characteristics of the sputtered particles being deposited may be controlled to further improve the durability of the seed layer.
In the sputtering process for forming the seed layer, an inert gas may be applied as the sputter gas. The inert gas may be argon.
The sputtering process for forming the first seed layer may be practiced for more than one minute. The sputtering process may be practiced for more than 2 minutes. The sputtering process may last 20 minutes or less.
The sputtering process for forming the second seed layer may be practiced for more than one minute. The sputtering process may be practiced for more than 2 minutes. The sputtering process may be practiced for 20 minutes or less.
In this case, a seed layer with a structure that stably bonds to the top surface of the glass core can be formed.
After the seed layer is formed, the portion of the seed layer that does not require the formation of an electrically conductive layer can be removed. A plating activation/deactivation treatment may be applied to the portion of the seed layer that is required to form an electrically conductive layer and the portion that is not required respectively. For example, the plating activation/deactivation treatment may be applied light irradiation treatment using a laser of a specific wavelength, chemical treatment, etc. However, it is possible to form a conductive layer on the seed layer without applying the above treatment.
The description of the structure and material of the seed layer is redundant and will be omitted.
A conductive layer can be formed by a plating process on the seed layer to provide an electrically conductive layer. A description of the material of the conductive layer is omitted as it is redundant to the preceding description. After forming the conductive layer, the electrically conductive layer can be etched so that the electrically conductive layer has a pre-designed pattern shape.
After forming the electrically conductive layer, an insulating layer surrounding at least a portion of the electrically conductive layer may be disposed to form a core distribution layer. The insulating layer may exemplarily include an epoxy-based resin including a filler. The insulating layer may be formed by, but is not limited to, a build-up layer material such as Ajinomoto Build-up Film (ABF) from Ajinomoto, an undercoat material, and the like.
The insulating layer can be formed by laminating uncured or semi-cured insulator films and then curing them.
The operation of forming a core distribution layer may include forming a core distribution layer over the glass core. The operation of forming a core distribution layer may include forming a core distribution layer above and below the glass core. The operation of forming a core distribution layer may include forming a core distribution layer over and below the glass core and within the core via. A description of the method of forming a core distribution layer under the glass core and on the core via is omitted as it is redundant to the preceding description.
Optionally, the method of manufacturing the substrate of an embodiment may further comprise the operation of forming a top distribution layer above the core distribution layer disposed on the glass core. The top distribution layer includes an electrically conductive layer and an insulating layer surrounding at least a portion of the electrically conductive layer.
The method of manufacturing the substrate of an embodiment may further comprise the operation of forming a bottom distribution layer and/or a bump below the core distribution layer disposed below the glass core. The bottom distribution layer includes an electrically conductive layer and an insulating layer surrounding at least a portion of the electrically conductive layer.
The electrically conductive and insulating layers applied to the upper and lower distribution layers may be of the same material and manufacturing method as the electrically conductive and insulating layers applied to the core distribution layer.
Specific embodiments will be described in more detail below. The following embodiments are illustrative only to aid in understanding the disclosure and are not intended to limit the scope of the disclosure.
Example 1: The surface of the base glass plate, which is an alkali-free glass plate from SCHOTT, was treated with argon plasma for 10 to 30 seconds to prepare the glass core. The argon plasma treatment was performed at a pressure of 10 mTorr, an argon gas flow rate of 300 sccm, a source power of 0.8 kW, and a bias power of 0.8 kW.
Example 2: The surface of the base glass plate, which is a soda-lime glass plate from SCHOTT, was treated with argon plasma for 10 to 30 seconds to prepare the glass core. The argon plasma treatment was performed at a pressure of 10 mTorr, an argon gas flow rate of 300 sccm, a source power of 0.5 kW, and a bias power of 0.5 kW.
Example 3: The surface of the base glass plate, which is an SG 7.8 glass plate from Corning, was plasma treated with argon for 20 to 40 seconds to prepare the glass core. The argon plasma treatment was performed at a pressure of 10 mTorr, an argon gas flow rate of 300 sccm, a source power of 0.5 kW, and a bias power of 0.5 kW.
Example 4: The surface of the base glass plate, which is an alkali-free glass plate from SCHOTT, was treated with argon plasma for 20 to 40 seconds to prepare the glass core. The argon plasma treatment was performed at a pressure of 10 mTorr, an argon gas flow rate of 300 sccm, a source power of 1.0 kW, and a bias power of 1.0 kW.
Example 5: The surface of the base glass plate, which is an alkali-free glass plate from SCHOTT, was treated with argon plasma for 30 to 50 seconds to prepare the glass core. The argon plasma treatment was performed at a pressure of 10 mTorr, an argon gas flow rate of 300 sccm, a source power of 1.2 kW, and a bias power of 1.5 kW.
Comparative Example 1: The surface of the base glass plate, a Corning SG7.8 glass plate, was argon plasma treated for 90 to 120 seconds to prepare the glass core. The argon plasma treatment was performed at an atmosphere pressure of 10 mTorr, argon gas flow rate of 300 sccm, source power of 1.2 kW, and bias power of 2.0 kW.
Comparative Example 2: The surface of the base glass plate, an alkali-free glass plate from SCHOTT, was subjected to argon plasma treatment for 90 to 120 seconds to prepare the glass core. The argon plasma treatment was performed at a pressure of 10 mTorr, an argon gas flow rate of 300 sccm, a source power of 1.5 kW, and a bias power of 2.5 kW.
A total of three measuring areas with a width of 5 μm and a length of 5 μm were randomly selected on the top surface of the glass core of the example and comparative examples. The measurement areas were selected so that they do not overlap each other.
The Rsk and Rz values of each of the above measured areas were measured in non-contact mode using a Park Systems XE-100 atomic force microscope according to ISO 4287.
The average value of the Rsk value of each measurement area was taken as the Rsk value of the glass core top surface, and the average value of the Rz value of each measurement area was taken as the Rz value of the glass core top surface.
From the above Rsk and Rz values, we calculated the value of Rs/z.
The results of the measurements and calculations for the examples and comparative examples are shown in Tables 1 and 2 below.
The standard deviation of Rsk values and Rz values were calculated from the Rsk values and Rz values measured in each measurement area of the glass core top surface of the examples.
The calculations for each example are shown in Table 2 below.
A titanium layer with a thickness of 300 nm was formed on the top surface of the glass core of the examples and comparative examples and a copper layer with a thickness of 300 nm on the titanium layer were sputtered to form a seed layer. In the sputtering process for forming the seed layer, a pressure of 0.4 Pa, a sputter power of 30 kW, and a substrate temperature of 120° C. were set. The titanium and copper layers were deposited by sputtering for 3 minutes each under the above conditions. Conductive layer with thickness of 20 μm was formed on the seed layer using a copper plating process to provide an electrically conductive layer.
The bonding force of the electrically conductive layer to the glass core was then measured with a bond tester Condor Sigma from XYZ TEC according to the 180° peel test.
The measurement results for the examples and comparative examples are shown in Table 1 below.
A seed layer was formed by sputtering a titanium layer with a thickness of 300 nm on the top surface of the glass core of the examples and the comparative examples respectively, and a copper layer with a thickness of 300 nm on the titanium layer. A conductive layer with a thickness of 20 μm was formed by a copper plating process on the seed layer to provide an electrically conductive layer.
Singulation was performed at the glass core on which the electrically conductive layer was formed. Specifically, energy was applied to the dicing path on the top surface of the glass core through a laser device, and the glass core was cut by applying a physical force. Then, grinding was performed on the edge of the cut glass core.
Cross-sections of the singulated glass cores were examined under a optical microscope to check for delamination of the electrically conductive layer.
For each Example and Comparative Example, the electrically conductive layer was evaluated as P if no delamination of the electrically conductive layer occurred and F if delamination of the electrically conductive layer occurred.
The measurement results for the examples and the comparative examples are shown in Table 1 below.
In Table 1 above, for Examples 1 through 5, where the Rs/z value was controlled from −5 nm−2 to 50 nm−2, the electrically conductive layer exhibited a bonding force of 0.2 kgf or more, and no delamination of the electrically conductive layer occurred in the delamination test.
In contrast, for Comparative Examples 1 and 2, where the Rs/z value was less than −5 nm−2 or greater than 55 nm−2, the bonding force of the electrically conductive layer was measured to be less than or equal to 0.15 kgf, and delamination of the electrically conductive layer occurred when evaluated for delamination.
In Table 2 above, in Examples 1 to 5, the standard deviation of the Rsk values of each measurement area was calculated to be 0.4 or less, and the standard deviation of the Rz values was calculated to be 0.9 nm or less. This means that the roughness characteristics of the glass core top surface of the Examples are even throughout.
Although preferred embodiments of the present disclosure have been described in detail above, the scope of the disclosure is not limited thereto, and various modifications and improvements by those skilled in the art utilizing the basic concepts of the disclosure as defined in the following claims are also within the scope of the disclosure.
This application claims the priority benefit of U.S. provisional application Ser. No. 63/535,306, filed on Aug. 29, 2023. The entirety of the above-mentioned patent application is hereby incorporated by reference herein and made a part of this specification.
| Number | Date | Country | |
|---|---|---|---|
| 63535306 | Aug 2023 | US |
