Not applicable.
A portion of this disclosure contains material which is subject to copyright protection. The copyright owner has no objection to the photocopy reproduction by anyone of the patent document or the patent disclosure in exactly the form it appears in the Patent and Trademark Office patent file or records, but otherwise reserves all copyright rights whatsoever. 37 C.F.R 1.71(d).
This application claims the benefit of Provisional Application No. 63/487,345, filed Feb. 28, 2023, entitled “SYSTEM ON FOIL.” The benefit under 35 USC § 119(e) of the United States provisional application is hereby claimed, and the aforementioned provisional application is hereby incorporated herein by reference in its entirety.
The present inventive concept relates to a substrate-on-foil formed of a metal substrate core including metal patterned in-substrate structures formed therein, and methods of making the same. More particularly, but not exclusively, the present inventive concept relates to a substrate-on-foil formed of a metal substrate core including metal patterned in-substrate structures formed therein which are different metals than the metal in which the metal substrate core is formed, and methods of making the same.
The high cost of advancing to the next semiconductor technology node (e.g., 5 nm) is changing the role of packaging in the electronics industry. With each new node, Moore's Law has historically fulfilled the economic and technological promises of density, speed, power, and cost scaling. However, these benefits are now slowing, and new packaging solutions are needed to maintain the pace of economic advantages previously met with silicon scaling.
Conductive through substrate vias are required for nearly all advanced packaging applications since successfully partitioning a System-on-Chip (SoC) design requires an abundance of Inputs/Outputs (I/Os). This is because SoC designs comprise millions of logic gates connected by complex networks of wires, in the form of multiple buses, complicated clock distribution networks, and control signals. Standard device I/Os impose pin-to-pin delays that degrade overall circuit performance. Moreover, using time-domain multiplexing (TDM) on standard I/Os to increase the virtual pin count by running multiple signals on each I/O imposes even greater latencies that can slow I/O speeds down by a factor of 4×-32× or more. TDM approaches also result in higher power consumption. When used to drive hundreds of package-to-package connections across PCB traces between multiple chips, standard device I/O pins carry a heavy power penalty compared to connecting logic nets on a monolithic die. These requirements all lead to a demand for vias through the substrate.
There are presently three options to achieve a feedthrough within an electronic substrate: Through Panel Vias (TPVs)—electrical conduits through printed circuit boards or organic substrates; Through Silicon Vias (TSVs)—electrically isolated copper traces through a thinned silicon wafer; and Through Glass Vias (TGVs)—metal filled holes through a glass wafer. All of the processing techniques to create conductive center pins for conductive through vias use electrodeposited copper or a conductive paste screen printing process that uses gold, silver or copper mixed with a glass powder and a polymer binder to form the conductive paste.
One issue with TPVs in printed circuit boards is the minimum resolution of wires (metal lines) and space is limited for larger features. Most printed circuit boards can pattern 4 mil (100 μm) or 3 mil (75 μm) lines and spacing and the state of the art is around 1.2 mil (30 μm), but at a very high premium price. Holes for through panel vias are limited to about 6 mils (150 μm). These large features mostly limit printed circuit boards to packaged components and do not allow for high resolution components, such as flip chip dies. Because of issues with electroplating copper to fill the large drilled holes in the printed circuit boards the TPVs are usually large barrel coated holes with an opening in the center of the via. One example of a TPV is described in U.S. Pat. No. 6,717,071 “Coaxial Via Hole and Process of Fabricating the Same.”
Besides the high cost of TSV, they also have low mechanical strength. Because the silicon interposers are thinned down to create the TSV, they are weak and subject to cracking and breaking. When a silicon interposer package is increased in size and attached to a printed circuit board the coefficient of thermal expansion (CTE) mismatch between the silicon interposer and organic substrate can cause the bonding bumps to physically crack or break. The TSV can also warp, which can prevent fabrication or assembly, leading to phenomenons such as ball grid array (BGA) non-wets.
Through glass vias (TGVs), and to a lesser extent through silicon vias (TSVs), suffer from a lack of their ability to dissipate heat. The glass substrates in TGVs are insulators, thus only allowing heat to escape out of the top of the package. The TGVs are also not flexible, thus limiting their role in certain applications.
System-on-Foil™, detailed in PCT/US20/54245 “System-on-Foil™ Device,” included herein by reference, is a system-level advanced packaging technology designed to address the shortcomings of the current 2.5/3D packaging architecture. Within System-on-Foil™ and all advanced packages, there exists a substrate with multilevel wiring layers to allow surface mounted electronic components to communicate with one another.
However, an issue with using a metal substrate for HI is that larger pads and solder bumps attached to wiring layers on the metal substrate can capacitively couple to the substrate, therefore limiting the high-frequency bandwidth.
U.S. patent application Ser. No. 18/446,841, filed on Aug. 9, 2023 by the same inventors of the present patent application, discloses metal substrates patterned with metal in-substrate structures which are formed of the same body of metal as the metal substrate itself.
Accordingly, there is a need for metal based package substrates with in-substrate structures formed therein of a dielectric and a different metal, to be able to tailor the electronic properties of the in-substrate metal for the desired performance criteria. Additionally, the selection of type of in-substrate metal allows for different processing parameters, and thus manufacturability and cost considerations.
The present general inventive concept provides a substrate-on-foil including metal patterned components formed therein, and methods of making the same. More particularly, but not exclusively, the present inventive concept relates to a substrate-on-foil including metal patterned components formed therein which are different metals than the metal in which the substrate if formed, and methods of making the same.
Additional features and utilities of the present general inventive concept will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the general inventive concept.
The foregoing and/or other features and utilities of the present general inventive concept may be achieved by providing a substrate-on-foil, comprising: a metal substrate core; at least one in-substrate metal structure patterned through the metal substrate core, the at least one in-substrate metal structure consisting of a different type of metal than the metal of the metal substrate core; and a dielectric material completely isolating the at least one in-substrate metal structure from the metal substrate core.
In an exemplary embodiment, the at least one in-substrate metal structure is made of a metal which is more electrically conductive than the core metal.
In another exemplary embodiment, the at least one in-substrate metal structure is made of copper.
In another exemplary embodiment, the dielectric material is selected from a group consisting of: a) a polymer; b) a silicone; c) a glass; d) a ceramic; or any combination of a through d.
In still another exemplary embodiment, the metal substrate core is between 200-400 μm in thickness.
In still another exemplary embodiment, the metal substrate core is between 10-1000 μm in thickness.
The foregoing and/or other features and utilities of the present general inventive concept may also be achieved by providing a method of fabricating a substrate-on-foil, the method comprising: etching at least one three-dimensional trench partially through a metal core structure from a top surface thereof; filling the at least one three-dimensional trench with a photoresist material; etching a trench into the photoresist material; depositing a metal of a different type than the type of metal that the metal core structure consists of into each trench etched into the photoresist material; etching away the photoresist to leave a partial trench surrounding the deposited metal; depositing a dielectric material into the partial trench surrounding the deposited metal; and griding a back side of the metal core structure until the deposited metal and surrounding dielectric material are exposed.
The foregoing and/or other features and utilities of the present general inventive concept may also be achieved by providing a method of fabricating a substrate-on-foil, the method comprising: etching at least one three-dimensional trench partially through a metal core structure from a top surface thereof; filling the at least one three-dimensional trench with a photoresist material; etching a trench into the photoresist material; depositing a metal of a different type than the type of metal the metal of the metal core structure into each trench etched into the photoresist material; etching away the photoresist to leave a trench surrounding the deposited metal; depositing a dielectric material into the trench surrounding the deposited metal; turning the metal core over and performing the steps of: etching at least one three-dimensional trench partially through the back side of the metal core structure to expose the at least one dielectric material and deposited metal; filling the at least one three-dimensional trench with a photoresist material; etching a trench into the photoresist material to expose the deposited metal; depositing a metal of a different type than the type of metal than the metal of the metal substrate into each trench etched into the photoresist material to form a through metal via; etching away the photoresist to leave a partial trench surrounding the deposited metal; and depositing a dielectric material into the partial trench surrounding the deposited metal.
The foregoing and/or other features and utilities of the present general inventive concept may also be achieved by providing a method of fabricating a substrate-on-foil, the method comprising: etching at least one three-dimensional trench partially through a metal core structure from a top surface thereof; filling the at least one three-dimensional trench with a dielectric material; etching a trench into the dielectric material; depositing a metal of a different type than the type of metal that the metal core structure consists of into each trench etched into the dielectric material; and griding a back side of the metal core structure until the deposited metal and surrounding dielectric material are exposed.
The foregoing and/or other features and utilities of the present general inventive concept may also be achieved by providing a method of fabricating a substrate-on-foil, the method comprising: etching at least one three-dimensional trench partially through a metal core structure from a top surface thereof; filling the at least one three-dimensional trench with a dielectric material; etching a trench into the dielectric material; depositing a metal of a different type than the type of metal that the metal core structure consists of into each trench etched into the dielectric material; etching at least one three-dimensional trench through the metal core structure from a back side thereof until the deposited metal and dielectric material are exposed; filling the at least one three-dimensional trench with a dielectric material; etching a trench into the dielectric material until the deposited metal is exposed; and depositing a metal of a different type than the type of metal that the metal core structure consists of into each trench etched into the dielectric material to form a through metal via.
These and/or other features and utilities of the present inventive concept will become apparent and more readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings of which:
The drawings illustrate a few example embodiments of the present inventive concept and are not to be considered limiting in its scope, as the overall inventive concept may admit to other equally effective embodiments. The elements and features shown in the drawings are to scale and attempt to clearly illustrate the principles of exemplary embodiments of the present inventive concept. In the drawings, reference numerals designate like or corresponding, but not necessarily identical, elements throughout the several views.
Reference will now be made in detail to the embodiments of the present general inventive concept, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to the like elements throughout. The embodiments are described below in order to explain the present general inventive concept while referring to the figures. Also, while describing the present general inventive concept, detailed descriptions about related well-known functions or configurations that may diminish the clarity of the points of the present general inventive concept are omitted.
It will be understood that although the terms “first” and “second” are used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. Thus, a first element could be termed a second element, and similarly, a second element may be termed a first element without departing from the teachings of this disclosure.
Expressions such as “at least one of,” when preceding a list of elements, modify the entire list of elements and do not modify the individual elements of the list.
All terms including descriptive or technical terms which are used herein should be construed as having meanings that are obvious to one of ordinary skill in the art. However, the terms may have different meanings according to an intention of the inventors, case precedents, or the appearance of new technologies. Also, some terms may be arbitrarily selected by the inventors, and in this case, the meaning of the selected terms will be described in detail in the detailed description herein. Thus, the terms used herein have to be defined based on the generally defined meaning of the terms together with the description throughout this specification.
Hereinafter, one or more exemplary embodiments of the present general inventive concept will be described in detail with reference to accompanying drawings.
Example embodiments of the present general inventive concept are directed to substrates-on-foil which include a metal substrate core and metal component structures patterned within the metal substrate core which are formed of a different metal than the metal core and isolated from the metal substrate core, and methods of making the same.
The metal component structures 206 can be patterned to create any type of in-substrate structure (ISS) desired depending on the ISSs required to complete the semiconductor packages and/or semiconductor boards in which the substrate-on-foil 200 will be integrated with. The metal component structures 206 are preferably formed of copper. However, other types of metals which provide the intended purposes described herein can be used for the metal component structures 206 without departing from the spirit and scope of the overall present inventive concept.
Referring to
It is to be noted that other metal in-substrate structures other than the illustrated coaxial in-substrate structures 206 can be patterned within the metal core 202 by the similar processes as described above with respect to
The metal substrate can be from a metal material selected from a group consisting of: a) Molybdenum; b) Iron; c) Titanium; d) Chromium; e) Tantalum; f) Tungsten; g) Copper; h) Nickel; i) Vanadium; j) Aluminum; k) Cobolt; or any alloy comprised of a) through k). One of the most useful metal alloys in the hermetic seal industry is 52 alloy, which consists of 50.5% Ni with a balance of Fe. 52 alloy and usually has a little Chromium to help the bonding to the dielectric insulating glass. The high Nickel content in 52 alloy gives the substrate a low CTE, on the order of 54×10-7/° C. (5.4 ppm/° C.), which makes the substrate a good candidate for the electronic packaging industry. Molybdenum with a CTE of 48×10-7/° C. (4.8 ppm/° C.) at 25° C. and a high thermal conductivity (138 W/m K) makes the substrate an even better candidate for electronic packaging.
The metal component structures 306 can be patterned to create any type of structural form desired depending on the in-substrate structures ISS required for the intended circuitry in which the metal component structures 306 will be integrated with. The metal component structures 306 are preferably formed of copper. However, other types of metals which provide the intended purposes described herein can be used without departing from the spirit and scope of the overall inventive concept.
It is to be noted that other metal in-substrate structures other than the illustrated coaxial in-substrate structures 306 can be patterned within the metal core 302 by the similar processes as described above with respect to
Number | Date | Country | |
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63487345 | Feb 2023 | US |