Patent Application
20230180636
The present invention relates generally to the field of phase change memory devices and more particularly to suppression of void-formation of phase change memory materials growth in trenches or holes.
Phase Change Memory (PCM) devices are non-volatile memory devices in which the state of the memory elements can be retained for days to decades without power consumption. Examples of volatile memory devices include Dynamic Random-Access Memory (DRAM) and Static Random-Access Memory (SRAM); where DRAM requires the memory element to be constantly refreshed while SRAM requires a constant supply of energy to maintain the state of the memory element.
With phase change memory, information is stored in materials that can be manipulated into different phases. Each of these phases exhibit different electrical properties which can be used for storing information. The amorphous and crystalline phases are typically two phases used for bit storage (0's and 1's) since they have detectable differences in electrical resistance. Specifically, the amorphous phase has a higher resistance than the crystalline phase.
Embodiments of the present invention provide a method for forming a semiconductor structure. In an embodiment, a bottom electrode is deposited on a substrate. A dielectric layer is deposited on the bottom electrode. One or more structures are patterned within the dielectric layer. A liner layer is deposited on top of the dielectric layer and the bottom electrode. A selectivity promotion layer is deposited on top of the liner layer. The selectivity promotion layer is etched to expose a top surface of the dielectric layer and a portion of the bottom electrode. A phase change memory material layer is deposited within a void of the one or more structures between the selectivity promotion layer.
Embodiments of the present invention provide for a semiconductor structure. In an embodiment, a bottom electrode is on top of a substrate. A patterned dielectric layer is on top of the bottom electrode. The patterned dielectric layer includes one or more structures. A liner layer is on either sidewall of each structure of the one or more structures. A selectivity promotion layer is on either each liner layer on either sidewall of each structure of the one or more structures. A phase change memory material layer is within the one or more structures between the selectivity promotion layer on either sidewall of each structure of the one or more structures.
Embodiments of the present invention provide a method for forming a semiconductor structure. A selectivity promotional layer is deposited to cover two sidewalls of each structure of one or more structures within a dielectric layer. The one or more structures are selected from the group consisting of a via and a hole. The selectivity promotion layer is thin enough to provide growth selectivity but not affect a current conduction. A phase change memory material layer is deposited within a void of the one or more structures between the selectivity promotion layer. The phase change memory material growth starts from the bottom of each structure of the one or more structures
The above and other aspects, features, and advantages of various embodiments of the present invention will be more apparent from the following description taken in conjunction with the accompanying drawings.
Embodiments of the present invention recognize that phase change memory (PCM) is a proven candidate for storage class memory. Embodiments of the present invention recognize that resistance drift is still an issue in PCM materials in the reset (amorphous) state for long term data stability in multi-bit applications. Embodiments of the present invention recognize that void formation occurs after annealing of as-deposit amorphous PCM materials due to density change that is not controllable. Embodiments of the present invention recognize that void formation occurs during crystalline PCM material growth due to random nucleation on exposed surfaces. Embodiments of the present invention recognize that selective growth is feasible because PCM materials prefer to nucleate and grow on metal nitride surfaces and that removal of a metal nitride layer on the surface and exposed dielectric layers would encourage growth starting inside the trenches or holes.
Embodiments of the present invention use a selectivity promotion layer to cover sidewalls of trenches or holes to create a selective environment to initiate growth starting from the bottom of the trenches or holes to avoid nucleation on the sidewalls. Embodiments of the present invention provide for a selectivity promotion layer that is thin enough to provide growth selectivity but not affect the current conduction.
Detailed embodiments of the claimed structures and methods are disclosed herein. The method steps described below do not form a complete process flow for manufacturing integrated circuits, such as, semiconductor devices. The present embodiments can be practiced in conjunction with the integrated circuit fabrication techniques currently used in the art and only so much of the commonly practiced process steps are included as are necessary for an understanding of the described embodiments. The figures represent cross-section portions of a semiconductor structure after fabrication and are not drawn to scale, but instead are drawn to illustrate the features of the described embodiments. Specific structural and functional details disclosed herein are not to be interpreted as limiting, but merely as a representative basis for teaching one skilled in the art to variously employ the methods and structures of the present disclosure. In the description, details of well-known features and techniques may be omitted to avoid unnecessarily obscuring the presented embodiments.
References in the specification to “one embodiment”, “other embodiment”, “another embodiment”, “an embodiment”, etc., indicate that the embodiment described may include a particular feature, structure or characteristic, but every embodiment may not necessarily include the particular feature, structure or characteristic. Moreover, such phrases are not necessarily referring to the same embodiment. Further, when a particular feature, structure, or characteristic is described in connection with an embodiment, it is understood that it is within the knowledge of one skilled in the art to affect such feature, structure or characteristic in connection with other embodiments whether or not explicitly described.
For purposes of the description hereinafter, the terms “upper”, “lower”, “right”, “left”, “vertical”, “horizontal”, “top”, “bottom”, and derivatives thereof shall relate to the disclosed structures and methods, as oriented in the drawing figures. The terms “overlying”, “atop”, “over”, “on”, “positioned on” or “positioned atop” mean that a first element is present on a second element wherein intervening elements, such as an interface structure, may be present between the first element and the second element. The term “direct contact” means that a first element and a second element are connected without any intermediary conducting, insulating or semiconductor layers at the interface of the two elements.
In the interest of not obscuring the presentation of the embodiments of the present invention, in the following detailed description, some of the processing steps, materials, or operations that are known in the art may have been combined together for presentation and for illustration purposes and in some instances may not have been described in detail. Additionally, for brevity and maintaining a focus on distinctive features of elements of the present invention, description of previously discussed materials, processes, and structures may not be repeated with regard to subsequent Figures. In other instances, some processing steps or operations that are known may not be described. It should be understood that the following description is rather focused on the distinctive features or elements of the various embodiments of the present invention.
In general, the various processes used to form a semiconductor chip fall into four general categories, namely, film deposition, removal/etching, semiconductor doping, and patterning/lithography. Deposition is any process that grows, coats, or otherwise transfers a material onto the wafer. Available technologies include but are not limited to physical vapor deposition (“PVD”), chemical vapor deposition (“CVD”), electrochemical deposition (“ECD”), molecular beam epitaxy (“MBE”) and more recently, atomic layer deposition (“ALD”) among others. Another deposition technology is plasma enhanced chemical vapor deposition (“PECVD”), which is a process that uses the energy within the plasma to induce reactions at the wafer surface that would otherwise require higher temperatures associated with conventional CVD. Energetic ion bombardment during PECVD deposition can also improve the film's electrical and mechanical properties.
Semiconductor lithography is the formation of three-dimensional relief images or patterns on the semiconductor substrate for subsequent transfer of the pattern to the substrate. In semiconductor lithography, the patterns are formed by a light sensitive polymer called a photoresist. The pattern created by lithography or photolithography typically are used to define or protect selected surfaces and portions of the semiconductor structure during subsequent etch processes.
Removal is any process such as etching or chemical-mechanical planarization (“CMP”) that removes material from the wafer. Examples of etch processes include either wet (e.g., chemical) or dry etch processes. One example of a removal process or dry etch process is ion beam etching (“IBE”). In general, IBE (or milling) refers to a dry plasma etch method that utilizes a remote broad beam ion/plasma source to remove substrate material by physical inert gas and/or chemical reactive gas means. Like other dry plasma etch techniques, IBE has benefits such as etch rate, anisotropy, selectivity, uniformity, aspect ratio, and minimization of substrate damage. Another example of a dry etch process is reactive ion etching (“RIE”). In general, RIE uses chemically reactive plasma to remove material deposited on wafers. High-energy ions from the RIE plasma attack the wafer surface and react with the surface material(s) to remove the surface material(s).
The descriptions of the various embodiments of the present invention have been presented for purposes of illustration but are not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein was chosen to best explain the principles of the embodiments, the practical application or technical improvement over technologies found in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.
The methods as described herein can be used in the fabrication of integrated circuit chips or semiconductor chips. The resulting semiconductor chips can be distributed by the fabricator in raw wafer form (that is, as a single wafer that has multiple unpackaged chips), as a bare die, or in a packaged form. In the latter case, the semiconductor chip is mounted in a single chip package (such as a plastic carrier, with leads that are affixed to a motherboard or other higher-level carrier) or in a multichip package (such as a ceramic carrier that has either or both of surface interconnections or buried interconnections). In any case, the semiconductor chip is then integrated with other semiconductor chips, discrete circuit elements, and/or other signal processing devices as part of either (a) an intermediate product, such as a motherboard, or (b) an end product. The end product can be any product that includes semiconductor chips, ranging from toys and other low-end applications to advanced computer products having a display, memory, a keyboard or other input device, and a central processor.
