Claims
- 1. A method for operation of a semiconductor memory device including a memory cell array and a data input circuit, comprising the steps of:receiving an address signal designating a write address; receiving a write data associated with the write address at least one cycle later; holding the received write data in the data input circuit different from the memory cell array; and selecting, as a read data, one of the write data held by the data input circuit and data read from said memory cell array.
- 2. The method according to claim 1, further comprising the step of writing the write data held by the data input circuit in the memory cell array when holding a newly received write data.
- 3. The method according to claim 1, wherein said semiconductor memory device further includes a write address register circuit, and said method further comprises the steps of:holding the address signal associated with the write data held by the data input circuit in the write address register circuit; and comparing newly inputted address signal and the address signal held by the write address register circuit, and producing a comparison result to select the write data held by the data input circuit when the newly inputted address signal hits the address signal held by the write address register circuit.
- 4. The method according to claim 3, wherein said data input circuit holds two write data, and said write address register circuit holds two address signals.
- 5. A method for operation of a semiconductor memory device including a memory cell array, an input buffer and a write register, comprising the steps of:receiving write data supplied to the input buffer; storing the received write data in the write register in response to a write request in a first cycle; holding the stored write data until receiving a write request in a second cycle subsequent to the first cycle; selecting a memory cell in said memory cell array; and writing write data held by said write register to the selected memory cell in response to the write request in the second cycle.
- 6. The method according to claim 5, further comprising the step of storing newly received write data in said write register in response to the write request in the second cycle.
- 7. The method according to claim 5, wherein said write register continuously holds write data during a third cycle inserted between the first and second cycles in which read data is read from the cell array.
- 8. The method according to claim 5, wherein said semiconductor memory device further includes a write address register circuit, and said method further comprises the steps of:holding an address signal associated with write data held by said write register in the write address register circuit; comparing newly inputted address signal and the address signal held by the write address register circuit; and selectively outputting one of write data held by said write register and data read from said memory cell array in response to the comparison result of the step of comparing.
- 9. The method according to claim 5, wherein the write data associated with the write request in the first cycle is stored at least one cycle later.
Priority Claims (1)
Number |
Date |
Country |
Kind |
5-326919 |
Dec 1993 |
JP |
|
Parent Case Info
This application is a Continuation of application Ser. No. 09/005,688 filed Jan. 13, 1998 now U.S. Pat. No. 6,026,048, which is a Continuation of application Ser. No. 08/846,206 filed Apr. 28, 1997 now U.S. Pat. No. 5,752,270, which is a Continuation of application Ser. No. 08/605,565 filed Feb. 22, 1996 abandoned, which a Divisional of application Ser. No. 08/354,767 filed Dec. 12, 1994 now U.S. Pat. No. 5,515,325.
US Referenced Citations (12)
Foreign Referenced Citations (9)
Number |
Date |
Country |
62-250583 |
Oct 1987 |
JP |
1-58591 |
Dec 1989 |
JP |
2-83895 |
Mar 1990 |
JP |
2-137189 |
May 1990 |
JP |
3-34190 |
Feb 1991 |
JP |
3-58386 |
Mar 1991 |
JP |
3-76094 |
Apr 1991 |
JP |
4-184791 |
Jul 1992 |
JP |
5-144269 |
Jun 1993 |
JP |
Continuations (3)
|
Number |
Date |
Country |
Parent |
09/005688 |
Jan 1998 |
US |
Child |
09/477560 |
|
US |
Parent |
08/846206 |
Apr 1997 |
US |
Child |
09/005688 |
|
US |
Parent |
08/605565 |
Feb 1996 |
US |
Child |
08/846206 |
|
US |