The present application claims priority on the basis of the following provisional applications: Ser. No. 60/130,616 entitled “Multi-Pair Gigabit Ethernet Transceiver” filed on Apr. 22, 1999, Ser. No. 60/116,946 entitled “Multiple Decision Feedback Equalizer” filed on Jan. 20, 1999, and Ser. No. 60/108,319 entitled “Gigabit Ethernet Transceiver” filed on Nov. 13, 1998. The present application is related to the following co-pending applications filed on the same day as the present application and assigned to the same assignee, the contents of each of which are herein incorporated by reference: Ser. No. 09/370,491 entitled “High-Speed Decoder for a Multi-Pair Gigabit Transceiver”, Ser. No. 09/370,353 entitled “Multi-Pair Transceiver Decoder System with Low Computation Slicer”, Ser. No. 09/370,370 entitled “System and Method for Trellis Decoding in a Multi-Pair Transceiver System”.
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Entry |
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“High-Speed VLSI Implementation of Reduced Complexity Sequence Estimation Algorithms with Application to Gigabit Ethernet 1000Base-T”, by Erich F. Haratsch, International Symposium on VLSI Technology, Systems and Applications, Jun. 8-10, 1999, pp. 171-174, XP002136642, Piscataway, USA. |
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IEEE Draft P802.3ab/D5.0, Dec. 10, 1998, pp. 40-ii to 40-129, Piscataway, USA. |
Number | Date | Country | |
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60/130616 | Apr 1999 | US | |
60/116946 | Jan 1999 | US | |
60/108319 | Nov 1998 | US |