Patent Application
20070155154
Regarding semiconductor devices, there is a desire to increase interconnect density and electrical performance of IC packages. For example, there is a push to provide flip chips having ever smaller bump pitch. Flip chip technologies, including “Controlled Collapse Chip Connection” (C4) technology, may provide a proven mechanism for electrically connecting a die to a mounting substrate.
There is a desire to decrease bump pitch for high I/O and high power chips. The push for reduced bump pitch may result in corresponding decreases in via size opening, bump size, bump height, etc. Consequently, in some instances, a process of creating solder bumps (i.e., solder bumping)
Reliability of a flip chip may be impacted by the construction of the solder bumps and other assembly factors, including understanding and controlling the systems and methods to create the solder bumps. Variations in a bumping process or aspects thereof may result in a failure and/or reduced reliability of a flip chip device.
The several embodiments described herein are solely for the purpose of illustration. Embodiments may include any currently or hereafter-known versions of the elements described herein. Therefore, persons in the art will recognize from this description that other embodiments may be practiced with various modifications and alterations.
Some embodiments hereof provide a manufacturing process for producing a flip chip package. In some embodiments, the flip chip is formed using a wafer substrate that has a conductive solder bump formed in an opening in solder resist material disposed on a surface of the substrate. In a process of forming the solder bump, a barrier layer is placed on top of the solder resist material that is on the substrate, and a mask material is placed on top of the barrier layer.
Placing the barrier layer between the solder resist material and the mask material, in some embodiments, may provide a mechanism for efficiently removing the mask material from the solder resist, wherein a quantity of residual mask material remaining on the solder resist is reduced, minimized, or eliminated.
Referring to
At operation 105, a wafer including a substrate is created, obtained, or otherwise provided for use in process 100. The substrate may be produced or formed using any number of methods of IC (integrated circuit) manufacturing processes that result in a substrate suitable and compatible with the various aspects and embodiments herein.
In some embodiments, the substrate may include a single or multilayer dielectric material. The dielectric material may be selected to include any number of materials compatible with and suitable for IC manufacturing processes, not limited to those explicitly discussed herein. Furthermore, those skilled in the art are familiar with the range of substrate materials compatible with the various embodiments herein. In some embodiments, the substrate may include build-up layers of ABF (Ajinomoto Build-Up Film) or other organic film layer.
At operation 110, a barrier layer is provided on top of the solder resist material. The barrier layer may be deposited, created, formed, and otherwise disposed on top of the solder resist material in a variety of methods and processes, including those consistent and compatible with IC manufacturing techniques and other aspects herein. In some embodiments a thin barrier layer may be applied to the top of the solder resist using an autocatalytic process. For example, an electroless Cu (copper) deposition process may be used to plate a thin layer of Cu on top of the solder resist material.
The barrier layer may be placed on top of the solder resist material using a number and variety of techniques to apply the barrier layer comprising a number of different materials
At operation 115, at least one layer of mask material is applied, placed, deposited, disposed, or otherwise provided on top of the barrier layer. In this manner, the barrier layer is between and separates the mask material from the solder resist material.
In some embodiments herein, the mask material comprises a disposable mask. In some embodiments, a disposable mask may be used to facilitate control of the solder bumping processes of the various embodiments herein. For example, a disposable mask that is used for a single run of a solder bumping process may provide precise mask coverage and solder bumps having consistent features (e.g., height, size, etc.) since the disposable mask is not degraded due to repeated use thereof.
In some embodiments hereof, the barrier layer may include materials that can be effectively and/or efficiently removed from the mask material such that substantially all of the mask material may be removed from the barrier layer. In some embodiments, the mask material is removed using techniques, processes, and methods consistent with IC manufacturing flows.
At operation 120, solder placed in an opening that is formed through the mask material, the barrier layer, and the solder resist is subjected to a reflow process. In some embodiments, the solder may be placed into the opening using a solder printing technique to place a solder paste in the opening. It should be appreciated that the solder should be compatible with IC manufacturing processes and the various embodiments herein, and may be placed in the opening through the mask material, barrier layer, and solder resist material in a variety of methods and techniques.
The solder is subjected to a thermal reflow process to create a solder bump in the opening formed through the mask material, barrier layer, and solder resist material. In some embodiments, the solder bump may have a substantially spherical upper surface. Sidewalls of the opening may act to contain the solder therebetween during the reflow process.
At operation 125, the mask material and the barrier layer are removed from the solder resist material. Removal of mask material and the barrier layer after the reflow process reduces or eliminates potential lift-off of solder material that may otherwise occur in an instance the mask material were removed prior to the reflow process. In some embodiments, the presence of the barrier layer facilitates the complete removal of the mask material since the barrier layer separates the mask material from the solder resist and the barrier layer may be efficiently removed from the solder resist material. In this manner, an ability of the mask material to adhere to the solder resist may be minimized or eliminated by placement of the barrier layer between the mask material and the solder resist material. For example, an interaction between the mask material and the solder resist material such as, for example, cross-linking, bonding, etc. between the different materials, may be eliminated or reduced.
In some embodiments, such as when the barrier layer comprises a metal (e.g., electroless Cu) and the solder resist material and the mask material include organic materials, the barrier layer does not readily or effectively adhere to the mask or solder resist material.
In some embodiments, the barrier layer may be removed or stripped from the solder resist material using a quick chemical etch process. In some embodiments, the mask material and/or the barrier layer may be removed from the solder resist material a chemical etch technique, a laser ablation technique, a mechanical removal technique, and combinations thereof.
In some embodiments herein, the barrier layer and the removal of mask material and barrier layer after the reflow process to create the solder bump facilitates a mechanism for providing consistent or uniform solder bumps. By controlling the size of the opening, the amount of solder placed in the opening, and effective removal of the mask material after the reflow process, the amount of solder subjected to the reflow process may be consistently maintained. Thus, consistent or uniform solder bumps may be provided in accordance with some of the embodiments herein.
In some embodiments, the height of the solder bumps created in accordance with some embodiments herein may vary about 5 micrometers (μm) or less.
At
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In some embodiments herein, an opening created through the mask material, the barrier layer, and the solder resist material may be done substantially at the same time. For example, the opening through the mask material, the barrier layer, and the solder resist material may be made using a laser beam in a laser projection patterning (LPP) process. Other methods, techniques, and processes may be used to create the opening through the the mask material, the barrier layer, and the solder resist material. In this manner, alignment of the opening through the mask material, the barrier layer, and the solder resist material may coincide with each other (i.e., align).
In some embodiments, an alignment tolerance of about 5 μm or less may be achieved for the opening through the various layers 210 (310), 215 (315), and 220 (320) at the same time.
In some embodiments, an IC device 415 is placed in contact with solder bumps 420. IC device 415 may contact solder bumps 420 at conductive connectors, pads, and traces (not shown) to provide electrical connectivity between IC device 415 and substrate 405, through solder bumps 420. In some embodiments, an apparatus, system, and device may include solder bumps 420 created by removing a mask material (not shown) (e.g., a disposable mask material) previously disposed on top of a barrier layer (not shown) that was disposed on top of solder resist material 410 and subsequently removed therefrom after a reflow process used to create solder bumps 420.
It should be appreciated that the drawings herein are illustrative of various aspects of the embodiments herein, not exhaustive of the present disclosure. For example,
The several embodiments described herein are solely for the purpose of illustration. Persons in the art will recognize from this description that other embodiments may be practiced with modifications and alterations limited only by the claims.
