This application relates generally to managing data in a memory system. More specifically, this application relates to analyzing data in sections of memory to detect a write abort.
A memory system, such as non-volatile flash memory system, may comprise a plurality of memory cells in which data may be stored. In operation, the memory controller of the memory system may program and/or erase the memory cells. Occasionally, the memory controller may experience an abrupt power shutdown during an ongoing write operation to the memory cells. The abrupt power shut down may generate an undesirable condition whereby the memory cells are programmed or erased to un-certain levels. More specifically, due to the abrupt power shutdown, the memory controller was unable to verify the program or erase of the memory cells.
At the next power-up, the memory controller and a host device may verify which blocks were programmed and/or erased properly, and which blocks were not and, in turn, should be marked as write abort blocks. For example, the memory controller may scan the memory blocks that were last written (according to stored metadata) and count the number of programmed bits (logic “0”s) in each flash memory unit (FMU) in a wordline (WL), which may be composed of multiple FMUs.
The memory controller then compares the count with multiple thresholds. In particular, in the event that the count is less than a first threshold (e.g., an erased threshold), the memory controller designates the FMU as an erased FMU. In the event that the count is greater than a second threshold (e.g., a programmed threshold), the memory controller designates the FMU as a programmed FMU. Finally, in the event that the count is between the first threshold and the second threshold, the memory controller designates the FMU as a suspected write abort FMU.
Blocks that include suspected write abort FMUs are designated as write abort blocks. In response to this designation, the memory controller will not access the designated blocks, either for a write or an erase. During the memory system's lifetime, the number of marked write abort blocks increases, thereby reducing the memory system's performance and increasing the likelihood of the memory system's failure.
Systems and methods for determining a write abort in a memory system are disclosed. In one aspect, a memory system is disclosed. The memory system includes a differential generator module configured to generate a differential between an aspect in data values stored a first section in memory and the aspect in data values stored a second section in memory; a comparison module configured to compare the differential with a differential threshold; and a write abort module configured to determine, based on the comparison of the differential with the differential threshold, whether at least one of the first section or the second section is subject to a write abort.
In another aspect, a method for determining whether a write abort occurred when writing to a section of memory is disclosed. The method includes: reading a first part of the section of the memory in order to generate a first count; reading a second part of the memory in order to generate a second count; comparing the first count with the second count; and determining, based on the comparison of the first count with the second count, whether a write abort occurred at the first section of the memory.
Other features and advantages will become apparent upon review of the following drawings, detailed description and claims. Additionally, other embodiments are disclosed, and each of the embodiments can be used alone or together in combination. The embodiments will now be described with reference to the attached drawings.
The system may be better understood with reference to the following drawings and description. In the figures, like reference numerals designate corresponding parts throughout the different views.
Prior to programming a section of a memory system, the section may be in a predetermined state. After which, part or all of the section of memory may be programmed. For example, in flash memory, a block is erased prior to programming in order to put the memory cells in the block to the logic “1” state. Thereafter, the memory cells in the block may be programmed. In one implementation, the block is composed of multiple pages, with each page being composed of the memory cells along a single wordline (WL), illustrated below in
An abrupt power shutdown that occurs during programming may result in the memory cells being in an indeterminate state. For example, in flash memory, the memory cells that comprise the FMU may be in one of three states: (1) erased; (2) programmed; or (3) indeterminate state.
One may analyze the values stored in a part of the block, such as count the logic “0” in a part of the block (e.g., count the values stored in an FMU), and compare it to one or more thresholds in order to determine the state of the FMU. In the example of an erased FMU, the memory cells should be in the logic “1” state (i.e., few of the memory cells are in the “0” state). In this regard, the count of logic “0” in a respective FMU is compared to Threshold1, which may be considered an erased threshold. If the count is less than Threshold1, the respective FMU is designated as being erased. Conversely, in the example of a programmed FMU, fewer memory cells should be in the logic “1” state (i.e., more of the memory cells are in the “0” state). In this regard, the count of logic “0” in a respective FMU is compared to Threshold2, which may be considered a programmed threshold. If the count is greater than Threshold2, the respective FMU is designated as being programmed. Finally, if the count is between Threshold1 and Threshold2, the respective FMU is designated as being in the indeterminate state.
Simply comparing the count in the FMU to one or more thresholds may be unreliable. More specifically, variables within the memory system may result the values stored in the memory cells being unreliable. In turn, the count being based on the values stored in the memory cells may be unpredictable, resulting in the comparison of the count with the thresholds potentially generating erroneous results. As one example, the memory system may have one or more bad columns. As illustrated in
As another example, the memory system performance degrades with age. More specifically, flash performance may degrade due to large number of program/erase (P/E) cycles, resulting in charge loss from floating gates, erased tails, and the like. The degrading in performance results in an erroneous count, and in turn, a potentially erroneous designation as a suspected write abort block.
In one embodiment, the state (e.g., programmed, erased, or indeterminate) of a first section of memory is determined, and in turn, whether a write abort occurred when programming the first section of memory. In order to perform the determination, the first section of memory and a second section of memory are analyzed. The first and second sections may comprise any part of the memory, such as different FMUs, different wordlines, or the like.
The second section of memory may be selected based on at least one similar aspect to the first section of memory and/or based on a known or suspected state of the second section of memory. In one embodiment, the second section of memory may be selected to be from the same block (or other similar sub-part of the memory) as the first section of memory. In this regard, errors due to programming and/or erasing of the first section of memory may likewise occur in programming and/or erasing of the second section of memory, with the differential canceling (or reducing the effect of) the errors. In the instance of bad column errors, affecting programming of cells in the first section of memory, the second section of memory, which may experience the same or similar bad column errors, may be selected, thereby reducing the effect of the bad column errors. In another embodiment, the second section of memory may be selected based on a known or suspected state, such as known/suspected to be erased or known/suspected to be programmed. In this way, comparing the first section of memory with the known state of the second section of memory may more easily establish the state of the first section of memory.
Further, the analysis may comprise counting values stored in the memory cells in the respective section of memory, such as counting the logic “0”s or the logic “1”s in the FMU. The analysis of the first section of memory and the analysis of the second section of memory may be compared. For example, the count of the “0”s in the memory cells of the first section of memory may be compared with the count of the “0”s in the memory cells of the second section of memory. More specifically, the difference in the counts of the “0”s in the first and second sections of memory may be determined, as discussed in more detail below. Based on the comparison, the state of the first section of memory is determined. For example, the difference in the counts of the “0”s in the first and second FMUs may be compared to a difference threshold. If the difference is less than the threshold, the first FMU may be designated as truly erased.
In the context of write abort analysis, generating a differential between an aspect of data values stored in the first section of memory (e.g., the count of the logic “0”s in the first section of memory) and the aspect of data values stored in the second section of memory may result in a more reliable indicator whether a write abort has occurred. More specifically, the memory system may have errors that, in turn, result in common errors for data values stored in the first and second sections of memory. As one example, bad column errors will appear in all WLs of a respective block connected to the bad columns. Thus, if a first FMU in the respective block is being analyzed, a second FMU in the respective block may suffer from the same bad column errors. As another example, block age-related errors, such as due to a high number of P/E cycles, may affect the entire block in a similar manner. In this regard, the first FMU and the second FMU, both in the same respective block, may suffer from the same or similar block age-related errors. Because the differential of an aspect of the data values stored in the first and second sections of memory is generated, the common errors manifested in the data values may be reduced or eliminated, thereby rendering the differential as a more reliable indicator in determining whether a write abort has occurred. Thus, instead of only analyzing the at least one aspect alone (e.g., comparing the count of logic “0”s against a threshold), the differential between the aspects of the data values stored in the first and second sections of memory may result in a reduction in the noise due to common errors.
In one embodiment, both the aspect of the data values stored in the first section of memory and the differential of the aspect of the data values stored in the first section and the second section are analyzed to determine whether a write abort has occurred. For example, both the count of the logic “0”s in a first FMU is compared against multiple thresholds, and the differential of the count of the logic “0”s in the first FMU and the second FMU is compared against at least one threshold in order to determine whether a write abort has occurred, as discussed in more detail below. In an alternate embodiment, only the differential of the aspect of the data values stored in the first section and the second section is analyzed to determine whether a write abort has occurred.
Further, the second section of memory, used to generate the differential with the first section of memory, may be selected based on one or more criteria. In one embodiment, the second section of memory is selected such that it is in the same sub-part of the memory as the first section of memory. For example, the first section of memory may comprise a first FMU in a respective block. The second section of memory may comprise a second FMU in the same respective block. As the first and second FMUs are from the same block, common errors may be reduced, as discussed above. In another embodiment, the second section of memory may be selected based on a known or reasonable belief as to its state. For example, the second section of memory may comprise an FMU in the last WL of a block. The last WL of the block is the last to be programmed. Thus, the last WL is the most likely WL in the block to be in the totally erased state, and is a good baseline for a section of memory that is erased. Conversely, the second section of memory may comprise an FMU in the first WL of a block. The first WL of the block is the first to be programmed. Thus, the first WL is the most likely to be in the programmed or non-erased state, and is a good baseline for a section of memory that is programmed or non-erased.
Controller 102 can take the form of a microprocessor or processor and a computer-readable medium that stores computer-readable program code (e.g., software or firmware) executable by the (micro)processor, logic gates, switches, an application specific integrated circuit (ASIC), a programmable logic controller, and an embedded microcontroller, for example. Controller 102 can be configured with hardware and/or software to perform the various functions described below and shown in the flow diagrams. Also, some of the components shown as being internal to the controller can also be stored external to the controller, and other components can be used. Additionally, the phrase “operatively in communication with” could mean directly in communication with or indirectly (wired or wireless) in communication with through one or more components, which may or may not be shown or described herein.
Non-volatile memory die 104 may include any suitable non-volatile storage medium, including NAND flash memory cells and/or NOR flash memory cells. The memory cells can take the form of solid-state (e.g., flash) memory cells and can be one-time programmable, few-time programmable, or many-time programmable. The memory cells can also be single-level cells (SLC), multiple-level cells (MLC), triple-level cells (TLC), or use other memory technologies, now known or later developed. Also, the memory cells can be arranged in a two-dimensional or three-dimensional fashion.
Thus, the memory may be a semiconductor memory device that includes volatile memory devices, such as dynamic random access memory (“DRAM”) or static random access memory (“SRAM”) devices, non-volatile memory devices, such as resistive random access memory (“ReRAM”), electrically erasable programmable read only memory (“EEPROM”), flash memory (which can also be considered a subset of EEPROM), ferroelectric random access memory (“FRAM”), and magnetoresistive random access memory (“MRAM”), and other semiconductor elements capable of storing information. Each type of memory device may have different configurations. For example, flash memory devices may be configured in a NAND or a NOR configuration.
The memory system can be formed from passive and/or active elements, in any combinations. By way of non-limiting example, passive semiconductor memory elements include ReRAM device elements, which in some embodiments include a resistivity switching storage element, such as an anti-fuse, phase change material, etc., and optionally a steering element, such as a diode, etc. Further by way of non-limiting example, active semiconductor memory elements include EEPROM and flash memory device elements, which in some embodiments include elements containing a charge storage region, such as a floating gate, conductive nanoparticles, or a charge storage dielectric material.
Multiple memory elements may be configured so that they are connected in series or so that each element is individually accessible. By way of non-limiting example, flash memory devices in a NAND configuration (NAND memory) typically contain memory elements connected in series. A NAND memory array may be configured so that the array is composed of multiple strings of memory in which a string is composed of multiple memory elements sharing a single bit line and accessed as a group. Alternatively, memory elements may be configured so that each element is individually accessible, e.g., a NOR memory array. NAND and NOR memory configurations are exemplary, and memory elements may be otherwise configured.
The semiconductor memory elements located within and/or over a substrate may be arranged in two or three dimensions, such as a two dimensional memory structure or a three dimensional memory structure.
In a two dimensional memory structure, the semiconductor memory elements are arranged in a single plane or a single memory device level. Typically, in a two dimensional memory structure, memory elements are arranged in a plane (e.g., in an x-z direction plane) which extends substantially parallel to a major surface of a substrate that supports the memory elements.
The substrate may be a wafer over or in which the layer of the memory elements are formed or it may be a carrier substrate which is attached to the memory elements after they are formed. As a non-limiting example, the substrate may include a semiconductor such as silicon.
The memory elements may be arranged in the single memory device level in an ordered array, such as in a plurality of rows and/or columns. However, the memory elements may be arrayed in non-regular or non-orthogonal configurations. The memory elements may each have two or more electrodes or contact lines, such as bit lines and word lines.
A three dimensional memory array is arranged so that memory elements occupy multiple planes or multiple memory device levels, thereby forming a structure in three dimensions (i.e., in the x, y and z directions, where the y direction is substantially perpendicular and the x and z directions are substantially parallel to the major surface of the substrate).
As a non-limiting example, a three dimensional memory structure may be vertically arranged as a stack of multiple two dimensional memory device levels. As another non-limiting example, a three dimensional memory array may be arranged as multiple vertical columns (e.g., columns extending substantially perpendicular to the major surface of the substrate, i.e., in the y direction) with each column having multiple memory elements in each column. The columns may be arranged in a two dimensional configuration, e.g., in an x-z plane, resulting in a three dimensional arrangement of memory elements with elements on multiple vertically stacked memory planes. Other configurations of memory elements in three dimensions can also constitute a three dimensional memory array.
By way of non-limiting example, in a three dimensional NAND memory array, the memory elements may be coupled together to form a NAND string within a single horizontal (e.g., x-z) memory device levels. Alternatively, the memory elements may be coupled together to form a vertical NAND string that traverses across multiple horizontal memory device levels. Other three dimensional configurations can be envisioned wherein some NAND strings contain memory elements in a single memory level while other strings contain memory elements which span through multiple memory levels. Three dimensional memory arrays may also be designed in a NOR configuration and in a ReRAM configuration.
Typically, in a monolithic three dimensional memory array, one or more memory device levels are formed above a single substrate. Optionally, the monolithic three dimensional memory array may also have one or more memory layers at least partially within the single substrate. As a non-limiting example, the substrate may include a semiconductor such as silicon. In a monolithic three dimensional array, the layers constituting each memory device level of the array are typically formed on the layers of the underlying memory device levels of the array. However, layers of adjacent memory device levels of a monolithic three dimensional memory array may be shared or have intervening layers between memory device levels.
Then again, two dimensional arrays may be formed separately and then packaged together to form a non-monolithic memory device having multiple layers of memory. For example, non-monolithic stacked memories can be constructed by forming memory levels on separate substrates and then stacking the memory levels atop each other. The substrates may be thinned or removed from the memory device levels before stacking, but as the memory device levels are initially formed over separate substrates, the resulting memory arrays are not monolithic three dimensional memory arrays. Further, multiple two dimensional memory arrays or three dimensional memory arrays (monolithic or non-monolithic) may be formed on separate chips and then packaged together to form a stacked-chip memory device.
The interface between controller 102 and non-volatile memory die 104 may be any suitable flash interface, such as Toggle Mode 200, 400, or 800. In one embodiment, memory system 100 may be a card based system, such as a secure digital (SD) or a micro secure digital (micro-SD) card. In an alternate embodiment, memory system 100 may be part of an embedded memory system.
Although in the example illustrated in
Back end module 110 includes an error correction controller (ECC) engine 124 that performs encoding on the data bytes received from the host, and decoding and error correction on the data bytes read from the non-volatile memory. A command sequencer 126 generates command sequences, such as program and erase command sequences, to be transmitted to non-volatile memory die 104. A RAID (Redundant Array of Independent Drives) module 128 manages generation of RAID parity and recovery of failed data. The RAID parity may be used as an additional level of integrity protection for the data being written into the memory device 104. In some cases, the RAID module 128 may be a part of the ECC engine 124. A memory interface 130 provides the command sequences to non-volatile memory die 104 and receives status information from non-volatile memory die 104. In one embodiment, memory interface 130 may be a dual data rate (DDR) interface, such as a Toggle Mode 200, 400, or 800 interface. A flash control layer 132 controls the overall operation of back end module 110.
Additional components of system 100 illustrated in
For the portion shown in
To perform a sense portion of a read or copy operation, a page of FGTs and a corresponding wordline may be selected, and current sensing of bitlines may be employed to determine whether a floating gate of a FGT in the selected page contains charge or not. Current flowing through a string may flow from a source line SL, through the string, to the bitline BL to which the string is coupled. The string may be coupled to the source line SL via a source select transistor and may be coupled to its associated bitline BL via a drain select transistor. For example, as shown in
As discussed above, there may be errors in one or more of the bitlines. In this regard, an error in a respective bitline will affect respective cells in different wordlines similarly. For example, if BL0 is faulty, transistor 352a16 in wordline WL16 and transistor 352a47 in wordline WL47 may be similarly affected. Thus, differential analysis of the values of the transistors in the different bitlines may reduce or cancel the affect due to bitline error, as discussed above. For example, the bad column resulting in errors in erasing and/or programming of WL16 may likewise affect erasing and/or programming of WL47. The differential of values stored in WL16 and WL47 may have the effect of canceling or reducing the effect of the bad columns.
In one instance, the last wordline in the block (such as WL47) may be analyzed for write abort detection. In one embodiment, determination that the last wordline in the block may be subject to write abort detection may automatically result in designating the block as write abort. In an alternate embodiment, the values stored in the last wordline in the block may be compared with values stored in another section of the memory, such as values stored in the second-to-last wordline in the block. The comparison may comprise generating a differential value, as discussed above.
As discussed above, the detection method of write abort WLs may include reading the number of logic “0”s in a FMU in a WL (designated as “N”) in a suspected block after power-on. N may be used in multiple ways, including comparing N to one or more thresholds, and determining the differential of N with another FMU.
In a more specific embodiment, N may first be compared with one or more thresholds, and dependent on the comparison of N with the one or more thresholds, the differential of N with another FMU may be determined. For example, if N is between threshold1 (which may be a value of 30) and threshold2 (which may be a value of 60), the method includes reading the number of logic “0”s in a FMU in the last WL in the block, NL. Next, the method includes calculating the difference between the number of “0” in the WL FMU, N, and the number of logic “0” in the last WL FMU (designated as NL) in the block. The method further includes marking the block as a write-abort block if the difference of logic “0”s, N-NL, is above a differential truly-erased (TER) threshold pre-defined value. The differential TER threshold may be 5, however other differential TER threshold values like 10 or more may be determined and furthermore may be changed during the product life time.
At 706, it is determined if N is greater than threshold2 (e.g., in programmed FMU 630 illustrated in
Accordingly, the methods and systems discussed herein may be realized in hardware, software, or a combination of hardware and software. The method and system may be realized in a centralized fashion in at least one electronic device (such as illustrated in memory system 100 in
The method and system may also be implemented using a computer-readable media. For example, abort management module 112 may be implemented using computer-readable media to implement the functionality described herein, such as discussed in
Alternatively or in addition, dedicated hardware implementations, such as application specific integrated circuits, programmable logic arrays and other hardware devices, may be constructed to implement one or more of the methods described herein. Applications that may include the apparatus and systems of various embodiments may broadly include a variety of electronic and computer systems. One or more embodiments described herein may implement functions using two or more specific interconnected hardware modules or devices with related control and data signals that may be communicated between and through the modules, or as portions of an application-specific integrated circuit. Accordingly, the present system may encompass software, firmware, and hardware implementations.
The above-disclosed subject matter is to be considered illustrative, and not restrictive, and the appended claims are intended to cover all such modifications, enhancements, and other embodiments, which fall within the true spirit and scope of the present disclosure. Thus, to the maximum extent allowed by law, the scope of the present embodiments are to be determined by the broadest permissible interpretation of the following claims and their equivalents, and shall not be restricted or limited by the foregoing detailed description. While various embodiments have been described, it will be apparent to those of ordinary skill in the art that many more embodiments and implementations are possible within the scope of the above detailed description. Accordingly, the embodiments are not to be restricted except in light of the attached claims and their equivalents.
This application claims the benefit of U.S. Provisional Application No. 62/072,720, which is hereby incorporated by reference herein in its entirety.
Number | Date | Country | |
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62072720 | Oct 2014 | US |