Patent Application
20220408565
The present disclosure generally relates to formation of electronic circuitry and electronic devices and in particular, to methods for using surface mounts technology on metal substrates.
As electronic and processing devices evolve, there is an increased need to miniaturize and integrate electronic components. Currently, many conventional device components are assembled using soldering techniques. For such techniques, components are generally soldered onto a rigid or flex printed circuit substrate to form a printed circuit board assembly (PCBA), with typical lead free process temperature ranges of 220 to 250° C. or more, or typical tin lead process temperature ranges of 180 to 220° C. Once the PCBA is formed, it is then attached or integrated into a device, a device portion or a product chassis, such as to form a final product.
With the advent of 3-dimensional (3D) printing and structural electronics, devices or products of various and/or unique shapes, sizes and/or dimensions, often in relative miniature scale, are being fabricated, and these unique devices and products often require dedicated cavities, spaces and/or areas to accommodate the aforementioned PCBA circuitry. Among various drawbacks, such as the at least partially inflexible nature of most conventional PCBA circuitry arrangements, the insertion of electronics to these devices may carry a significant cost in space requirements that is highly undesirable because of the referenced unique and often miniature nature of these products and devices.
Described herein is a system and method for placing surface mount technology components directly onto a metal substrate with circuitry pattern. A method for forming a circuit pattern on a metal substrate structure includes providing the metal substrate structure with an insulating surface which includes a pattern forming portion. An activation ink is deposited (i.e. printed and other similar techniques) only on the pattern forming portion of the insulating surface to form a non-conductive isolation layer on the pattern forming portion of the insulating surface. A first metal layer is formed on the non-conductive isolation layer by electroless plating. A patterned portion of the first metal layer is isolated from a remaining portion of the first metal layer to form the circuit pattern. A non-conductive masking layer is applied on the first metal layer. A second metal layer is formed on the non-conductive masking layer. A surface mount land pattern and pad configuration is determined. A solder mask layer is applied to the patterned portion to protect the circuit pattern. A protective layer is applied to protect the pad areas not covered by the solder mask layer.
Other features and advantages of the disclosure will become apparent in the following detailed description of the exemplary embodiment with reference to the accompanying drawings, of which:
The figures and descriptions provided herein may have been simplified to illustrate aspects that are relevant for a clear understanding of the herein described devices, systems, and methods, while eliminating, for the purpose of clarity, other aspects that may be found in typical similar devices, systems, and methods. Those of ordinary skill may thus recognize that other elements and/or operations may be desirable and/or necessary to implement the devices, systems, and methods described herein. But because such elements and operations are known in the art, and because they do not facilitate a better understanding of the present disclosure, a discussion of such elements and operations may not be provided herein. However, the present disclosure is deemed to nevertheless include all such elements, variations, and modifications to the described aspects that would be known to those of ordinary skill in the art.
Exemplary embodiments are provided throughout so that this disclosure is sufficiently thorough and fully conveys the scope of the disclosed embodiments to those who are skilled in the art. Numerous specific details are set forth, such as examples of specific components, devices, and methods, to provide a thorough understanding of embodiments of the present disclosure.
Nevertheless, it will be apparent to those skilled in the art that specific disclosed details need not be employed, and that exemplary embodiments may be embodied in different forms. As such, the exemplary embodiments should not be construed to limit the scope of the disclosure. In some exemplary embodiments, well-known processes, well-known device structures, and well-known technologies may not be described in detail.
The terminology used herein is for the purpose of describing particular exemplary embodiments only and is not intended to be limiting. As used herein, the singular forms “a”, “an” and “the” may be intended to include the plural forms as well, unless the context clearly indicates otherwise. The terms “comprises,” “comprising,” “including,” and “having,” are inclusive and therefore specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. The steps, processes, and operations described herein are not to be construed as necessarily requiring their respective performance in the particular order discussed or illustrated, unless specifically identified as a preferred or required order of performance. It is also to be understood that additional or alternative steps may be employed, in place of or in conjunction with the disclosed aspects.
When an element or layer is referred to as being “on”, “engaged to”, “connected to” or “coupled to” another element or layer, it may be directly on, engaged, connected or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being “directly on,” “directly engaged to”, “directly connected to” or “directly coupled to” another element or layer, there may be no intervening elements or layers present. Other words used to describe the relationship between elements should be interpreted in a like fashion (e.g., “between” versus “directly between,” “adjacent” versus “directly adjacent,” etc.). As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items.
Although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms may be only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Terms such as “first,” “second,” and other numerical terms when used herein do not imply a sequence or order unless clearly indicated by the context. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the exemplary embodiments.
Described herein is a system and method for placing surface mount technology (SMT) components directly onto a metal substrate with circuitry pattern or similar substrate. For purposes of illustration only, an integrated substrate can include a metal baseplate covered by a thin layer of dielectric and a layer of copper.
The integrated substrate structure is processed in accordance with
As described above, an integrated substrate structure (also referred to as substrate herein) is provided (block 305). For example, the integrated substrate structure can be a part of a product using a heat sink 200, such as a cell phone, a touch panel, a watch, glasses, etc. Referring now also to
An activation ink is printed on a portion 415 (pattern forming region) of insulating surface 410 so as to form a non-conductive isolation layer or activation layer 420 on portion 415 of insulating surface 410 (block 315). Note that non-conductive isolation layer 420 is initially the same dimensions as portion 415 prior to the processing described herein. In certain embodiments, non-conductive isolation layer 420 may include a catalyst metal element which is selected from the group consisting of palladium, rhodium, platinum, silver, and combinations thereof. In certain embodiments, non-conductive isolation layer 420 may be made of a metal oxide compound that is electrically non-conductive. Activation ink printing can be conducted by digital printing, screen printing, pad printing, transfer printing, coating, spraying, or powder coating techniques. These techniques are illustrative and non-limiting. Activation ink can include but is not limited to N-methyl-2-pyrrolidone (NMP) which can slightly etch insulating surface 410 when the same is being applied onto insulating surface 410. As such, a conventional step of roughening insulating surface 410 to increase the bonding strength between activation layer 420 and insulating surface 410 may be omitted.
A first metal layer 425 is formed on activation layer 420 by electroless plating (block 320). In certain embodiments, this may be conducted by placing the substrate with the non-conductive isolation layer 420 into an electroless plating solution for a predetermined period of time, so as to perform the electroless plating reaction. In certain embodiments, first metal layer 425 may have a thickness ranging from 0.1 μm to 0.25 μm. In certain embodiments, first metal layer 425 may be made of nickel, but is not limited thereto. For example, first metal layer 425 may be made of copper in certain embodiments.
A patterned portion 422, (also known as circuit or trace pattern), is isolated from a remaining portion 423 (block 325), where portion 415 is equal to patterned portion 422 plus remaining portion 423. In certain embodiments, this may include removing part of first metal layer 425 so as to form a gap (not shown) along an outer periphery of patterned portion 422 to isolate patterned portion 422 of first metal layer 425. The removal of the part of first metal layer 425 may be conducted by laser ablation. In certain embodiments, patterned portion 422 of first metal layer 425 may be surrounded by remaining portion 423 of first metal layer 425. In certain embodiments, a patterned portion of non-conductive isolation layer 420 may be isolated, e.g., by laser ablation, where patterned portion of non-conductive isolation layer 420 corresponds in position to patterned portion 422 of first metal layer 425 as described herein. In certain embodiments, where activation layer 420 is electrically non-conductive, the gap does not need to extend into non-conductive isolation layer 420 considering the subsequent electroplating process.
A second metal layer 430 is formed on patterned portion 422 of first metal layer 425 by electroplating (block 330). In certain embodiments, second metal layer 430 may be made of copper, i.e., using copper-containing electroplating solution with copper electrodes during the electroplating process. In certain embodiments, second metal layer 430 may have a thickness ranging from 0.2 μm to 0.5 μm. Since patterned portion 422 of first metal layer 425 is isolated from remaining portion 423, second metal layer 430 can only be formed on patterned portion 422 of first metal layer 425 during the electroplating process.
In certain embodiments, the method may further include a step of removing remaining portion 423 of first metal layer 425. Such a step may be performed by wet-etching techniques or laser ablation and is not limited thereto according to the present disclosure.
In certain embodiments, the method may further include a step of removing part of non-conductive isolation layer 420 which is located outside patterned portion 422. Such a step may be performed by applying a stripping solution onto the substrate, e.g., by spraying the stripping solution onto the substrate or by dipping the substrate into the stripping solution. As such, non-conductive isolation layer 420 is softened due to the stripping solution, and the bonding between non-conductive isolation layer 420 and insulating surface 410 of the substrate is diminished, thereby allowing the same to be removed from insulating surface 410 of the substrate. In certain embodiments, the step of removing non-conductive isolation layer 420 may be conducted by laser ablation.
Surface mount land pattern(s) for soldering are determined, followed by a pad configuration for the determined pattern (block 335). In order to provide desired connectivity and to increase reliability of the attachment of the surface mount components, specific pad layouts on the integrated substrate structure may be designed to increase and/or maximize the amount of integrated substrate structure and pad surface area contact. Such a configuration should promote stronger bonding through mechanical and chemical bonds, and also may help to absorb at least some forces created by potential mismatches of CTE between the traces, substrate, interconnect material and the component terminals. An example pad configuration 500 is shown in
A solder mask layer may be applied to cover copper traces (e.g. patterned portion 422) to protect against corrosion, electrical short, avoid oxidation and environmental influences (block 340). If a solder mask is not applied, then the pad configuration design may be reconsidered. For bonding pads, test points and fiducial marks may or may not be required. Moreover, a silkscreen may be applied as a reference designator and pin marker for each SMT component designed for the integrated substrate structure. An example solder mask is shown in
A protective layer is applied to protect the pad areas not covered by solder mask layer and prevent oxidation (block 345). For example, a surface finish/plating layer may be applied which can be a resin layered with a plurality of metals that may include copper (Cu), nickel (Ni) and/or gold (Au), among other materials. Organic Solderability Preservative (OSP) may be used for high/regular temperature integrated substrate structure configurations. Preferably, smooth, glossy plating should be used instead of matte surface finishes, as rough plating surfaces may form inconsistent intermetallic compound thickness which may affect bonding reliability performance.
Referring back to
Once SMT component placement is determined, reflow and/or curing processes (if necessary) are performed (in block 108), followed by electrical testing (block 110) and inspection (block 112). Inspection may occur manually or automatically, such as using machine-vision technologies.
As described above,
Users may be able to assemble SMT components directly onto 3D structures to form a final product and enable integration of mechanical and electronic functions into a single device. Other advantages include, but are not limited to, enabling device miniaturization, integration, rationalization and feature advancement; providing shape flexibility and hybrid configurations that may shorten process chains; providing greater design flexibility to further improve portability and functionality; and reducing number of parts and substrates and total assembly time through integration. There are a wide variety of industry applications, including, but not limited to, automotive lighting applications, consumer applications (e.g., wireless chargers, power transmission touch sensors, camera module etc.), industrial applications (e.g., sensors, power controllers, battery containers, switching modules, OLED, etc.), and microelectronics, power electronics product application especially with high heat dissipation requirement i.e. LED lighting, power conversion, motor drives and semiconductor modules etc. For wire bonding on integrated substrate structure, soft surface finish/plating should be considered i.e. ENEPIG.
While the disclosure has been described in connection with what are considered the exemplary embodiments, it is understood that this disclosure is not limited to the disclosed embodiments but is intended to cover various arrangements included within the spirit and scope of the broadest interpretation so as to encompass all such modifications and equivalent arrangements.
This application is a continuation of U.S. patent application Ser. No. 16/622,381, filed on Dec. 13, 2019, of which is incorporated herein by reference.
| Number | Date | Country | |
|---|---|---|---|
| Parent | 16622381 | Dec 2019 | US |
| Child | 17857664 | US |
