Systems and methods for correcting non-uniformities in plasma processing of substrates

Abstract

An electrostatic chuck includes an embedded electrode receiving a first voltage to electrostatically attract a semiconductor substrate to the electrostatic chuck. A plurality of current loops are disposed in at least one of the electrostatic chuck and an edge ring surrounding the electrostatic chuck. The current loops are laterally spaced apart. Each current loop is a wire formed into a loop. One or more DC power sources are electrically connected to the current loops. A controller supplies the first voltage to the embedded electrode, supplies a DC current to the current loops from the power sources, and controls the power sources. Each current loop is independently operable and generates a localized DC magnetic field proximate to the semiconductor substrate on receiving the DC current during plasma processing of the semiconductor substrate to adjust the plasma processing of the semiconductor substrate. The localized DC magnetic field does not generate plasma.

Description

FIELD

Disclosed herein is a component of a substrate support assembly having a plurality of current loops adapted to generate small magnetic fields and compensate for variations during plasma processing of a semiconductor substrate supported on the substrate support assembly. The component can be an edge ring or substrate support such as a tunable electrostatic chuck (ESC) that allows for improved control of critical dimension (CD) uniformity, as well as methods and uses thereof.

BACKGROUND

In this specification where a document, act or item of knowledge is referred to or discussed, this reference or discussion is not an admission that the document, act or item of knowledge or any combination thereof was at the priority date, publicly available, known to the public, part of common general knowledge, or otherwise constitutes prior art under the applicable statutory provisions; or is known to be relevant to an attempt to solve any problem with which this specification is concerned.

Commonly-owned U.S. Pat. No. 6,921,724 discloses an etch processor for etching a wafer that includes an ESC for holding a wafer and a temperature sensor reporting a temperature of the wafer. The chuck includes a heater controlled by a temperature control system and a temperature sensor is operatively coupled to the temperature control system to maintain the temperature of the ESC at a selectable set-point temperature. A first set-point temperature and a second set-point temperature are selected. The wafer is placed on the chuck and set to the first set-point temperature. The wafer is then processed for a first period of time at the first set-point temperature and for a second period of time at the second set-point temperature.

Commonly-owned U.S. Pat. No. 6,847,014 discloses a ESC for a plasma processor comprising a temperature-controlled base, a thermal insulator, a flat support, and a heater. The temperature-controlled base has a temperature below the desired temperature of a substrate. The thermal insulator is disposed over the temperature-controlled base. The flat support holds a substrate and is disposed over the thermal insulator. A heater is embedded within the flat support and/or disposed on an underside of the flat support and includes a plurality of heating elements that heat a plurality of corresponding heating zones. The power supplied and/or temperature of each heating element is controlled independently.

Commonly-owned U.S. Patent Publication No. 2011/0092072 discloses a heating plate for a substrate support assembly in a semiconductor plasma processing apparatus comprising multiple independently controllable planar heater zones arranged in a scalable multiplexing layout, and electronics to independently control and power the planar heater zones.

Thus, there is a need for a component of a substrate support assembly, such as a substrate support assembly comprising an ESC or edge ring, which is capable of making spatial corrections and/or adjustments to the azimuthal plasma processing rate non-uniformity to correct for film thickness variation, etch chamber induced etch rate non-uniformity and large magnetic field (from plasma generation) induced non-uniformity.

While certain aspects of conventional technologies have been discussed to facilitate disclosure of the invention, Applicant in no way disclaims these technical aspects, and it is contemplated that the claimed invention may encompass or include one or more of the conventional technical aspects discussed herein.

SUMMARY

Disclosed herein is a component of a substrate support assembly comprising an edge ring or substrate support incorporating a plurality of current loops which generate small magnetic fields in a plasma during plasma processing of at least one semiconductor substrate. The component creates a localized magnetic field without the need for a permanent magnet or iron core. The magnetic fields are small enough to avoid damage to circuits undergoing processing on the semiconductor substrate but strong enough to affect the plasma so as to increase or decrease localized plasma processing such as etch rates during plasma etching. The spatial adjustments to the localized plasma processing rates can compensate for film thickness variation, chamber non-uniformity and/or magnetic field induced non-uniformity.

During plasma processing such as etching, the current loops can be powered to manipulate the plasma and effect spatial adjustments to an azimuthal plasma to correct for film thickness variation, chamber non-uniformity and/or magnetic field induced non-uniformity.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows a cross-sectional view of a substrate support assembly comprising an ESC.

FIG. 2 shows a top view (FIG. 2A) of a component of a substrate support assembly in accordance with an embodiment and a cross-sectional view (FIG. 2B) of the associated perpendicular applied magnetic field. FIG. 2C shows a controller, DC power source(s), and current loop(s).

FIG. 3 shows a perspective view of a component of a substrate support assembly in accordance with an embodiment.

FIG. 4 shows a top view of a component of a substrate support assembly in accordance with another embodiment.

FIG. 5 shows a top view of a component of a substrate support assembly in accordance with yet another embodiment.

FIG. 6 shows a top view of a component of a substrate support assembly in accordance with a further embodiment.

FIG. 7 shows a top view of a component in accordance with an embodiment that surrounds a substrate support.

FIG. 8 shows a perspective view of a component in accordance with an embodiment that surrounds a substrate support.

FIG. 9 shows a top view of a component in accordance with another embodiment that surrounds a substrate support.

FIG. 10 shows a top view of a component of a substrate support in accordance with an embodiment and a component surrounding the substrate support in accordance with an embodiment.

FIG. 11 shows a top view of a component of a substrate support in accordance with another embodiment and a component surrounding the substrate support in accordance with another embodiment.

FIG. 12 shows a top view of a component of a substrate support in accordance with yet another embodiment and a component surrounding the substrate support in accordance with yet another embodiment.

FIG. 13 shows a top view of an etch rate pattern after partial etching of a substrate.

FIG. 14 shows a top view of an etch rate pattern after final etching of a substrate.

DETAILED DESCRIPTION

Precise azimuthal CD control on a substrate by small (e.g., <5° C.) corrections azimuthally to the substrate temperature can address CD uniformity which is sensitive to substrate temperature (e.g., as high as 1 nm/° C.). For example, even with an azimuthally symmetric etch chamber design, film thickness non-uniformity can result in azimuthal etch rate non-uniformity, as regions of substrate with thinner films undergo film clearing faster than other regions on the substrate. Small variabilities in hardware also contribute to azimuthal etch rate non-uniformity (e.g., <1%). Large applied DC magnetic fields (e.g., >20 Gauss), such as those used for plasma generation, can be a source of etch rate non-uniformity in plasma etching. Such a magnetic field induces a force, F, defined by F=ExB (where E is the electric field in the plasma and B is the magnetic field) on electrons in the plasma which results in azimuthal non-uniformity in the plasma during plasma etching, such non-uniformity in the plasma can lead to non-uniformity in the etch rate.

FIG. 1 shows a cross-sectional perspective of a substrate 70 and substrate support assembly 100 comprising a tunable ESC. The tunable ESC comprises a baseplate 10 with coolant fluid channels 20 disposed therethrough. A thermal insulating layer 30 is disposed on baseplate 10. A heating plate 40 is disposed on insulating layer 30 and comprises an array of discrete heating zones 50 distributed laterally across the substrate support and is operable to tune a spatial temperature profile for CD control. A ceramic plate 60 is disposed on heating plate 40. A substrate 70 is disposed over the ceramic plate 60 and is electrostatically clamped to the ESC by an electrostatic chucking electrode 61 embedded in the ceramic plate. It is noted that a substrate support 100 may comprise a standard, or non-tunable, ESC, instead of a tunable ESC. The substrate support assembly is adapted to support substrates of at least about 200 mm in diameter, or at least about 300 mm in diameter or at least about 450 mm in diameter. The materials of the components are not particularly limited. Baseplate 10 is preferably made from a suitable thermal conductor, such as aluminum or stainless steel. Ceramic plate 60 is preferably made from a suitable ceramic material, such as aluminum oxide (Al2O3) or aluminum nitride (AlN). Thermal insulating layer 30 preferably comprises a silicone material, which adheres baseplate 10 to heating plate 40. An epoxy, silicone or metallurgical bond is preferably used to adhere heating plate 40 to ceramic plate 60.

Under operational conditions (e.g., plasma etching), DC magnetic fields used for plasma generation are a known source of etch rate non-uniformity. For example, a magnetic field parallel to the plane of substrate undergoing processing in the plasma volume is expected to induce non-uniformity in the azimuthal etch rate pattern with about 5% etch rate non-uniformity induced per Gauss of applied magnetic field. Thin film thickness variation and etch chamber hardware variation are also known to contribute to azimuthal etch rate non-uniformity.

The induced non-uniformity can be used to make adjustments to the azimuthal etch rate pattern using applied DC magnetic fields. These applied magnetic fields are relatively small (e.g., <20 Gauss or <10 Gauss, preferably ≤1 Gauss or ≤½ Gauss) and allow for localized corrections to the plasma processing such as etch rate to be made without significantly affecting other etch parameters (e.g. CD uniformity, substrate temperature). For example, the relatively small applied magnetic field also minimizes potential damage to circuits on a substrate being etched. Thus, when an azimuthal etch rate non-uniformity is detected in an etching process, such as those induced by film thickness variation, etch chamber hardware and the magnetic field of the plasma, a localized magnetic field above a substrate and generated from the substrate support can be used to make adjustments to an azimuthal etch rate pattern. Similar results can be obtained in other plasma processing such as plasma assisted deposition.

To apply such a localized magnetic field, at least one current carrying conductor (current loop) may be powered. FIG. 2 illustrates a current carrying conductor 150 embedded in a component of a substrate support assembly 100 (FIG. 2A). When DC current flows through the current carrying conductor 150, a magnetic field is generated predominantly in a direction perpendicular (FIG. 2B) to substrate support assembly 100 and substrate 70. Under operational conditions (e.g., plasma etching), the conductor 150 is operated independently of the other components of substrate support assembly 100, such as RF to the baseplate 10 and power to the heating plate 40 and voltage to the ESC. The conductor 150 is adapted to generate a DC magnetic field when DC power is supplied thereto by electrical leads running through the body of the component.

In order to generate small magnetic fields, a plurality of conductors 150 are laterally spaced across the substrate support and/or edge ring at locations suitable to generate applied magnetic fields effective to make corrections and/or adjustments to plasma processing such as an etch rate pattern. The conductors 150 may be located in a component such as an ESC ceramic, such as ceramic plate 60. The conductors 150 may be located in another component, such as baseplate 10. The conductors 150 may also be located in hardware adjacent the substrate support, such as an edge ring. Preferably, the current carrying conductors 150 are placed inside baseplate 10, such that any heat generated due to electrical current flow inside the conductors does not substantially alter the substrate temperature. If incorporated in baseplate 10, the conductors 150 are preferably wires with an electrically insulating sheath.

The current carrying conductor 150 may preferably comprise a wire, cable or conductive trace that is electrically isolated from its surroundings to ensure that the applied DC current only flows inside the conductor and not within the substrate support component in which it is embedded. Electrical isolation may be realized by providing a thin electrically insulating layer, or layers, surrounding current carrying conductor 150. For example, if current carrying conductor 150 is disposed in a component that is electrically conductive, a thin layer, or layers, of electrically insulating material or sheath is disposed around the conductor for electrical isolation. The electrically insulating material may comprise a Kapton film, an epoxy film, a silicone film and combinations thereof. If current carrying conductor 150 is disposed in a component that is electrically non-conductive, a thin layer, or layers, of electrically insulating material or sheath is not required for electrical isolation. The material of conductor 150 preferably comprises copper, but may be comprised of other materials with a suitable electrical conductivity.

The conductor 150 may be disposed within a component of a substrate support such that it forms a current loop 150. The current loop 150 may be formed into any desirable shape within the component and with reference to the plane of the upper surface of the substrate 70 and is preferably circular or semi-circular. Other shapes may be oval, semi-oval, square, rectangular, trapezoidal, triangular or other polygonal shape. If a wire is chosen for conductor 150 to be incorporated in ceramic plate 60, a wire may be placed at a desired location in a mold containing powder starting materials of the component. The molded component is then fired to form the component. If a conductive trace is chosen for conductor 150, a powder starting material of the trace may be formed into a pattern in a powder molding, with subsequent firing of the molding to form the component. If a conductive trace is chosen for conductor 150 and is to be placed on an outer surface of a component, a metal or other material may be plated on the component, with subsequent etching of the metal or other material to form the current loop on the component. If an individual wire is chosen as the conductor 150 and is to be formed on an upper surface of a component, a groove may be machined into the surface with dimensions suitable for receiving the wire and the insulated wire can be mounted in the groove with a suitable adhesive.

The current loop 150 can be supplied DC power by electrical leads connected thereto. FIG. 3 shows a perspective view of a substrate support assembly 100 comprising current loop 150 with leads 130 for power supply (up arrow) and power return (down arrow). The current loop 150 is disposed in or on baseplate 10. The leads are spaced a few mm apart such that the magnetic fields generated on the leads, and particularly those proximate the current loop 150, cancel each other out and do not interfere in the magnetic field over the substrate 70 being etched (FIG. 2A).

A current loop, or loops, may comprise a single turn. However, a current loop, or loops, comprising a plurality of turns to form a coil, or coil-like, structure are also contemplated. The coil, or coil-like, structure may reduce the DC current required for generating the applied magnetic field during an etching process. The embodiments of the current loop, or loops, are preferably disposed in planes parallel to the substrate. However, the current loop, or loops, may be disposed in planes that are not parallel to the substrate if such a disposition is desired.

The dimensions of current carrying conductor 150 are not particularly limited so long as the dimensions render its applied magnetic field effective to make corrections and/or adjustments to the plasma to achieve uniform processing such as an azimuthal etch rate pattern. The length of current carrying conductor 150 may be chosen such that the corresponding current loop 150 may be shaped into a desired form. For example, if a 300 mm diameter wafer is to be etched, each localized magnetic field can be generated by a single circular shaped current loop formed with a loop diameter between about 1-150 mm and preferably between about 1-75 mm. Depending on the shape of the current loop and the desired number of currently loops in the substrate support, the length of an individual current loop may be 5-1000 mm, e.g., 5-50 mm or 50-1000 mm, such as in the case of a component comprising up to two hundred current loops. The diameter of current carrying conductor 150 itself is also not particularly limited and may be any diameter or dimension that forms a suitable applied localized magnetic field. For example, if a 300 mm diameter wafer is to be etched, the current loop may be a wire with a diameter of between about 0.5 mm-10 mm and preferably between about 0.5 mm-5 mm. If a conductive trace is to be the current loop 150, the trace may be formed in a rectangular shape with a thickness of between about 0.5 mm-10 mm, preferably between about 0.5 mm-5 mm, and a width of between about 0.5 mm-10 mm, preferably between about 0.5 mm-5 mm. The direction of current flowing in the current loop is not particularly limited and may be either clockwise or counter-clockwise. Preferably, the current flowing in current loop 150 is adapted to be reversible to switch the direction of the current flow, and thus, switching the direction of the applied DC magnetic field, if desired.

For purposes of explanation, FIG. 2 shows an embodiment of a component of a substrate support assembly 100 comprising a single current loop 150. However, to provide localized magnetic fields it is desirable to have a plurality of current loops 150 in the substrate support. A plurality of current loops 150 allows for reduction of DC current required for a localized magnetic field strength over a substrate. An advantage of a plurality of current loops 150 is that each loop can be operated independently of one another such that each current loop may be supplied varying power levels and processing non-uniformity can be corrected and/or adjusted more efficiently. If each of the current loops 150 in the plurality of current loops is independently operable, further fine tuning capabilities are imparted to the applied magnetic field over the substrate. Preferably, as shown in FIG. 2C, the plurality of current loops 150 are connected to one or more DC power sources 152 controlled by a controller 154 such that the loops can be supplied power at the same or different times with the same or different power levels. Preferably, the DC power source, or sources, comprise a multiplexed powering scheme and can supply power to each current loop 150 such that each loop can be individually tuned by time-domain multiplexing. Preferably, the periphery of each current loop 150 in a plurality of current loops is laterally offset from the periphery of an adjacent current loop such that no overlap occurs. Preferably, the plurality of current loops 150 are disposed in a laterally symmetric or equidistant manner such that a plane that vertically intersects the center of the component where the loops are disposed produces substantial mirror images of each half of the component. The current loops 150 in the component are preferably arranged in a defined pattern, for example, a rectangular grid, a hexagonal grid, a polar array or any desired pattern.

FIG. 4 shows a preferred embodiment of a component of a substrate support assembly 100 wherein substrate support 100 comprises a plurality of current loops 150. FIG. 4 shows a preferred embodiment having two separate current loops 150 which are D-shaped and having their straight legs facing each other. The current loops 150 may be of the same size or may be of different sizes. Preferably, each of the current loops 150 extends less than about halfway around the support or edge ring. The current loops 150 are shown as being disposed towards a peripheral area of the substrate support component, but may also be disposed at any radial position desired. When the currents of these two loops are applied in the same direction (e.g., both clockwise or both counter-clockwise), a magnetic field similar to that shown in FIG. 2A is generated. When the currents of the two loops are applied in opposite directions (e.g., one clockwise and one counter-clockwise), certain portions of the applied magnetic field are cancelled over the center of the substrate.

FIG. 5 shows a preferred embodiment of a component of a substrate support assembly 100 wherein a substrate support 100 comprises multiple current loops 150. FIG. 5 shows a preferred embodiment with four separate current loops 150 which are each D-shaped and having their straight legs facing inward. Similar to those shown in FIG. 4, the current loops 150 are shown as being disposed towards a peripheral area of the substrate support component, but may also be disposed at any radial position desired. The four current loops 150 are capable of generating applied magnetic fields in various directions over the substrate depending on the direction of the current in each of the four loops 150, similar to the applied magnetic field generated by the two separate loops in FIG. 4.

FIG. 6 shows an embodiment of a component of a substrate support assembly 100 having circular current loops wherein controlling the direction of current in various current loops 150, more complex magnetic field patterns can be generated over the substrate. The embodiment of FIG. 6 comprises nine separate current loops 150, with eight outer current loops surrounding a center current loop. If desired, the total number of current loops 150 may be significantly more than nine, and can be as high as about two hundred. The more current loops 150, the more fine tuning capability imparted to the applied magnetic field over the substrate.

FIG. 7 shows an embodiment of a substrate support assembly 100 wherein a component adapted to surround a substrate support 100 comprises at least one current loop 150, and wherein substrate support 100 does not comprise a current loop. The generation of the magnetic field from the component compensates for non-uniformity at the outermost edge of substrate 70. FIG. 7 shows an embodiment wherein an edge ring 110 comprises two current loops 150 disposed in a plane substantially parallel to an upper surface of substrate 70. The current loops 150 are formed into a block semi-circular shape that substantially surround substrate support 100 and are disposed on opposite sides of edge ring 110. The loops are independently operated with respect to each other such that two magnetic fields can be generated. The major legs of the current loops can be on the same or different planes. FIG. 8 shows a perspective view of current loop 150 disposed in edge ring 110. The loop includes major legs which are vertically offset with electrical leads 130 for power supply (up arrow) and power return (down arrow). The leads are spaced a few mm apart such that the magnetic fields generated on the leads, and particularly those proximate the current loop 150, cancel each other out and do not interfere in the magnetic field over the substrate 70 being etched (FIG. 2A). If desired, edge ring 110 may comprise more than two current loops 150. FIG. 9 shows an embodiment wherein edge ring 110 comprises four current loops 150 and wherein substrate support 100 does not comprise any current loops. Each of the four current loops 150 are arranged diametrically opposite to another one of the loops 150.

FIG. 10 shows an embodiment of a component of a substrate support assembly 100 wherein both substrate support 100 and a component 110 surrounding the substrate support comprise at least one current loop 150. Adding at least one current loop 150 to such hardware, such as edge ring 110 surrounding the substrate support 100, extends the influence of the applied magnetic field over the substrate to the outermost edge of substrate 70. In the embodiment of FIG. 10, the substrate support 100 and edge ring 110 each comprise two current loops 150. The current loops incorporated in the substrate support are D-shaped with the straight legs facing each other. The current loops incorporated in the edge ring are offset 90° with respect to the current loops of the substrate support. The current loops 150 in the substrate support 100 and edge ring 110 may or may not be planar with respect to each other or with respect to a substrate surface. The current loops 150 in the edge ring 110 preferably extend around a substantial portion of its circumference.

The number of current loops 150 that the substrate support assembly 100 comprise may be greater than two, such as that shown in FIG. 11, wherein both substrate support 100 and edge ring 110 each comprise four current loops 150. FIG. 12 shows an embodiment of a substrate support assembly 100 wherein the support comprises nine current loops 150 and edge ring 110 comprises twelve current loops 150. The current loops 150 comprised in the substrate support or edge ring are laterally distributed in a symmetric manner.

The current loops can be incorporated in any type of substrate support which may or may not include an electrostatic clamping arrangement, heating arrangement and/or temperature controlled baseplate. In a preferred method of controlling and/or adjusting an etch rate pattern using a substrate support incorporating current loops, a substrate is supported on a substrate support comprising a baseplate, a thermal insulating layer disposed over the baseplate, a heating plate disposed over the thermal insulating layer, a ceramic plate disposed over the a thermal insulating layer; and current loops; etching a substrate disposed on the substrate support; detecting an etch rate non-uniformity, such as an azimuthal etch rate non-uniformity, after etching has been initiated; and providing one or more of the current loops with DC power to generate localized DC magnetic fields that correct and/or adjust the etch rate non-uniformity.

An azimuthal etch rate non-uniformity may be detected as follows. A substrate comprising a thin film, such as a polysilicon thin film in the case of semiconductor substrate, to be processed is inspected to determine the thickness of the thin film at various locations across the substrate using standard interferometry techniques. The substrate is then plasma etched, or partially etched. After etching, or partial etching, the thickness of the thin film is measured again using standard interferometry techniques. The difference between the two thin film thickness measurements is determined by an appropriate algorithm, which also is able to generate an etch pattern on the substrate surface. From an etch rate pattern, a mean depth of the film thickness left on the substrate is determined, along with other parameters, such as the standard deviation and global maximum and minimum depths. These parameters are used to determine where selective application of a magnetic field can be applied to correct and/or adjust an azimuthal etch rate non-uniformity during subsequent etching of a batch of wafers undergoing the same etch process.

Alternatively, incoming wafer thickness of a substrate can be measured, the B-field pattern to provide uniform etching can be determined, and etching of a batch of substrates can be carried out. In another method, a substrate can be etched, an azimuthal pattern for etching can be determined, the magnetic field compensation is determined and further substrates are etched while applying the magnetic field compensation. The etch rate or other parameters could be monitored during plasma etching and the current loops could be powered to compensate for local etch rate variation during the plasma etch process.

Example 1

A silicon wafer with a 1 μm thick silicon oxide film on its surface to be etched to a depth of about 400 nm is surrounded by an edge ring with two current loops, similar to the configuration of FIG. 7, wherein the supply trace and return trace are non-planar. Etching can be carried out using a fluorocarbon etching gas. The substrate is loaded into a plasma etch vacuum chamber and is partially etched to a depth of about 200 nm and then removed from the chamber. Interferometric techniques are used to determine the etch rate non-uniformity by measuring the film thickness profile over the substrate before and after partial etching. From these measurements, an algorithm is used to generate the etch rate pattern. After analysis of the pattern, parameters used to determine corrections and/or adjustments to be carried out to the azimuthal etch rate non-uniformity are determined. The partial etch is determined to result in average depth in the film of 192.4 nm, with a three-sigma standard deviation of 19.2 nm (10%). The difference between a global maximum and minimum is 31.9 nm (16.6%). Analysis of the etch rate pattern is shown in FIG. 13. Areas 190 (in black) on substrate 70 are shown to be etched with a faster etch rate than areas 180 (in gray).

Etching the remaining portions of the film on substrate 70 is then carried out. During the subsequent etching, DC power is supplied to the current loops 150 disposed in edge ring 110. DC power is supplied such that an 3 Gauss magnetic field is generated by the loops 150. After completion of etching, the etch rate pattern is determined, as described above. This etch results in an average of 189.5 nm of film thickness removed, with a three-sigma standard deviation of 13.9 nm (7.3%). The difference between a global maximum and minimum is 25.2 nm (13.3%). Analysis of the etch rate pattern is shown in FIG. 14. Areas 190 (in gray) on substrate 70 are shown to be etched with a slower etch rate than areas 180 (in black).

Thus, etching a substrate in the presence of an applied DC magnetic field can compensate for etch rate non-uniformity and thus provide a more uniform etch rate. With an applied magnetic field of about 3 Gauss generated from current loops in an edge ring, azimuthal etch rate non-uniformity can be decreased by about 3.3.% (range after partial etch−range after final etch), with a decrease in the three-sigma standard deviation of about 2.7% (deviation after partial etch−deviation after final etch). Furthermore, application of an 3 Gauss magnetic field shows that areas etched at a faster etch rate in the partial etch can be etched at a slower etch rate in the final etch step, thus, correcting for an azimuthal etch rate non-uniformity. Similarly, application of an 3 Gauss magnetic field shows that the areas that are etched at a slower etch rate in the partial etch can be etched at a faster etch rate in the final etch step, thus, correcting for an azimuthal etch rate non-uniformity.

Example 2

In a process scheme to compensate for etch rate variation: a) a wafer is partially etched and the etch rate non-uniformity is measured; b) apply a magnetic field pattern to the plasma above a wafer (based on historical knowledge); c) etch another wafer, determine etch pattern sensitivity to the applied magnetic field pattern since the applied field is known; and d) optionally repeat steps a-c to determine an optimal magnetic field pattern.

Example 3

In a process scheme to compensate for incoming wafer thickness variation: a) measure incoming wafer thickness variation; b) apply a magnetic field pattern (based on historical knowledge); c) etch a wafer, determine etch pattern sensitivity to the applied magnetic field pattern since the applied field is known; and d) optionally repeat steps a-c and adjust the applied magnetic field pattern if necessary.

All of the above-mentioned references are herein incorporated by reference in their entirety to the same extent as if each individual reference was specifically and individually indicated to be incorporated herein by reference in its entirety.

While the invention has been described with reference to preferred embodiments, it is to be understood that variations and modifications may be resorted to as will be apparent to those skilled in the art. Such variations and modifications are to be considered within the purview and scope of the invention as defined by the claims appended hereto.

Claims

1. A system comprising: an electrostatic chuck including an embedded electrode receiving a first voltage to electrostatically attract a semiconductor substrate to the electrostatic chuck; anda plurality of current loops disposed in at least one of the electrostatic chuck and an edge ring surrounding the electrostatic chuck, wherein the plurality of current loops are laterally spaced apart, and wherein each of the plurality of current loops is a wire formed into a loop;one or more DC power sources electrically connected to the plurality of current loops; anda controller configured to: supply the first voltage to the embedded electrode;supply a DC current to the plurality of current loops from the one or more DC power sources; andcontrol the one or more DC power sources such that each of the plurality of current loops is independently operable and generates a localized DC magnetic field proximate to the semiconductor substrate on receiving the DC current during plasma processing of the semiconductor substrate to adjust the plasma processing of the semiconductor substrate,wherein the localized DC magnetic field generated by the plurality of current loops does not generate plasma.

2. The system of claim 1 wherein the localized DC magnetic field generated by the plurality of current loops adjusts an etch rate during the plasma processing of the semiconductor substrate.

3. The system of claim 1 wherein the controller is configured to supply the DC current to one or more of the plurality of current loops in response to detecting an etch rate non-uniformity during the plasma processing of the semiconductor substrate.

4. The system of claim 1 wherein the controller is configured to supply the DC current to one or more of the plurality of current loops initially in a first direction and subsequently in a second direction that is opposite of the first direction.

5. The system of claim 1 wherein the controller is configured to supply the DC current to the plurality of current loops in the same direction.

6. The system of claim 1 wherein the controller is configured to supply the DC current to the plurality of current loops in different directions.

7. The system of claim 1 wherein the controller is configured to supply the DC current to the plurality of current loops at the same time.

8. The system of claim 1 wherein the controller is configured to supply the DC current to the plurality of current loops at different times.

9. The system of claim 1 wherein the controller is configured to supply the same amount of the DC current to the plurality of current loops.

10. The system of claim 1 wherein the controller is configured to supply different amounts of the DC current to the plurality of current loops.

11. The system of claim 1 wherein the controller is configured to supply the DC current to the plurality of current loops using a multiplexing scheme.

12. The system of claim 1 wherein the plurality of current loops are embedded in a baseplate of the electrostatic chuck.

13. The system of claim 1 wherein the plurality of current loops are embedded in a ceramic plate of the electrostatic chuck.

14. The system of claim 1 wherein the plurality of current loops are electrically isolated from the embedded electrode.

15. The system of claim 1 wherein the plurality of current loops are electrically insulated.

16. The system of claim 1 wherein the plurality of current loops lie in a plane parallel to the semiconductor substrate.

17. The system of claim 1 wherein the plurality of current loops in the electrostatic chuck and in the edge ring are not planar with respect to each other.

18. The system of claim 1 wherein the plurality of current loops in the electrostatic chuck and in the edge ring are not planar with respect to the semiconductor substrate.

19. The system of claim 1 wherein the plurality of current loops extend less than halfway around the electrostatic chuck or the edge ring.

20. The system of claim 1 wherein a periphery of each current loop of the plurality of current loops is laterally offset from a periphery of an adjacent current loop of the plurality of current loops.

21. The system of claim 1 wherein the plurality of current loops have the same size and shape.

22. The system of claim 1 wherein the plurality of current loops have different sizes and shapes.

23. The system of claim 1 wherein at least one of the plurality of current loops has a circular, semi-circular, oval, semi-oval, square, rectangular, trapezoidal, triangular, or polygonal shape.

24. The system of claim 1 wherein at least one of the plurality of current loops comprises a single turn.

25. The system of claim 1 wherein at least one of the plurality of current loops comprises a plurality of turns.