TECHNIQUE FOR FORMING AN ISOLATION TRENCH AS A STRESS SOURCE FOR STRAIN ENGINEERING

Abstract

By forming a non-oxidizable liner in an isolation trench and selectively modifying the liner within the isolation trench, the stress characteristics of the isolation trench may be adjusted. In one embodiment, a high compressive stress may be obtained by treating the liner with an ion bombardment and subsequently exposing the device to an oxidizing ambient at elevated temperatures, thereby incorporating silicon dioxide into the non-oxidizable material. Hence, an increased compressive stress may be generated within the non-oxidizable layer.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

The invention may be understood by reference to the following description taken in conjunction with the accompanying drawings, in which like reference numerals identify like elements, and in which:

FIGS. 1 a-1f schematically show cross-sectional views of a semiconductor device during the formation of an isolation trench having a compressive stress in accordance with illustrative embodiments of the present invention;

FIG. 2 schematically illustrates a cross-sectional view of a semiconductor device during the formation of an isolation trench by means of a liner material having an intrinsic stress; and

FIGS. 3 a-3d schematically illustrate cross-sectional views of a semiconductor device having differently stressed isolation trenches during various manufacturing stages in accordance with yet other illustrative embodiments of the present invention.

Claims

1. A method, comprising: forming a non-oxidizable layer within an isolation trench formed in a semiconductor layer located above a substrate;selectively modifying said non-oxidizable layer within said isolation trench to generate compressive stress;filling said isolation trench with an insulating material; andforming a transistor element adjacent to said isolation trench, said compressive stress inducing a lattice strain in said transistor element.

2. The method of claim 1, wherein said non-oxidizable layer comprises silicon and nitride.

3. The method of claim 2, wherein selectively modifying said non-oxidizable layer comprises forming a mask layer to expose said non-oxidizable layer within said isolation trench and treating an exposed portion of said non-oxidizable layer by an ion bombardment.

4. The method of claim 3, wherein selectively modifying said non-oxidizable layer further comprises exposing said portion to an oxidizing ambient.

5. The method of claim 4, wherein selectively modifying said non-oxidizable layer further comprises exposing said portion to an oxidizing plasma ambient.

6. The method of claim 3, wherein said ion bombardment is generated by an ion implantation process.

7. A method, comprising: depositing a non-oxidizable layer having an intrinsic stress above a first isolation trench and a second isolation trench, said first and second isolation trenches being formed in a semiconductor layer;selectively modifying said intrinsic stress in said first isolation trench; andfilling said first and second isolation trenches with an insulating material.

8. The method of claim 7, wherein modifying said intrinsic stress comprises treating said non-oxidizable layer in said first isolation trench by an ion bombardment.

9. The method of claim 8, further comprising exposing said modified non-oxidizable layer to an oxidizing ambient.

10. The method of claim 9, wherein selectively modifying said non-oxidizable layer further comprises exposing said portion to an oxidizing plasma ambient.

11. The method of claim 8, wherein said ion bombardment is generated by an ion implantation process.

12. The method of claim 7, wherein said non-oxidizable layer comprises silicon and nitride.

13. The method of claim 7, wherein said non-oxidizable layer is deposited with an intrinsic tensile stress.

14. The method of claim 13, wherein modifying said intrinsic stress in said first isolation trench comprises creating a compressive stress.

15. The method of claim 14, further comprising forming a first transistor in a first semiconductor region bordered by said first isolation trench and forming a second transistor in a second semiconductor region bordered by said second isolation trench.

16. The method of claim 15, wherein said first transistor is a P-channel transistor and said second transistor is an N-channel transistor.

17. A semiconductor device, comprising: a first isolation trench formed in a semiconductor layer and having sidewalls and a bottom;a insulating liner material formed on said sidewalls and said bottom, said insulating liner material comprising silicon, nitrogen and oxygen and having a compressive intrinsic stress; andan insulating oxide material formed adjacent to said insulating liner material.

18. The semiconductor device of claim 17, wherein said insulating oxide material comprises silicon dioxide.

19. The semiconductor device of claim 17, further comprising a buried insulating layer formed below said semiconductor layer.

20. The semiconductor device of claim 17, further comprising a second isolation trench comprising an insulating non-oxidizable liner material having an intrinsic stress that differs from said intrinsic compressive stress of said first isolation trench.

21. The semiconductor device of claim 20, wherein said second isolation trench comprises an intrinsic tensile stress.

22. The semiconductor device of claim 17, further comprising a first transistor element formed in a first semiconductor region bordered by said first isolation trench, said first transistor element being a P-channel transistor.

23. The semiconductor device of claim 21, further comprising a second transistor element formed in a second semiconductor region bordered by said second first isolation trench, said second transistor element being an N-channel transistor.