This invention relates to electronic integrated circuits, and more particularly to electronic integrated circuits having transistors fabricated with semiconductor-on-insulator technology.
Virtually all modern electronic products—including laptop computers, mobile telephones, and electric cars—utilize complementary metal oxide semiconductor (CMOS) transistor integrated circuits (ICs), and in many cases CMOS ICs fabricated using a semiconductor-on-insulator process, such as silicon-on-insulator (SOI) or germanium-on-insulator. SOI transistors in which the electrical insulator is aluminum oxide (i.e., sapphire) are called silicon-on-sapphire or “SOS” devices. Another example of a semiconductor-on-insulator technology is “silicon-on-glass”, and other examples are known to those of ordinary skill in the art.
Taking SOI as one example of semiconductor-on-insulator, SOI technology encompasses the use of a layered silicon-insulator-silicon substrate in place of conventional “bulk” silicon substrates in semiconductor manufacturing. More specifically, SOI transistors are generally fabricated on a layer of silicon dioxide, SiO2 (often called a “buried oxide” or “BOX” layer) formed on a bulk silicon substrate. The BOX layer reduces certain parasitic effects typical of bulk silicon CMOS processes, thereby improving performance. SOI-based devices thus differ from conventional bulk silicon devices in that the silicon regions of the CMOS transistors are fabricated on an electrical insulator (typically silicon dioxide or aluminum oxide) rather than on a bulk silicon substrate.
As a specific example of a semiconductor on insulator process for fabricating ICs,
If the source S and drain D are highly doped with N type material, the FET is an N-type FET, or NMOS device. Conversely, if the source S and drain D are highly doped with P type material, the FET is a P-type FET, or PMOS device. Thus, the source S and drain D doping type determines whether a FET is an N-type or a P-type. CMOS devices comprise N-type and P-type FETs co-fabricated on a single IC die, in known fashion. The gate G is typically formed from polysilicon.
A superstructure 112 of various elements, regions, and structures may be fabricated in known fashion above the FET 108 in order to implement particularly functionality. The superstructure 112 may include, for example, conductive interconnections from the illustrated FET 108 to other components (including other FETs) and/or external contacts, passivation layers and regions, and protective coatings. The conductive interconnections may be, for example, copper or other suitable metal or electrically conductive material.
For example,
Other elements, regions, and structures may be included for particular circuit designs. For example, referring to
As should be appreciated by one of ordinary skill in the art, a single IC die may embody from one electronic component—such as FET 108—to millions of electronic components. Further, the various elements of the superstructure 112 may extend in three-dimensions and have quite complex shapes. In general, the details of the superstructure 112 will vary from IC design to IC design.
The BOX layer 104, while enabling many beneficial characteristics for SOI IC's, also introduces some problems, such as capacitive coupling to the substrate 102, a thermal barrier to heat flow, and a voltage breakdown path to the substrate 102. Capacitive coupling with the substrate 102 alone can cause numerous side effects compared to an ideal SOI transistor, such as increased leakage current, lower breakdown voltage, signal cross-coupling, and linearity degradation. However, the most serious capacitive coupling effect caused by the BOX layer 104 is often the “back-channel” effect.
Referring back to
It is possible to mitigate some of the side effects of the secondary parasitic back-channel FET 120. One known mitigating technique utilizes “single layer transfer”, or SLT, as part of the IC fabrication process. The SLT process essentially flips an entire SOI transistor structure upside down onto a “handle wafer”, with the original substrate (e.g., substrate 102 in
In the structure of
Although not exactly to scale, the BOX layer 104 in
While the IC structure of
The problems caused by the secondary parasitic back-channel FET of conventional FET IC structures are mitigated or eliminated by the structures and methods taught in co-pending and commonly owned U.S. patent application Ser. No. 15/920,321, referenced above. Embodiments of that invention enable full control of the secondary parasitic back-channel FET of semiconductor-on-insulator IC primary FETs by fabricating such ICs using a process which allows access to the backside of the FET, such as an SLT process (collectively, a “back-side access process”). Thereafter, a conductive aligned supplemental (CAS) gate structure is fabricated relative to the BOX layer and juxtaposed to a primary FET such that a control voltage applied to the CAS gate can regulate the electrical characteristics of the regions of the primary FET adjacent the BOX layer. Such a FET may also be referred to as a “CAS-gated FET”.
While the disclosure in U.S. patent application Ser. No. 15/920,321 mitigates or eliminates the problems caused by the secondary parasitic back-channel FET of conventional FET IC structures, in some cases, some embodiments exhibit poor thermal conductivity, which can cause reliability, performance, and other problems in an IC. The problem of poor thermal conductivity thus also applies generally to ICs made by a back-side access process, such as the SLT process.
Accordingly, there is a need for a FET IC structure made using a back-side access process that mitigates or eliminates thermal conductivity problems arising from such structures. The present invention addresses these needs and more.
The present invention encompasses an FET IC structure made using a back-side access process that mitigates or eliminates thermal conductivity problems arising from such structures.
In some embodiments of the invention, during fabrication of a FET made using a back-side access process, one or more electrically-isolated thermal paths are formed adjacent the FET and configured to conduct heat laterally away (e.g., “horizontally”) from the FET to generally orthogonal (e.g., “vertical”) thermal pathways (e.g., vias or other heat pipes), and thence to corresponding thermal pads externally accessible at the “top” of the completed integrated circuit (IC).
In some embodiments of the invention that utilize a thermally-conductive handle wafer, during fabrication of a FET made using a back-side access process, one or more electrically-isolated thermal paths are formed adjacent a FET and configured to conduct heat laterally away from the FET. Thermal vias or pathways are formed sufficiently through a separating passivation layer so as to be in thermal contact with the handle wafer and with the conventional metallization layers of the device superstructure, at least one of which is in thermal contact with the lateral thermal paths. Accordingly, heat is conducted from the FET through the lateral thermal paths, then through the metallization layers and thermal vias to the thermally-conductive handle wafer, and thus to the “bottom” or “backside” of the completed integrated circuit (IC), which may be placed in thermal contact with a heat sink.
In some embodiments, the lateral thermal paths may use dummy gates specially configured to conduct heat laterally away from a FET to generally orthogonal thermal pathways or interconnection metallization structures.
The details of one or more embodiments of the invention are set forth in the accompanying drawings and the description below. Other features, objects, and advantages of the invention will be apparent from the description and drawings, and from the claims.
Like reference numbers and designations in the various drawings indicate like elements.
The present invention encompasses an FET IC structure made using a back-side access process that mitigates or eliminates thermal conductivity problems arising from such structures. Embodiments of the invention are applicable to conductive aligned supplemental (CAS) FET IC structures made in accordance with the teachings of U.S. patent application Ser. No. 15/920,321).
To better understand the thermal conductivity problems of integrated circuits (ICs) made using a back-side access process (such as an SLT process, and including CAS-gated FET IC structures), it is useful to consider details of how such structures are formed. For convenience, the example below describes a CAS-gated silicon-on-insulator (SOI) FET made using a single layer transfer (SLT) process as one example of a FET made by a back-side access process. While SOI FETs are used in the example below, similar problems exist in other semiconductor-on-insulator technologies.
For the structure shown in
Due to the presence of the heat conduction inhibitors that result from the back-side access (e.g., SLT) and CAS-gate fabrication processes, removing heat from a CAS-gated FET 108 can be difficult, leading to degradations to reliability, performance, and other characteristics. This issue is highlighted in
The result is that heat generated by the FET 108 does not readily dissipate, which may cause a severe temperature rise when the FET 108 is operated in a high power mode, such as in a power amplifier (PA). Some embodiments of conventional SLT SOI FETs have shown temperature increases of 76%-135% when compared to conventional non-SLT SOI FETs.
With respect to the figures referenced in the examples below, note that the dimensions for the various elements are not to scale; some dimensions have been exaggerated vertically and/or horizontally for clarity or emphasis. In addition, references to orientations and directions (e.g., “top”, “bottom”, “above”, “below”, “lateral”, “orthogonal” etc.) are relative to the example drawings, and not necessarily absolute orientations or directions.
In some embodiments of the invention, during fabrication of a FET made using a back-side access process, one or more electrically-isolated, laterally-extending thermal paths are formed adjacent the FET and configured to conduct heat laterally away (e.g., “horizontally”) from the FET to generally orthogonal (e.g., “vertical”) thermal pathways (e.g., vias or heat pipes), and thence to corresponding thermal pads externally accessible at the “top” of the completed integrated circuit (IC). Such a “top side” thermal extraction configuration is particularly useful for ICs mounted in a “flip-chip” package.
For example,
During the formation of the first metallization connection layer (commonly called “metal 1” or “M1”) for the IC FET structure 420, electrical connections 426 are made to the various terminals of the FET device 402 (e.g., source, drain, gate). In addition, in the illustrated example, the M1 layer—which is also thermally conductive and patterned over a first interlevel dielectric layer (ILD)—is patterned to form one or more electrically-isolated, laterally-extending thermal paths 404 each comprising (1) a near portion 404a in thermal contact, through the ILD, with the edge portion 422a, 422b adjacent the FET device 402, and (2) a far portion 404b spaced away from the edge portions 422a, 422b adjacent FET device 402 in a lateral direction (e.g., “horizontally” in
To be clear, heat generated by the FET device 402 (especially at its drain D) will flow laterally through the active region of the FET device 402, thence through the electrically isolating structures 428, and finally through edge portions 422a, 422b. After this lateral heat diffusion, the transistor-generated heat will diffuse vertically through the ILD layer situated between the edge regions 422a, 422b and the M1 layer, and thence into the near and far portions 404a, 404b of the electrically-isolated, laterally-extending thermal paths 404, respectively, that are patterned from the M1 layer. Since the M1 layer is an excellent heat conductor, the near portions 404a will conduct heat to the far portions 404b of the electrically-isolated, laterally-extending thermal paths 404, and ultimately on to an external heat sink (such as the thermal pads 406 in
Thus, the purpose of the electrically-isolated, laterally-extending thermal paths 404 is to conduct heat away from the FET device 402 in a lateral direction when fabrication and SLT processing of the IC FET structure 420 is finished. Note that while
In
Each generally orthogonal thermal pathway 440 may be capped by a thermal pad 406 made of a thermally conductive material. If the thermal pathways 440 are made of copper, then the material for the thermal pads 406 would generally be aluminum, to avoid oxidation of the copper. The thermal pads 406 may be fashioned as part of the RDL process for forming a CAS gate for the FET device 402. Of course, other heat conducting materials compatible with IC fabrication processes may be used for both the generally orthogonal thermal pathways 440 and the thermal pads 406.
Of note, using STI trenches for the electrically isolating structures 428 is particularly beneficial, since STI trenches can be made very narrow (e.g., about 200 nm, or 2000 Angstroms) and they run the entire width of the active transistor region (i.e., silicon island 422). Accordingly, the thermal resistance from the FET device 402 to the electrically-isolated, laterally-extending thermal paths 404 through STI trenches is much less than the thermal resistance through to either the top or the bottom of the completed SOI IC structure 400 (see
While using the M1 metallization layer to form the electrically-isolated, laterally-extending thermal paths 404 is quite convenient from a fabrication point of view, it is also possible to use other metallization layers (including custom layers) or to combine metallization layers. For example, one or more generally orthogonal thermal pathways may be formed in thermal contact with the electrically-isolated edge portions 422a, 422b of the silicon island 422 so as to be thermally coupled to the edge portions 422a, 422b. Such orthogonal thermal pathways may then be thermally coupled to lateral thermal paths formed from a metallization layer or layers other than M1. Other thermal pathways 440 and corresponding thermal pads 406 may then be thermally coupled to the lateral thermal paths, similar to
It should be understood that “electrically isolated”, in the context of this disclosure, refers to substantially isolated from direct current flow. As a person of skill will understand, AC coupling through capacitor-like structures is inherent in conductor/insulator/conductor structures such as described above. Such AC coupling can be managed and mitigate by known design techniques.
In some embodiments of the invention that utilize a thermally-conductive handle wafer (e.g., silicon, metal, silicon carbide, diamond, etc.), during fabrication of a FET made using a back-side access process, one or more electrically-isolated thermal paths are formed adjacent a FET and configured to conduct heat laterally away from the FET. Thermal vias are formed sufficiently through (including all of the way through) the first passivation layer so as to be in thermal contact with the handle wafer and with the conventional metallization layers (such as M1-M5) of the device superstructure, at least one of which is in thermal contact with the lateral thermal paths. Accordingly, heat is conducted from the FET through the lateral thermal paths, then through the metallization layers and thermal vias to the thermally-conductive handle wafer, and thus to the “bottom” or “backside” of the completed integrated circuit (IC), which may be placed in thermal contact with a heat sink. Such a “bottom side” thermal extraction configuration may be used alone, but generally would be used in conjunction with the “top side” thermal extraction configuration described above to provide extra heat extraction from a FET device 402. A “bottom side” thermal extraction configuration is particularly useful for ICs mounted in a “wire bond” package.
The metallization layers can be patterned and interconnected, in known fashion, to provide lateral thermal pathways and vertical thermal pathways (e.g., “vertical” with respect to the plane of the FET device 402 in
Using the M5 metallization layer as an example of the layer nearest the handle wafer after SLT processing, conventionally, the M5 layer would be separated from the handle wafer by the first passivation layer, as shown in
Arrows 504 show the direction of heat flow, initially laterally away from the FET 402 along the laterally-extending thermal paths 404, and then “downwards” to the “bottom” of the IC structure 500. If desired, the FET 402 can be further processed to become a CAS-gated FET by adding the second passivation layer 206 and CAS gate “above” the BOX layer, as shown in
An advantage of the configuration shown in
The embodiments shown in
In general, the main barrier to heat flow within IC FETs is the many different layers of SiO2 or other insulating layers. As has been noted, the STI separation regions described above may be made quite narrow by lateral dimension standards, typically about 2000 Ångströms. However, one of the thinnest insulators in a FET, and therefore the lowest thermal resistance path (of the insulating layers in an IC FET) is through the gate oxide 612, with typical thicknesses of tens of Ångströms. Further, the gate material, typically polysilicon, is a relatively good thermal conductor. It was realized by the inventors that these characteristics could be adapted to provide lateral thermal paths to conduct heat away from a FET.
As an example,
In the example illustrated in
As in the configuration of
Heat from the FET to the heat release pads 704 thus flows through the entire area of the silicon island 602 that is covered by the dummy gates 610, passing through the extremely thin gate oxide material underneath the dummy gates 610. Compared to an embodiment that utilizes electrically-isolating STI trenches, the illustrated “trenchless” configuration reduces thermal resistance substantially (by as much as the ratio of the planar width of an STI trench to the thickness of a gate oxide), due to elimination of the series thermal resistance of the STI trench. An additional advantage of this embodiment is that the thermally conductive polysilicon dummy gates 610 are often thicker than the underlying silicon island 602, further reducing lateral thermal resistance.
While
In some embodiments, the connection of the thermally conductive structures 702 to the dummy gates 610 may be made at positions other than an end (i.e., along dashed line A-B through thermal vias to electrically isolated thermally conductive structures 702), and more than one thermally conductive structure 702 per “side” of the gate 608 may be used. One or more of the dummy gates 610 may be interconnected to one or more other dummy gates 610 by, for example, using polysilicon “straps” (such as strap 610a in
In a variation of the embodiment of
As should be appreciated from the above description, one aspect of the invention encompasses a thermal conduction structure for an integrated circuit transistor device made using a back-side access process and mounted on a handle wafer such that a gate of the transistor device is oriented towards the handle wafer, including: at least one laterally-extending thermal path (e.g., element 404 in
Finite element modeling of the configurations shown in
As the results in TABLE 1 indicate, a conventional SLT configuration exhibits significant temperature increases compared to a baseline non-SLT configuration, regardless of cooling scenario (additional modeling indicates that the problem is significantly exacerbated as device widths increase). However, use of a “top side” thermal extraction configuration in accordance with the present invention results in significant mitigation of FET temperature increases across all cooling scenarios. Lastly, use of a “top side” and “bottom side” thermal extraction configuration in accordance with the present invention results in a significant mitigation of FET temperature increases in the bottom cooling scenario, and actually reduces FET temperatures in the top cooling and combined top-and-bottom scenarios compared to a baseline non-SLT configuration.
Another aspect of the invention includes methods for making thermal conduction structures in accordance with the above teachings. For example,
Variants of the above method may include one or more of the following aspects: further including spacing at least one laterally-extending thermal path from the transistor device by an electrically isolating structure; further including spacing at least one laterally-extending thermal path from the transistor device by an electrically isolating structure formed by a shallow trench isolation process; further including fabricating at least one laterally-extending thermal path at least in part out of a metallization layer extending laterally from the transistor device; further including spacing the handle wafer from the transistor device by a passivation layer, and forming at least one thermal via through the passivation layer sufficiently so as to be thermally coupled to the handle wafer and to at least one generally orthogonal thermal pathway; further including fabricating at least one dummy gate electrically isolated from the transistor device by a gate oxide and in thermal contact with the transistor device, and fabricating at least one laterally-extending thermal path to be in thermal contact with at least one dummy gate; wherein the dummy gate comprises polysilicon; and/or further including fabricating at least one laterally-extending thermal path at least in part by fabricating at least one metallization layer overlaying at least one dummy gate and extending laterally from the transistor device.
While the particular IC examples shown in
In addition, the teachings of present invention may be used in conjunction with the circuit designs and methods taught in the co-pending U.S. patent applications entitled “High-Q Integrated Circuit Inductor Structure and Methods” and “SLT Integrated Circuit Capacitor Structure and Methods”, both referenced above.
The term “MOSFET”, as used in this disclosure, means any field effect transistor (FET) with an insulated gate and comprising a metal or metal-like, insulator, and semiconductor structure. The terms “metal” or “metal-like” include at least one electrically conductive material (such as aluminum, copper, or other metal, or highly doped polysilicon, graphene, or other electrical conductor), “insulator” includes at least one insulating material (such as silicon oxide or other dielectric material), and “semiconductor” includes at least one semiconductor material.
As should be readily apparent to one of ordinary skill in the art, various embodiments of the invention can be implemented to meet a wide variety of specifications. Unless otherwise noted above, selection of suitable component values is a matter of design choice and various embodiments of the invention may be implemented in any suitable integrated circuit (IC) technology (including but not limited to MOSFET structures), or in hybrid or discrete circuit forms. Integrated circuit embodiments may be fabricated using any suitable substrates and processes, including but not limited to standard bulk silicon, silicon-on-insulator (SOI), and silicon-on-sapphire (SOS). Unless otherwise noted above, the invention may be implemented in other transistor technologies such as bipolar, GaAs HBT, GaN HEMT, GaAs pHEMT, and MESFET technologies. However, the inventive concepts described above are particularly useful with an SOI-based fabrication process (including SOS), and with fabrication processes having similar characteristics. Fabrication in CMOS on SOI or SOS processes enables circuits with low power consumption, the ability to withstand high power signals during operation due to FET stacking, good linearity, and high frequency operation (i.e., radio frequencies up to and exceeding 50 GHz). Monolithic IC implementation is particularly useful since parasitic capacitances generally can be kept low (or at a minimum, kept uniform across all units, permitting them to be compensated) by careful design.
Voltage levels may be adjusted, and/or voltage and/or logic signal polarities reversed, depending on a particular specification and/or implementing technology (e.g., NMOS, PMOS, or CMOS, and enhancement mode or depletion mode transistor devices). Component voltage, current, and power handling capabilities may be adapted as needed, for example, by adjusting device sizes, serially “stacking” components (particularly FETs) to withstand greater voltages, and/or using multiple components in parallel to handle greater currents. Additional circuit components may be added to enhance the capabilities of the disclosed circuits and/or to provide additional functionality without significantly altering the functionality of the disclosed circuits.
A number of embodiments of the invention have been described. It is to be understood that various modifications may be made without departing from the spirit and scope of the invention. For example, some of the steps described above may be order independent, and thus can be performed in an order different from that described. Further, some of the steps described above may be optional. Various activities described with respect to the methods identified above can be executed in repetitive, serial, or parallel fashion.
It is to be understood that the foregoing description is intended to illustrate and not to limit the scope of the invention, which is defined by the scope of the following claims, and that other embodiments are within the scope of the claims. (Note that the parenthetical labels for claim elements are for ease of referring to such elements, and do not in themselves indicate a particular required ordering or enumeration of elements; further, such labels may be reused in dependent claims as references to additional elements without being regarded as starting a conflicting labeling sequence).
The present application is a continuation of U.S. patent application Ser. No. 17/123,881 filed Dec. 16, 2020, to issue on Sep. 6, 2022 as U.S. Pat. No. 11,437,404, which in turn is a a continuation of International Patent Application No. PCT/US2019/041898 filed on Jul. 15, 2019, which in turn is a continuation of U.S. Non-Provisional application Ser. No. 16/040,295, filed on Jul. 19, 2018 for “Thermal Extraction of Single Layer Transfer Integrated Circuits”, issued as U.S. Pat. No. 10,658,386 on May 19, 2020, the disclosures of which are incorporated herein by reference in their entirety. The present application may be related to the following patents and patent applications, the contents of all of which are incorporated herein by reference in their entirety: U.S. patent application Ser. No. 15/920,321, filed Mar. 13, 2018, entitled “Semiconductor-on-Insulator Transistor with Improved Breakdown Characteristics”;U.S. Pat. No. 9,837,412, issued Dec. 5, 2017, entitled “S-Contact for SOI”;U.S. Pat. No. 9,960,098, issued May 1, 2018, entitled “Systems and Methods for Thermal Conduction Using S-Contacts”;U.S. Pat. No. 10,276,371, issued Apr. 30, 2019, entitled “Managed Substrate Effects for Stabilized SOI FETs”;Co-pending U.S. patent application Ser. No. 16/040,411, filed Jul. 19, 2018, entitled “High-Q Integrated Circuit Inductor Structure and Methods”; andCo-pending U.S. patent application Ser. No. 16/040,390, filed Jul. 19, 2018, entitled “SLT Integrated Circuit Capacitor Structure and Methods”.
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Number | Date | Country | |
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20230072271 A1 | Mar 2023 | US |
Number | Date | Country | |
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Parent | 17123881 | Dec 2020 | US |
Child | 17901189 | US | |
Parent | PCT/US2019/041898 | Jul 2019 | WO |
Child | 17123881 | US | |
Parent | 16040295 | Jul 2018 | US |
Child | PCT/US2019/041898 | US |