Embodiments of the present invention relate to the field of integrated circuit manufacturing and test. More specifically, embodiments of the present invention relate to systems and methods for thermal control for device under test (DUT) testing.
It is common to subject integrated circuits, either packaged or unpackaged, to environmental testing as an operation in a development and/or manufacturing process. Typically in such testing, the integrated circuit devices are subject to electrical testing, e.g., “test patterns,” or “vectors,” to confirm functionality while being subjected to environmental stress. For example, an integrated circuit is heated and/or cooled to its specification limits while being electrically tested. In some cases, e.g., for qualification testing, an integrated circuit may be stressed beyond its specifications, for example, to determine failure points and/or to establish “guard band” information regarding its environmental specifications.
Traditionally, such testing has included placing one or more integrated circuits and their associated test interface(s) and support hardware into an environmental chamber. The environmental chamber would heat and/or cool the integrated circuit(s) under test, known as or referred to as a device under test, or “DUT,” as well as the test interface and support hardware, to the desired test temperature. Unfortunately, use of such test chambers has numerous drawbacks. For example, the limits and/or accuracy of such testing may be degraded due to environmental limits of the test interface circuits and/or devices. In addition, due to the large volumes of air and mass of mounting structures and interface devices required within an environmental test chamber, the environment inside such a test chamber may not be changed rapidly, limiting a rate of testing. Further, placing and removing DUTs and testing apparatus into and out of such test chambers further limits rates of testing, and requires complex and expensive mechanisms to perform such insertions and removals.
Recently, environmental test systems have been created that heat and/or cool a DUT directly, without placing the DUT and test apparatus into an environmental chamber. Such “chamber-less” test systems overcome many of the limitations of chamber-based testing. Unfortunately, chamber-less test systems introduce testing difficulties, particularly related to cooling integrated circuits under test.
Cooling of integrated circuits under test is typically performed by thermally coupling a cooling structure, e.g., metal, to the device under test. A cooling fluid, e.g., comprising glycol, is circulated through a portion of the cooling structure. To adjust the temperature of the cooling structure, the temperature of the cooling fluid may be adjusted. The flow of the cooling fluid may also be adjusted, e.g., increased, reduced, started, and/or stopped.
It is desirable to perform environmental testing on many, e.g., hundreds, of integrated circuits at the same time, beneficially increasing manufacturing throughput. Unfortunately, individual control of the flow and/or temperature of cooling fluids to hundreds of cooling structures is prohibitively complex and deleteriously limiting of test density. For example, individual control of a flow of a cooling fluid for each integrated circuit under test may require two cooling fluid valves per device under test. Such hundreds to thousands of valves and associated actuators would greatly enlarge a size requirement for a test apparatus, and, due to all of the mechanical elements, would be unreliable. Similarly, individual control of cooling fluid temperature would be unwieldy employing the cooling mechanisms that use cooling liquids described above.
Therefore, what is needed are systems and methods for thermal solutions available for massively parallel testing. What is additionally needed are systems and methods for thermal solutions for massively parallel testing that reduce or eliminate a need to change a temperature of a cooling structure. There is a further need for systems and methods for thermal solutions for massively parallel testing that are compatible and complementary with existing systems and methods of testing integrated circuits.
In accordance with an embodiment of the present invention, an apparatus for thermal control of a device under test (DUT) includes a cooling structure operable to provide cooling, the cooling structure operable to inlet cooling material via an inlet port thereof and operable to outlet cooling material via an outlet port thereof, a variable thermal conductance material (VTCM) layer disposed on a surface of the cooling structure, and a heater layer operable to generate heat based on an electronic control, and wherein the VTCM layer is operable to transfer cooling from the cooling structure to the heater layer. A thermal interface material layer is disposed on the heater layer. The thermal interface material layer is operable to provide thermal coupling and mechanical compliance with respect to the DUT. The apparatus includes a compression mechanism for providing compression to the VTCM layer to vary a thermal conductance of the VTCM layer. The compression mechanism is also for decoupling the VTCM layer from the heater layer.
Embodiments include the above and further include wherein a temperature of the thermal interface material layer is controlled by varying the electronic control to the heater layer and further by varying an amount of compression applied to the VTCM layer from the compression mechanism.
Embodiments include the above and further include wherein the compression mechanism includes a plunger that is pneumatically controlled.
Embodiments include the above and further include wherein the VTCM layer includes a material that varies in thermal conductance responsive to compression thereof.
Embodiments include the above and further include wherein the cooling material is a cooling liquid.
Embodiments include the above and further include wherein the heater layer includes a ceramic heater layer.
Embodiments include the above and further include wherein the heater layer includes an aluminum nitride layer.
Embodiments include the above and further include wherein the thermal interface material layer includes one of: indium; and graphite.
Embodiments include the above and further include wherein the thermal interface material layer includes an integrated temperature sensor.
Embodiments include the above and further include wherein the DUT is a packaged memory device.
In accordance with another embodiment of the present invention, an apparatus for thermal control of a device under test (DUT) includes a cooling structure operable to provide cooling and including an inlet port and an outlet port, the cooling structure operable to inlet cooling liquid via the inlet port thereof and operable to outlet cooling liquid via the outlet port, a variable thermal conductance material (VTCM) layer disposed on a surface of the cooling structure, wherein a thermal conductance characteristic of the VTCM varies with compression thereof, and a heater layer operable to generate heat based on an electronic control signal, and wherein the VTCM layer is operable to transfer cooling from the cooling structure to the heater layer. The apparatus further includes a thermal interface material layer disposed on the heater layer, wherein the thermal interface material layer is operable to provide thermal coupling and mechanical compliance with respect to the DUT, a socket alignment layer disposed between the VTCM layer and the heater layer; and a compression mechanism for providing compression to the VTCM layer to vary the thermal conductance characteristic thereof.
Embodiments include the above and further include wherein a temperature of the thermal interface material layer is controlled by varying the electronic control to the heater layer and further by varying an amount of compression applied to the VTCM layer from the compression mechanism.
Embodiments include the above and further include wherein the compression mechanism is a plunger that is pneumatically controlled.
Embodiments include the above and further include wherein the heater layer includes a ceramic heater layer.
Embodiments include the above and further include wherein the heater layer includes an aluminum nitride layer.
Embodiments include the above and further include wherein the thermal interface material layer includes one of: indium; and graphite.
Embodiments include the above and further include wherein the thermal interface material layer includes an integrated temperature sensor.
Embodiments include the above and further include wherein the DUT is a packaged memory device.
In accordance with further embodiments of the present invention, an apparatus for performing thermal control and testing of a device under test (DUT) includes a cooling structure operable to provide cooling, the cooling structure operable to inlet cooling liquid and operable to outlet cooling liquid, a variable thermal conductance material (VTCM) layer disposed on a surface of the cooling structure, wherein a thermal conductance characteristic of the VTCM varies with compression thereof, and a heater layer operable to generate heat based on an electronic control. The VTCM layer is operable to transfer cooling from the cooling structure to the heater layer. The apparatus further includes a thermal interface material layer disposed on the heater layer, wherein the thermal interface material layer is operable to provide thermal coupling and mechanical compliance with respect to the DUT, a compression mechanism for providing compression to the VTCM layer to vary a thermal conductance of the VTCM layer. The apparatus further includes a computer system for implementing a method of testing the DUT. The method includes applying input test signals to DUT and retrieving output signals from the DUT responsive to the input test signals.
Embodiments include the above and further include wherein the thermal interface material layer further includes an integrated temperature sensor; and wherein the method further includes varying a temperature of the DUT by varying the electronic control to the heater layer and further by varying an amount of compression applied to the VTCM layer from the compression mechanism, both responsive to the integrated temperature sensor.
The accompanying drawings, which are incorporated in and form a part of this specification, illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention. Unless otherwise noted, the drawings may not be drawn to scale.
Reference will now be made in detail to various embodiments of the invention, examples of which are illustrated in the accompanying drawings. While the invention will be described in conjunction with these embodiments, it is understood that they are not intended to limit the invention to these embodiments. On the contrary, the invention is intended to cover alternatives, modifications and equivalents, which may be included within the spirit and scope of the invention as defined by the appended claims. Furthermore, in the following detailed description of the invention, numerous specific details are set forth in order to provide a thorough understanding of the invention. However, it will be recognized by one of ordinary skill in the art that the invention may be practiced without these specific details. In other instances, well known methods, procedures, components, and circuits have not been described in detail as not to unnecessarily obscure aspects of the invention.
Each test island 130, 140, 150 may comprise test support for hundreds of devices under test (DUTs). For example, a teat island may comprise test support for 144 or 512 integrated circuit devices. A test island may comprise physical support and mounting for each device under test and an electrical interface for each device under test, e.g., for power and communication of test patterns. In accordance with embodiments of the present invention, a test island includes an individual device under test environmental unit, further described below, for each device under test.
DUT 210 is illustrated as packaged in a ball grid array (BGA) package. Embodiments in accordance with the present invention are well suited to other types of packaging for integrated circuits, including multi-chip modules, and are further well suited to testing unpackaged integrated circuit devices. In some embodiments, there may be a plurality of electrical connections coupling DUT 210 to automated test equipment (not shown) to provide electrical power and/or perform electrical tests. It is appreciated that environmental control unit 200 is not limited to testing integrated circuits and/or multi-chip modules. Rather, embodiments in accordance with the present invention are well suited to controlling temperature of a wide variety of systems.
Environmental control unit 200 comprises a cooling structure 260. Cooling structure 260 is configured to absorb or “sink” heat from other portions of environmental control unit 200 and/or DUT 210. Cooling structure 260 typically comprises highly thermally conductive materials, including, for example, metals. Cooling structure 260 may also comprise multi-material structures, for example, a structural material with low thermal conductivity in combination, e.g., filled, with a higher thermal conductivity material. Cooling structure 260 is configured to receive a cooling fluid via controllable inlet port 270, and discharge cooling fluid via controllable outlet port 280. Inlet port 270 and/or outlet port 280 may comprise a valve (not shown) in some embodiments. The cooling fluid may be inlet at a temperature of −60 degrees C., in some embodiments.
Environmental control unit 200 comprises a thermal interface material 220. Thermal interface material 220 is configured to provide a highly conductive and physically conformal interface between DUT 210 and the rest of environmental control unit 200. Thermal interface material 220 may comprise a built-in temperature sensor, e.g., a thermocouple (not shown). In some embodiments, a temperature sensor may be included in active interposer or heater 230, further described below. The temperature sensor has a temperature sensor interface 225 that communicates with a test controller (not shown).
Thermal interface material 220 is coupled to an active interposer or heater 230. Active interposer 230 is configured to apply thermal energy to DUT 210 via thermal interface material 220. Active interposer 230 may comprise a ceramic heater and/or a cartridge heater, in some embodiments. Active interposer 230 receives electrical power and/or control via interface 235. Active interposer 230 is highly thermally conductive, in some embodiments. Active interposer 230 may comprise a number of traces used as heating elements for controlling the head produce thereby.
Active interposer 230 is coupled to a socket alignment adapter 240. Socket alignment adapter 240 provides mechanical and spatial compliance and functions to align the stack of environmental control unit 200 with DUT 210 and its electrical test interface (not shown). Socket alignment adapter 240 is highly thermally conductive, in some embodiments.
The socket alignment adapter 240 is coupled to cooling structure 260 via variable conductance material 250. Variable resistance material 250 is characterized as having a thermal conductance that varies with an amount of compression and/or pressure applied to the material. For example, when variable conductance material 250 is compressed relative to its rest thickness 255, its thermal conductance increases, e.g., it conducts heat energy better than when at its rest thickness 255. By way of further example, when variable conductance material 250 is compressed a relatively large amount in comparison to its rest thickness 255, its thermal conductivity is increased more than when variable conductance material 250 is compressed by a relatively lesser amount. Embodiments in accordance with the present invention are also well suited to a variable conductance material characterized as decreasing its thermal conductance as it is compressed and/or has pressure applied.
In the
In order to apply heat energy to DUT 210, active interposer/heater 230 may be controlled to produce heat energy. Since the cooling structure 260 is decoupled from the active interposer/heater 230 and the DUT 210, substantially all of the heat output of the active interposer/heater 230 is available for thermal coupling into DUT 210.
Advantageously, since the cooling structure 260 is decoupled from the DUT 210 by gap 410, it is not necessary to change the temperature of the cooling structure 260. For example, the flow rate and/or temperature of a cooling fluid applied to the cooling structure 260 need not be changed. Beneficially, since the flow rate and/or temperature of a cooling fluid applied to the cooling structure 260 need not be changed, the control of the cooling fluid is greatly simplified. For example, the temperature of the cooling fluid may not be monitored and/or controlled, or the requirements for controlling temperature may be reduced. The flow rate of the cooling fluid may not be monitored and/or controlled, or the requirements for controlling flow rate may be reduced. In some embodiments, requirements for valves to control a flow rate of the cooling fluid may be decreased in comparison to the conventional art. For example, cooling fluid valves may be decreased in quantity and/or functionality, e.g., valves may not have a partial flow capacity. In some embodiments, there may not be valves to control flow to individual instances of cooling structure 260.
In addition, since the cooling structure 260 is decoupled from the active interposer/heater 230 and the DUT 210, the heating capacity of the active interposer/heater 230 may be beneficially reduced in comparison to the prior art, since active interposer/heater 230 is not required to overcome the active or latent heat absorption of cooling structure 260. Such a reduction in the requirements of active interposer/heater 230 may lead to reductions in size, cost, complexity, and/or power consumption of an automated test system.
In the embodiment of
If a lesser amount of cooling is desired, for example, the temperature of cooling structure 260 is colder than the desired temperature for DUT 210, the embodiment of
In the embodiment of
In this novel manner, a device under test, e.g., DUT 210, may be controlled, e.g., heated and/or cooled, to a desirable temperature without changing the temperature of a cooling structure, e.g., cooling structure 260. For example, an amount of cooling may be varied according to the thickness and/or compression of variable thermal conductance material 250, or decoupling variable thermal conductance material 250 from DUT 210 by a gap 410 (
Central processor complex 1105 may comprise a single processor or multiple processors, e.g., a multi-core processor, or multiple separate processors, in some embodiments. Central processor complex 1105 may comprise various types of well-known processors in any combination, including, for example, digital signal processors (DSP), graphics processors (GPU), complex instruction set (CISC) processors, reduced instruction set (RISC) processors, and/or very long word instruction set (VLIW) processors. In some embodiments, exemplary central processor complex 1105 may comprise a finite state machine, for example, realized in one or more field programmable gate array(s) (FPGA), which may operate in conjunction with and/or replace other types of processors to control embodiments in accordance with the present invention.
Electronic system 1100 may also include a volatile memory 1115 (e.g., random access memory RAM) coupled with the bus 1150 for storing information and instructions for the central processor complex 1105, and a non-volatile memory 1110 (e.g., read only memory ROM) coupled with the bus 1150 for storing static information and instructions for the processor complex 1105. Electronic system 1100 also optionally includes a changeable, non-volatile memory 1120 (e.g., NOR flash) for storing information and instructions for the central processor complex 1105 which can be updated after the manufacture of system 1100. In some embodiments, only one of ROM 1110 or Flash 1120 may be present.
Also included in electronic system 1100 of
Electronic system 1100 may comprise a display unit 1125. Display unit 1125 may comprise a liquid crystal display (LCD) device, cathode ray tube (CRT), field emission device (FED, also called flat panel CRT), light emitting diode (LED), plasma display device, electro-luminescent display, electronic paper, electronic ink (e-ink) or other display device suitable for creating graphic images and/or alphanumeric characters recognizable to the user. Display unit 1125 may have an associated lighting device, in some embodiments.
Electronic system 1100 also optionally includes an expansion interface 1135 coupled with the bus 1150. Expansion interface 1135 can implement many well known standard expansion interfaces, including without limitation the Secure Digital Card interface, universal serial bus (USB) interface, Compact Flash, Personal Computer (PC) Card interface, CardBus, Peripheral Component Interconnect (PCI) interface, Peripheral Component Interconnect Express (PCI Express), mini-PCI interface, IEEE 1394, Small Computer System Interface (SCSI), Personal Computer Memory Card International Association (PCMCIA) interface, Industry Standard Architecture (ISA) interface, RS-232 interface, and/or the like. In some embodiments of the present invention, expansion interface 1135 may comprise signals substantially compliant with the signals of bus 1150.
A wide variety of well-known devices may be attached to electronic system 1100 via the bus 1150 and/or expansion interface 1135. Examples of such devices include without limitation rotating magnetic memory devices, flash memory devices, digital cameras, wireless communication modules, digital audio players, and Global Positioning System (GPS) devices.
System 1100 also optionally includes a communication port 1140. Communication port 1140 may be implemented as part of expansion interface 1135. When implemented as a separate interface, communication port 1140 may typically be used to exchange information with other devices via communication-oriented data transfer protocols. Examples of communication ports include without limitation RS-232 ports, universal asynchronous receiver transmitters (UARTs), USB ports, infrared light transceivers, ethernet ports, IEEE 1394, and synchronous ports.
System 1100 optionally includes a network interface 1160, which may implement a wired or wireless network interface. Electronic system 1100 may comprise additional software and/or hardware features (not shown) in some embodiments.
Various modules of system 1100 may access computer readable media, and the term is known or understood to include removable media, for example, Secure Digital (“SD”) cards, CD and/or DVD ROMs, diskettes and the like, as well as non-removable or internal media, for example, hard drives, solid state drive s (SSD), RAM, ROM, flash, and the like.
Embodiments in accordance with the present invention provide systems and methods for thermal solutions for massively parallel testing. In addition, embodiments in accordance with the present invention provide systems and methods for thermal solutions for massively parallel testing that reduce or eliminate a need to change a temperature of a cooling structure. Further, embodiments in accordance with the present invention provide systems and methods for thermal solutions for massively parallel testing that are compatible and complementary with existing systems and methods of testing integrated circuits.
Although the invention has been shown and described with respect to a certain exemplary embodiment or embodiments, equivalent alterations and modifications will occur to others skilled in the art upon the reading and understanding of this specification and the annexed drawings. In particular regard to the various functions performed by the above described components (assemblies, devices, etc.) the terms (including a reference to a “means”) used to describe such components are intended to correspond, unless otherwise indicated, to any component which performs the specified function of the described component (e.g., that is functionally equivalent), even though not structurally equivalent to the disclosed structure which performs the function in the herein illustrated exemplary embodiments of the invention. In addition, while a particular feature of the invention may have been disclosed with respect to only one of several embodiments, such feature may be combined with one or more features of the other embodiments as may be desired and advantageous for any given or particular application.
Various embodiments of the invention are thus described. While the present invention has been described in particular embodiments, it should be appreciated that the invention should not be construed as limited by such embodiments, but rather construed according to the below claims.
This Application is a Continuation of, commonly owned U.S. patent application Ser. No. 17/479,998, filed Sep. 20, 2021, entitled “Thermal Solution for Massively Parallel Testing” to Kabbini et al., now U.S. Pat. No. 11,549,981 which in turn claims benefit of U.S. Provisional Application Ser. No. 63/086,522, filed Oct. 1, 2020, entitled “Thermal Solution for Massively Parallel Testing.” All such applications are hereby incorporated herein by reference in their entireties.
Number | Name | Date | Kind |
---|---|---|---|
5126656 | Jones | Jun 1992 | A |
5164661 | Jones | Nov 1992 | A |
5239093 | Cheng | Aug 1993 | A |
5315240 | Jones | May 1994 | A |
5329093 | Okano | Jul 1994 | A |
5420521 | Jones | May 1995 | A |
5821505 | Tustaniwskyj et al. | Oct 1998 | A |
6184504 | Cardella | Feb 2001 | B1 |
6359264 | Schaper et al. | Mar 2002 | B1 |
6389225 | Malinoski et al. | May 2002 | B1 |
6498899 | Malinoski et al. | Dec 2002 | B2 |
6515470 | Suzuki et al. | Feb 2003 | B2 |
6668570 | Wall et al. | Dec 2003 | B2 |
6711904 | Law et al. | Mar 2004 | B1 |
6825681 | Feder et al. | Nov 2004 | B2 |
6862405 | Malinoski et al. | Mar 2005 | B2 |
6985000 | Feder et al. | Jan 2006 | B2 |
7042240 | Lopez et al. | May 2006 | B2 |
7138811 | Mahoney et al. | Nov 2006 | B1 |
7151388 | Gopal et al. | Dec 2006 | B2 |
7311782 | Strang et al. | Dec 2007 | B2 |
7355428 | Kabbani et al. | Apr 2008 | B2 |
7411792 | Richards et al. | Aug 2008 | B2 |
7436059 | Ouyang | Oct 2008 | B1 |
7519880 | Johnson et al. | Apr 2009 | B1 |
7626407 | Kabbani | Dec 2009 | B2 |
7659738 | Hong | Feb 2010 | B2 |
7726145 | Nakamura | Jun 2010 | B2 |
7755899 | Stenmark | Jul 2010 | B2 |
7781883 | Sri-Jayantha et al. | Aug 2010 | B2 |
7830164 | Earle et al. | Nov 2010 | B2 |
7848106 | Merrow | Dec 2010 | B2 |
8343280 | Iimuro | Jan 2013 | B2 |
8558540 | Wu et al. | Oct 2013 | B2 |
8772682 | Ambal et al. | Jul 2014 | B2 |
8927907 | Fink et al. | Jan 2015 | B2 |
8970244 | Suzuki et al. | Mar 2015 | B2 |
9080820 | Bolton | Jul 2015 | B2 |
9291667 | Armstrong et al. | Mar 2016 | B2 |
9307578 | Pease | Apr 2016 | B2 |
9310145 | Colongo et al. | Apr 2016 | B2 |
9414526 | Mann et al. | Aug 2016 | B2 |
9494353 | Yu et al. | Nov 2016 | B2 |
9594113 | Davis et al. | Mar 2017 | B2 |
9766287 | Narasaki et al. | Sep 2017 | B2 |
9841772 | Bucher | Dec 2017 | B2 |
10056225 | Gaff et al. | Aug 2018 | B2 |
10126356 | Barabi et al. | Nov 2018 | B2 |
10163668 | Steinhauser | Dec 2018 | B2 |
10354785 | Yamaguchi | Jul 2019 | B2 |
10656200 | Cruzan et al. | May 2020 | B2 |
10775408 | Carvalho et al. | Sep 2020 | B2 |
10908207 | Barabi et al. | Feb 2021 | B2 |
10955466 | Tsai et al. | Mar 2021 | B2 |
10983145 | Akers et al. | Apr 2021 | B2 |
11143697 | Wolff | Oct 2021 | B2 |
20020026258 | Suzuki et al. | Feb 2002 | A1 |
20020118032 | Norris et al. | Aug 2002 | A1 |
20030155939 | Lutz et al. | Aug 2003 | A1 |
20040017185 | Song et al. | Jan 2004 | A1 |
20050026476 | Mok et al. | Feb 2005 | A1 |
20050086948 | Milke-Rojo et al. | Apr 2005 | A1 |
20050103034 | Hamilton et al. | May 2005 | A1 |
20050151553 | Kabbani et al. | Jul 2005 | A1 |
20060158207 | Reitinger | Jul 2006 | A1 |
20060290370 | Lopez | Dec 2006 | A1 |
20090160472 | Segawa et al. | Jun 2009 | A1 |
20090218087 | Oshima | Sep 2009 | A1 |
20100042355 | Aube et al. | Feb 2010 | A1 |
20110050268 | Co et al. | Mar 2011 | A1 |
20110074080 | Di Stefano et al. | Mar 2011 | A1 |
20130181576 | Shiozawa et al. | Jul 2013 | A1 |
20130285686 | Malik et al. | Oct 2013 | A1 |
20140035715 | Takahashi et al. | Feb 2014 | A1 |
20140251214 | Cuvalci et al. | Sep 2014 | A1 |
20150028912 | Cho et al. | Jan 2015 | A1 |
20150137842 | Murakami et al. | May 2015 | A1 |
20150226794 | Chen | Aug 2015 | A1 |
20160084880 | Locicero et al. | Mar 2016 | A1 |
20160247552 | Kim et al. | Aug 2016 | A1 |
20160351526 | Boyd et al. | Dec 2016 | A1 |
20170102409 | Sarhad et al. | Apr 2017 | A1 |
20180024188 | Cruzan et al. | Jan 2018 | A1 |
20180189159 | Carmichael et al. | Jul 2018 | A1 |
20180218926 | Stuckey et al. | Aug 2018 | A1 |
20190064254 | Bowyer et al. | Feb 2019 | A1 |
20190162777 | Chiang et al. | May 2019 | A1 |
20190271719 | Sterzbach | Sep 2019 | A1 |
20190310314 | Liu et al. | Oct 2019 | A1 |
20190346482 | Kiyokawa et al. | Nov 2019 | A1 |
20200041564 | Cojocneanu | Feb 2020 | A1 |
20200363104 | MacDonald et al. | Nov 2020 | A1 |
20200371155 | Walczyk et al. | Nov 2020 | A1 |
20210071917 | Pei et al. | Mar 2021 | A1 |
20210183668 | Cagle | Jun 2021 | A1 |
20210293495 | Barako et al. | Sep 2021 | A1 |
20210396801 | Ranganathan et al. | Dec 2021 | A1 |
20220044084 | Cardy | Feb 2022 | A1 |
20220082587 | Gopal et al. | Mar 2022 | A1 |
20220137092 | Ranganathan et al. | May 2022 | A1 |
20220137129 | Ranganathan et al. | May 2022 | A1 |
20220206061 | Ranganathan et al. | Jun 2022 | A1 |
Number | Date | Country |
---|---|---|
101073016 | Nov 2007 | CN |
103038751 | Apr 2013 | CN |
105144114 | Dec 2015 | CN |
109716513 | May 2019 | CN |
110214270 | Sep 2019 | CN |
110618903 | Dec 2019 | CN |
3270261 | Apr 2023 | EP |
2005156172 | Jun 2005 | JP |
2008275512 | Nov 2008 | JP |
446682 | Jul 2001 | TW |
200535440 | Nov 2005 | TW |
200620596 | Jun 2006 | TW |
200628818 | Aug 2006 | TW |
201226579 | Jul 2012 | TW |
201229535 | Jul 2012 | TW |
201323883 | Jun 2013 | TW |
201504647 | Jul 2013 | TW |
201447325 | Dec 2014 | TW |
201636618 | Dec 2014 | TW |
I651540 | Jan 2016 | TW |
201608254 | Mar 2016 | TW |
201712459 | Apr 2017 | TW |
201834134 | Sep 2018 | TW |
201840996 | Nov 2018 | TW |
202004980 | Jan 2020 | TW |
202043787 | Dec 2020 | TW |
2016122039 | Aug 2016 | WO |
201712076 | Jan 2017 | WO |
2017015052 | Jan 2017 | WO |
2017039936 | Mar 2017 | WO |
2020159954 | Aug 2020 | WO |
Entry |
---|
Ranganathan et al. D517: Shielded Socket and Carrier for High-Volume Test of Semiconductor Devices; Powerpoint; 12 pp. Sep. 30, 2021. |
Number | Date | Country | |
---|---|---|---|
20230228812 A1 | Jul 2023 | US |
Number | Date | Country | |
---|---|---|---|
63086522 | Oct 2020 | US |
Number | Date | Country | |
---|---|---|---|
Parent | 17479998 | Sep 2021 | US |
Child | 18094899 | US |