Patent Application
20240038631
The present invention relates to the field of integrated circuit (IC) technology and, in particular, to a three-dimensional (3D) IC module and a method of fabricating such a 3D IC module.
The boom of the electronics industry provides a main driving force for the evolution of the contemporary packaging technology. Main pursuits of advanced packaging are increased miniaturization, higher density, operation at higher frequencies and higher speeds, higher performance, higher reliability and lower cost, and system-in-packages (SiPs) is one of the most important techniques with the greatest potential to meet these high-density system integration demands. As a powerful and compact system, a SiP is a three-dimensional (3D) integrated circuit (IC) module obtained by integrating and assembling active components, passive components, MEMS devices or discrete chips (e.g., photoelectric chips, biological chips, memory chips, logic chips, computing chips), which have different functions or are fabricated by different processes. For example, some 3D IC modules used in a number of emerging applications (e.g., edge computing, artificial intelligence) are system-on-chip (SoC) products, which include 3D integrated logic and memory chips and thus possess both the high-speed computing ability of logic chips and high-speed storage ability of memory chips.
Despite their excellent performance per unit area achieved by SiP technology, those 3D IC modules tend to suffer from inadequate heat dissipation due to high power consumption per unit area. For example, in edge computing or artificial intelligence applications, logic chips consume much power due to extremely high computational burden, contributing to total power of the modules which may be as high as 100 or more watts. Uneven heat dissipation is another challenge. Extreme heat generation and uneven heat dissipation will lead to degradations in chip performance and reliability. For example, a DRAM chip in a module may have an unstable refresh rate due to extreme heat generated by a logic chip incorporated in the same module.
The present invention provides a 3D IC module with enhanced heat dissipation ability, as well as a method of fabricating such a 3D IC module.
In one aspect, the present invention provides a three-dimensional (3D) integrated circuit (IC) module including a semiconductor structure and a first passivation layer on the semiconductor structure. The semiconductor structure includes at least two substrates which are stacked vertically one on another and electrically connected to one another. Additionally, the semiconductor structure includes at least one conductive hole located in a topmost one of the substrates and configured for connection with an internal specified metal layer. In the topmost substrate in the semiconductor structure, a trench arranged to avoid the conductive hole is also formed, and the first passivation layer spans over and covers the trench to define a heat exchange channel.
Optionally, the heat exchange channel may include at least one heat dissipation medium inlet and at least one heat dissipation medium outlet, which are configured to allow a heat dissipation medium to be introduced to the heat exchange channel through the heat dissipation medium inlet and discharged therefrom through the heat dissipation medium outlet, the heat dissipation medium inlet provided in a side face and/or an upper surface of the semiconductor structure, the heat dissipation medium outlet provided in a side face and/or the upper surface of the semiconductor structure.
Optionally, the topmost substrate may include a substrate layer and an interconnect layer underlying the substrate layer, wherein the specified metal layer is situated within the interconnect layer, and the conductive hole extends through the substrate layer, with a bottom surface located within the interconnect layer.
Optionally, a bottom surface of the heat exchange channel may be located within the substrate layer.
Optionally, the conductive hole may include a pad metal layer, which extends from the inside of the conductive hole over an upper surface of the first passivation layer.
Optionally, the 3D IC module may further include a second passivation layer on the first passivation layer, wherein a portion of the pad metal layer is defined by and exposed from the second passivation layer to serve as a pad.
Optionally, the upper surface of the semiconductor structure may include a heat exchange region for accommodating the heat exchange channel and a plurality of electrical connection regions for accommodating a set of conductive holes and pads, wherein the heat exchange region interlaces with the plurality of electrical connection regions, or the electrical connection regions are all disposed around the heat exchange region.
In another aspect, the present invention provides a method of fabricating a 3D IC module, including the steps of:
Optionally, the topmost substrate may include a substrate layer and an interconnect layer underlying the substrate layer, wherein the specified metal layer is situated within the interconnect layer, and the conductive hole extends through the substrate layer with a bottom surface located within the interconnect layer.
Optionally, a depth of the trench may be smaller than or equal to the depth of the contact hole.
Optionally, the method may further include, after the contact hole and the trench are formed and before the first passivation layer is formed, conformally forming a surface cap layer over the semiconductor structure, which covers inner surfaces of the contact hole and the trench but does not fill up the trench, wherein after the first passivation layer is etched and before the pad metal layer is formed, the surface cap layer on a bottom surface of the contact hole is at least partially removed, thereby causing the exposure of the specified metal layer through the contact hole.
Optionally, the method may further include:
In the 3D IC module of the present invention, the conductive hole for connection with the internal specified metal layer and the trench arranged to avoid the conductive hole are formed in the topmost substrate of the semiconductor structure. Moreover, the first passivation layer spans over and covers the trench so that the first passivation layer covering the trench to define the heat exchange channel. During operation of 3D IC module, a heat dissipation medium may be caused to flow through the heat exchange channel to facilitate heat dissipation. Thus, the 3D IC module has enhanced heat dissipation ability and is substantially immune from the problems of excessive heat build-up and uneven heat dissipation. This helps optimize performance and reliability of the 3D IC module.
In the method of the present invention, the at least one contact hole and the trench arranged to avoid the contact hole are first formed in the topmost substrate of the semiconductor structure, and the first passivation layer is then formed on the semiconductor structure so as to cover the upper surface of the semiconductor structure and span over the trench. In this way, the first passivation layer covers the trench to define the heat exchange channel. After that, the first passivation layer is etched, and exposure of the specified metal layer in the semiconductor structure is caused through the contact hole. The portion of the pad metal layer in the contact hole is electrically connected to the specified metal layer, thereby forming the conductive hole. In this method, during the formation of the conductive hole in the semiconductor structure, the heat exchange channel for enhancing heat dissipation is simultaneously formed, making the fabrication easier without causing a significant increase in cost. As the heat exchange channel is routed on the top of the semiconductor structure 100 off the conductive hole, it will not expand the size of the module. During operation of the 3D IC module, a heat dissipation medium may be continuously supplied to and discharged from the heat exchange channel to provide heat exchange.
In these figures:
Three-dimensional (3D) integrated circuit (IC) modules and methods of fabrication proposed in the present invention will be described in detail below with reference to the accompanying drawings and to specific embodiments. Advantages and features of the invention will become more apparent from the following description. It will be understood that the figures are provided in a very simplified form not necessarily drawn to exact scale for the only purpose of facilitating easy and clear description of the disclosed embodiments.
It is to be noted that, the terms “first”, “second” and the like may be used hereinafter to distinguish between similar elements without necessarily implying any particular ordinal or chronological sequence. It will be understood that the terms so used are interchangeable under appropriate circumstances such that the embodiments of the invention described herein are, for example, capable of operation in sequences other than those illustrated or otherwise described herein. Similarly, if a method is described herein as including a series of steps, the order of such steps as presented herein is not necessarily the only order in which such steps may be performed, and certain steps of the stated steps may possibly be omitted and/or certain other steps not described herein may possibly be added to the method. It will be understood, as used herein, spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is inverted or otherwise oriented (e.g., rotated), the exemplary term “over” can encompass an orientation of “under” and other orientations.
A specific embodiment of the above method of fabricating a 3D IC module will be described below with reference to the other accompanying drawings.
In particular, the semiconductor structure 100 may be a 3D laminated structure obtained using a 3D integration and assembly technique. In the 3D integration and assembly technique, active components, passive components, MEMS devices or discrete chips (e.g., photoelectric chips, biological chips, memory chips, logic chips, computing chips) of different functions and fabricated using different processes along a 3D direction (e.g., an X, Y or Z direction in an orthogonal coordinate system) are assembled into a complete circuit system. Depending on design requirements, a varying number of devices (or chips) may be integrated in the semiconductor structure 100. In embodiments of the present invention, the semiconductor structure 100 provided in step S1 includes at least two substrates stacked vertically one on another. Here, the “substrates” refer to semiconductor substrates separately obtained from individual processes. Each of the substrates may include a substrate layer (e.g., silicon substrate, SOI substrate or another suitable substrate), as well as fabricated on the basis of the substrate layer, semiconductor devices, interconnect layers, passivation layers and the like (referred to as a dielectric layer). In order to form the semiconductor structure 100, the substrates may be stacked together by gluing, bonding or otherwise. For example, they may be glued or bonded together with the substrate layers being adjacent to each other or opposite to each other (as shown in
The following embodiments are set forth in the context of the semiconductor structure integrating two substrates along the direction perpendicular to surfaces of the substrate, as an example. As shown in
Referring to
In this embodiment, a conductive hole for electrically leading out the specified metal layer 21 in the semiconductor structure 100 is to be formed in the contact hole 110, and a heat dissipation medium (e.g., liquid or gas) is to be introduced in the heat exchange channel provided by the trench 120 arranged to avoid the contact hole 110 during operation of the 3D IC module to enhance heat dissipation. It is unnecessary for the trench 120 to be connected to any conductive component, and in order to avoid adversely affecting the interconnect system in the semiconductor structure 100, it is preferred that no conductive component in semiconductor structure 100 is exposed in the trench 120.
In step S2, before the second substrate 20 is etched, a protective layer 101 may be formed on the second substrate 20. The protective layer 101 may include silicon oxide, silicon nitride, silicon oxynitride or a layer stack thereof. In the etching process on the second substrate 20, the protective layer 101 may serve as a hard mask layer. Patterns for the contact hole 110 and the trench 120 may be formed in a single photolithography step, or in two separate photolithography steps. Preferably, they are formed in a single photolithography and etching process. In particular, the process may include: at first, coating a photoresist layer on the protective layer 101 and patterning the photoresist layer by exposing with a single photomask and developing the photoresist layer; next, with the patterned photoresist layer serving as a mask, etching and patterning the protective layer 101; and then removing the photoresist layer and, with the patterned protective layer 101 serving as a mask, etching the second substrate 20 to form therein the contact hole 110 and the trench 120.
The contact hole 110 and the trench 120 are formed by performing the downward etching process performed on the topmost substrate (in this embodiment, the second substrate 20), the contact hole 110 and the trench 120 are both upwardly open. The distance between an upper surface of the topmost substrate (in this embodiment, an upper surface of the protective layer 101) and a bottom surface of the contact hole 110 is taken as the depth of the contact hole 110, and the distance between the upper surface of the topmost substrate and a bottom surface of the trench 120 is taken as a depth of the trench 120. Referring to
In this embodiment, both the contact hole 110 and the trench 120 formed in step S2 are TSV holes. The depth of the trench 120 may be equal to the depth of the contact hole 110, or not. For example, the depth of the trench 120 may be smaller than the depth of the contact hole 110. The depths of the trench 120 and the contact hole 110 may be in the range of about 5 μm to 10 μm. In the example shown in
In this embodiment, a first passivation layer is subsequently formed so as to span over and cover the trench 120 to define the heat exchange channel. Therefore, the trench 120 may be designed to have a narrow width (a dimension measured in a plane parallel to the second substrate 20 along a direction perpendicular to the extension direction of the trench 120), for example, in the range of approximately 0.3 μm to 100 μm. The contact hole 110 may, for example, have a circular, elliptical or polygonal cross-section along the plane parallel to the second substrate 20. The width of the trench 120 in the plane parallel to the second substrate 20 may be configured to be smaller than a maximum opening size of the contact hole 110.
In some embodiments, the semiconductor structure 100 may require two or more pads configured for connection with the same specified metal layer or different specified metal layers in the semiconductor structure 100. In this case, as many contact holes 110 as the pads may be formed in step S2. The trench 120 that provides the heat exchange channel may be composed of multiple sections extending in different regions so as to come into communication with one another, or include multiple sections extending in different regions so as not to come into communication with one another. At least one heat dissipation medium inlet and at least one heat dissipation medium outlet (not shown) may be provided at terminal ends of the trench 120. A heat dissipation medium may be introduced into the heat exchange channel through the heat dissipation medium inlet and discharged therefrom through the heat dissipation medium outlet. Either of the heat dissipation medium inlet and the heat dissipation medium outlet may be arranged on a side face of the second substrate 20. However, the present invention is not so limited. Either of the heat dissipation medium inlet and the heat dissipation medium outlet may be alternatively arranged at a side face location of the semiconductor structure 100 above or below a plane of the trench 120. Still alternatively, either of the heat dissipation medium inlet and the heat dissipation medium outlet may be arranged on the upper or lower surface of the semiconductor structure 100.
The upper surface of the semiconductor structure 100 may define a heat exchange region for accommodating the heat exchange channel and an electrical connection region for accommodating a contact hole/pad pair. In this case, the aforementioned contact hole 110 is formed in the electrical connection region, and the trench 120 is formed in the heat exchange region. For example, there may be one or more such electrical connection regions. Arrangement examples of the contact hole 110 and the trench 120 in the second substrate 20 will be described with reference to
The present invention is not limited to the arrangements of contact holes 110 and the trench 120 in the upper surface of the semiconductor structure 100 shown in
In an optional embodiment, subsequent to the formation of the contact hole 110 and the trench 120 and prior to the formation of the first passivation layer 103, the method of fabricating a 3D IC module may further include the step of forming a surface cap layer 102 on the semiconductor structure 100. Referring to
The first passivation layer 103 may be formed over the semiconductor structure 100 after the formation of the surface cap layer 102. The first passivation layer 103 may be formed of silicon oxide, silicon nitride, silicon oxynitride or another material optionally using a chemical vapor deposition (CVD) process. In this embodiment, the CVD process may be controlled (e.g., by controlling the film formation rate of the CVD) so that the resultant first passivation layer 103 covers the upper surface of the second substrate 20 and spans over and covers the trench 120 so that a closed channel is formed, i.e., the heat exchange channel 120a according to the present embodiment. In other words, the first passivation layer 103 serves as a cap layer of the heat exchange channel 120a. During operation of the 3D IC module, a heat dissipation medium may be introduced to and circulate through the heat exchange channel, thereby taking away heat generated by the 3D IC module and enhancing heat dissipation. In an alternatively embodiment, the first passivation layer 103 may be formed in step S3 so as to fill up and cover the trench 120. In this case, release holes exposing the material of the first passivation layer in the trench may be subsequently formed by an etching process performed on the first passivation layer 103 (e.g., release holes may be formed by the etching process in step S4), and the material of the first passivation layer in the trench may be etched and removed through the release holes. After the etching process is complete, a dielectric material may be deposited to close the release holes. In this way, the heat exchange channel can also be formed along the trench.
In one embodiment, after the first passivation layer 103 is etched through, when the specified metal layer 21 remains unexposed due to the presence of the surface cap layer 102 and/or the dielectric layer of the semiconductor structure 100 thereon, instead of an etching process that proceeds downwardly from the entire bottom surface of the contact hole 110, a patterning process may be employed to remove the surface cap layer 102 and/or the dielectric layer under only a desired portion of the bottom surface of the contact hole 110 to expose the specified metal layer 21 under the contact hole 110.
The pad metal layer 104 may be formed of a material including one or more metals selected from, among others, aluminum, copper, nickel, zinc, tin, silver, gold, tungsten and magnesium or including an alloy of a metal such as aluminum, copper, nickel, zinc, tin, silver, gold, tungsten or magnesium. The pad metal layer 104 may be formed by physical vapor deposition (PVD), electroplating or electroless plating and subsequent patterning. For example, forming the pad metal layer 104 by electroplating may include: firs of all, forming a seed layer on inner surfaces of the contact hole 110 and an upper surface of the first passivation layer 103 by PVD or sputtering; then placing the semiconductor structure 100 with the seed layer in a plating tank of electroplating equipment and removing it therefrom after a predetermined period of time so that a plating layer is formed on the inner surfaces of the contact hole 110 and the upper surface of the first passivation layer 103; and after that, forming the pad metal layer 104 by removing unwanted portions of the plating and seed layers on the upper surface of the semiconductor structure 100 by a photolithography and etching process.
In an optional embodiment, the method of fabricating a 3D IC module may further include the step of forming a pad.
The second passivation layer 105 is formed to protect the semiconductor structure 100 with the pad metal layer 104 being formed thereon, and as a result of patterning the second passivation layer 105, an opening is formed therein, which exposes the underlying pad metal layer 104. The location of the opening depends on the location of the portion of the pad metal layer 104 that serves as the pad 104a. In this embodiment, the portion of the pad metal layer 104 exposed from the second passivation layer 105 serves as the pad 104a. The pad 104a may be directly electrically connected to an external device. Alternatively, a solder bump (or solder ball) may be further formed on the pad 104a. In this case, the pad 104a may be electrically connected to an external device via the solder bump. The second passivation layer 105 may be formed of an oxide or nitride of silicon, such as silica, silicon nitride or silicon oxynitride, or a dielectric material such as magnesia, zirconia, alumina, lead zirconate titanate or gallium arsenide. The second passivation layer 105 may be alternatively formed of an organic material, such as a polyimide-based polymer, a propargyl ether polymer, a cyclobutane polymer, a perfluorocyclobutyl (PFCB) polymer, benzocyclobutene (BCB) or the like. The second passivation layer 105 may also be a stack of layers of different materials.
From the foregoing steps, the 3D IC module can be obtained. In the above method, during the formation of the conductive hole 110a in the semiconductor structure 100, the heat exchange channel 120a for enhancing heat dissipation is simultaneously formed, making the fabrication easier without causing a significant increase in cost. As the heat exchange channel 120a is routed on the top of the semiconductor structure 100 off the conductive hole 110a, it will not expand the size of the 3D IC module. During operation of the 3D IC module, a heat dissipation medium may be continuously supplied to and discharged from the heat exchange channel 120a to provide heat exchange. A device for supplying and recovering the heat dissipation medium may be integrated within the 3D IC module to provide an IC module with self-circulating heat exchange capabilities. Alternatively, the device may be a standalone device deployed around the 3D IC module.
Embodiments of the present invention further relate to a 3D IC module, which can be made using a method as defined above. Referring to
Each substrate in the semiconductor structure 100 may include a substrate layer, as well as fabricated on the basis of the substrate layer, semiconductor devices, interconnect layers, passivation layers and the like (referred to as a dielectric layer). In order to form the semiconductor structure 100, the substrates may be stacked together by gluing, bonding or otherwise. For example, they may be glued or bonded together with the substrate layers being adjacent to each other or opposite to each other (as shown in
Specifically, the conductive hole 110a includes a contact hole 110 formed in the semiconductor structure 100 and a pad metal layer 104 covering inner surfaces of the contact hole 110. The pad metal layer 104 extends from the inside of the conductive hole 110a over an upper surface of the first passivation layer 103. The conductive hole 110a may extend through the first passivation layer 103. The 3D IC module may further include a second passivation layer 105 on the first passivation layer 103, the second passivation layer 105 defines and exposes a portion of the pad metal layer 104. The portion of the pad metal layer 104 exposed from the second passivation layer 105 serves as a pad 104a of the 3D IC module.
Continuing the example of
In order to enable introduction and recovery of a heat dissipation medium, the heat exchange channel 120a includes at least one heat dissipation medium inlet and at least one heat dissipation medium outlet. The heat dissipation medium can be introduced to the heat exchange channel through the heat dissipation medium inlet and discharged therefrom through the heat dissipation medium outlet. The heat dissipation medium inlet may be provided in a side face and/or the upper surface of the semiconductor structure, and the dissipation medium outlet may also be provided in a side face and/or the upper surface of the semiconductor structure.
As noted above in the description of the method of fabricating a 3D IC module, the trench 120 of the heat exchange channel 120a and the contact hole 110 of the conductive hole 110a may be formed in a single photolithography and etching process. It is not necessary for the specified metal layer 21 in the semiconductor structure 100 to be exposed in the trench 120. A width of the trench 120, i.e., a width of the heat exchange channel 120a may be in the range of approximately 0.3 μm to 100 μm. The distance between an upper surface of the topmost substrate (in this embodiment, an upper surface of a protective layer 101) and a bottom surface of the contact hole 110 is taken as a depth of the contact hole 110, and the distance between the upper surface of the topmost substrate and a bottom surface of the trench 120 is taken as a depth of the trench 120. The depth of the trench 120 may be in the range of approximately 5 μm to 10 μm. A depth of the heat exchange channel 120a may be smaller than or equal to the depth of the conductive hole 110a. The heat exchange channel 120a may account for a proportion of the total area of the upper surface of the semiconductor structure 100, which may be determined according to the size of an area available for its accommodation and heat dissipation requirements. In particular, the proportion may vary in the range of approximately 0.1% to 99%. In the upper surface of the semiconductor structure 100, the heat exchange channel 120a may be evenly distributed according to certain rules, or locally concentrated in one or more regions. For example, in an embodiment, the heat exchange channel may be more densely routed across some regions of the upper surface of the 3D IC module, which tend to cause an uneven heat distribution due to release of more heat there. In this way, excessive local heat build-up and uneven heat dissipation in the 3D IC module can be avoided.
In the 3D IC module of the present invention, the conductive hole 110a for connection with the internal specified metal layer 21 and the trench 120 arranged to avoid the conductive hole 110a are formed in the topmost substrate of the semiconductor structure 100. Moreover, the first passivation layer 103 spans over and covers the trench 120 to define the heat exchange channel 120a. During operation of 3D IC module, a heat dissipation medium may be caused to flow through the heat exchange channel 120a to facilitate heat dissipation. Thus, the 3D IC module has enhanced heat dissipation ability and is substantially immune from the problems of excessive heat build-up and uneven heat dissipation. This helps optimize performance and reliability of the 3D IC module.
It is to be noted that the embodiments disclosed herein are described in a progressive manner with the description of each embodiment focusing on its differences from others. Reference can be made between the embodiments for their identical or similar parts as appropriate.
While the invention has been described above with reference to several preferred embodiments, it is not intended to be limited to these embodiments in any way. In light of the teachings hereinabove, any person of skill in the art may make various possible variations and changes to the disclosed embodiments without departing from the scope of the invention. Accordingly, any and all such simple variations, equivalent alternatives and modifications made to the foregoing embodiments without departing from the scope of the invention are intended to fall within the scope thereof.
| Number | Date | Country | Kind |
|---|---|---|---|
| 202110455072.5 | Apr 2021 | CN | national |
| Filing Document | Filing Date | Country | Kind |
|---|---|---|---|
| PCT/CN2021/097007 | 5/28/2021 | WO |
