The present invention relates to semiconductor device manufacturing techniques, specifically fabrication of through silicon vias (TSVs) with multiple diameters.
In the microelectronics industry, packaging density continuously increases in order to accommodate more electronic devices into a package. In this regard, three-dimensional (3D) stacking technology of wafers and/or chips substantially contributes to the device integration process. Typically, a semiconductor wafer includes several layers of integrated circuitry (e.g., processors, programmable devices, memory devices, etc.) built on a silicon substrate. A wafer may be cut into a number of portions to define chips. A top layer of such a chip may be connected to a bottom layer of another such chip by means of through silicon interconnects or vias. In order to form a 3D integrated circuit (IC) stack, two or more chips or wafers are placed on top of one other and bonded.
Previous methods for electrically connecting the stacked chips or wafers used vias that consumed geometric space on the 3D IC by connecting multiple vias of a single diameter utilizing additional wiring levels. The formation of TSVs with complex shapes, such as multiple diameters in a single TSV, has used inefficient fabrication methods utilizing additional mask layers and patterning steps, which adds cost, complexity, and process time to the manufacturing process.
3D wafer stacking technology offers a number of potential benefits, including, for example, improved form factors, lower costs, enhanced performance, and greater integration through system-on-chip (SOC) solutions. In addition, the 3D wafer stacking technology may provide other functionality to the chip. For instance, after being formed, the 3D wafer stack may be diced into stacked dies or chips, with each stacked chip having multiple tiers (i.e., layers) of integrated circuitry. SOC architectures formed by 3D wafer stacking can enable high bandwidth connectivity of products such as, for example, logic circuitry and dynamic random access memory (DRAM), that otherwise have incompatible process flows. At present, there are many applications for 3D wafer stacking technology, including high performance processing devices, video and graphics processors, high density and high bandwidth memory chips, and other SOC solutions.
According to one embodiment of the present invention, a method includes patterning a photoresist layer on a substrate of a structure, removing a first portion of the photoresist layer to expose a first area of the substrate, etching the first area to form a cavity having a first depth, removing a second portion of the photoresist to expose an additional area of the substrate, and etching the cavity to expose a first conductor in the structure and the additional area to expose a second conductor in the structure.
An alternate exemplary method includes patterning a photoresist layer on a substrate of a structure, the photoresist layer defining an opening having a first area, etching to form a cavity having a first depth in the structure partially defined by the first area, depositing a spacer material along sidewalls of the cavity to define an opening having a second area, and etching to increase the depth of a portion of the cavity in the structure to expose a first conductor and a second conductor in the structure.
Additional features and advantages are realized through the techniques of the present invention. Other embodiments and aspects of the invention are described in detail herein and are considered a part of the claimed invention. For a better understanding of the invention with the advantages and the features, refer to the description and to the drawings.
The subject matter which is regarded as the invention is particularly pointed out and distinctly claimed in the claims at the conclusion of the specification. The drawings are not necessarily drawn to scale. The forgoing and other features, and advantages of the invention are apparent from the following detailed description taken in conjunction with the accompanying drawings in which:
The
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” and/or “comprising,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, element components, and/or groups thereof.
The description is presented for purposes of illustration, but is not intended to be exhaustive or to limit the invention in the form disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the invention.
The diagrams depicted herein are just examples. There may be many variations to the structure or the steps (or operations) described therein without departing from the spirit of the invention. For instance, the steps may be performed in a differing order or steps may be added, deleted or modified. All of these variations are considered a part of the claimed invention.
While the preferred embodiment to the invention had been described, it will be understood that those skilled in the art, both now and in the future, may make various improvements and enhancements which fall within the scope of the claims which follow. These claims should be construed to maintain the proper protection for the invention first described.
Number | Name | Date | Kind |
---|---|---|---|
5915167 | Leedy | Jun 1999 | A |
5937324 | Abercrombie et al. | Aug 1999 | A |
6133640 | Leedy | Oct 2000 | A |
6208545 | Leedy | Mar 2001 | B1 |
6500755 | Dakshina-Murthy et al. | Dec 2002 | B2 |
6551857 | Leedy | Apr 2003 | B2 |
6563224 | Leedy | May 2003 | B2 |
6632706 | Leedy | Oct 2003 | B1 |
6664500 | Wilbur et al. | Dec 2003 | B2 |
6790782 | Yang et al. | Sep 2004 | B1 |
6808942 | Patel et al. | Oct 2004 | B1 |
6858361 | Mui et al. | Feb 2005 | B2 |
6900139 | Dakshina-Murthy et al. | May 2005 | B1 |
6924088 | Mui et al. | Aug 2005 | B2 |
6949830 | Owada et al. | Sep 2005 | B2 |
6953722 | Seidl et al. | Oct 2005 | B2 |
7041434 | Raebiger et al. | May 2006 | B2 |
7081408 | Lane et al. | Jul 2006 | B2 |
7132340 | Sadra et al. | Nov 2006 | B2 |
7138295 | Leedy | Nov 2006 | B2 |
7151055 | Aminpur et al. | Dec 2006 | B2 |
7176126 | Oh et al. | Feb 2007 | B2 |
7193239 | Leedy | Mar 2007 | B2 |
7320927 | DeLoach et al. | Jan 2008 | B2 |
7402515 | Arana et al. | Jul 2008 | B2 |
7453150 | McDonald | Nov 2008 | B1 |
7474004 | Leedy | Jan 2009 | B2 |
7504732 | Leedy | Mar 2009 | B2 |
7538032 | Borwick et al. | May 2009 | B2 |
7705466 | Leedy | Apr 2010 | B2 |
20020132465 | Leedy | Sep 2002 | A1 |
20030173608 | Leedy | Sep 2003 | A1 |
20070042599 | Tsui et al. | Feb 2007 | A1 |
20070045779 | Hiatt | Mar 2007 | A1 |
20070096312 | Humpston et al. | May 2007 | A1 |
20070138562 | Trezza | Jun 2007 | A1 |
20070182014 | Usami et al. | Aug 2007 | A1 |
20080153187 | Luo et al. | Jun 2008 | A1 |
20090014843 | Kawashita et al. | Jan 2009 | A1 |
20090067210 | Leedy | Mar 2009 | A1 |
20090174082 | Leedy | Jul 2009 | A1 |
20090175104 | Leedy | Jul 2009 | A1 |
20090218700 | Leedy | Sep 2009 | A1 |
20090219742 | Leedy | Sep 2009 | A1 |
20090219743 | Leedy | Sep 2009 | A1 |
20090219744 | Leedy | Sep 2009 | A1 |
20090219772 | Leedy | Sep 2009 | A1 |
20090230501 | Leedy | Sep 2009 | A1 |
20100171224 | Leedy | Jul 2010 | A1 |
20100171225 | Leedy | Jul 2010 | A1 |
20100172197 | Leedy | Jul 2010 | A1 |
20100173453 | Leedy | Jul 2010 | A1 |
20110076845 | Tsai et al. | Mar 2011 | A1 |
Number | Date | Country |
---|---|---|
1268925 | Oct 2000 | CN |
1525485 | Sep 2004 | CN |
101188235 | May 2008 | CN |
0975472 | Feb 2000 | EP |
1986233 | Oct 2008 | EP |
2008028407 | Feb 2008 | JP |
200516033 | May 2008 | JP |
2008166831 | Jul 2008 | JP |
2008166832 | Jul 2008 | JP |
2008172254 | Jul 2008 | JP |
2009032992 | Feb 2009 | JP |
1020010005983 | Jan 2001 | KR |
1020050107819 | Nov 2005 | KR |
412854 | Nov 2000 | TW |
Entry |
---|
English Abstract of JP2009032992(A) data supplied from the esp@cenet database Worldwide. |
Number | Date | Country | |
---|---|---|---|
20110171582 A1 | Jul 2011 | US |