Three-dimensional package and method of making the same

Abstract

The present invention relates to a three-dimensional package and a method of making the same. The method comprises: (a) providing a wafer; (b) forming at least one blind hole in the wafer; (c) forming an isolation layer on the side wall of the blind hole; (d) forming a conductive layer on the isolation layer; (e) forming a dry film on the conductive layer; (f) filling the blind hole with a solder; (g) removing the dry film; (h) patterning the conductive layer; (i) removing a part of the lower surface of the wafer and a part of the isolation layer, so as to expose a part of the conductive layer; (j) stacking a plurality of the wafers, and performing a reflow process; and (k) cutting the stacked wafers, so as to form a plurality of three-dimensional packages. As such, the lower end of the conductive layer is inserted into the solder of the lower wafer, so as to enhance the joint between the conductive layer and the solder, and effectively reduce the overall height of the three-dimensional packages after joining.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows a schematic view of the three-dimensional package before reflow disclosed in U.S. Pat. No. 4,499,655;

FIG. 2 shows a schematic view of the three-dimensional package after reflow disclosed in U.S. Pat. No. 4,499,655;

FIG. 3 shows a schematic flow chart of the method for making a three-dimensional package according to the first embodiment of the present invention;

FIGS. 4 to 17 show the schematic views of each step of the method of making a three-dimensional package according to the first embodiment of the present invention;

FIG. 18 shows a schematic flow chart of the method for making a three-dimensional package according to the second embodiment of the present invention;

FIGS. 19 to 21 show the schematic views of a part of the steps of the method for making a three-dimensional package according to the second embodiment of the present invention; and

FIG. 22 shows a cross-sectional view of the three-dimensional package according to the present invention.

Claims

1. A method of making a three-dimensional package, comprising the following steps: (a) providing a wafer, having a first surface and a second surface, the first surface having at least one pad and a protection layer exposing the pad;(b) forming at least one blind hole on the first surface of the wafer;(c) forming an isolation layer on the side wall of the blind hole;(d) forming a conductive layer covering the pad, the protection layer and the isolation layer;(e) forming a dry film on the conductive layer, the dry film having an opening at the position corresponding to the blind hole;(f) filling the blind hole with a solder;(g) removing the dry film;(h) patterning the conductive layer;(i) removing a part of the second surface of the wafer and a part of the isolation layer, so as to expose a part of the conductive layer;(j) stacking a plurality of the wafers, and performing a reflow process; and(k) cutting the stacked wafers, so as to form a plurality of three-dimensional packages.

2. The method according to claim 1, wherein the blind hole is disposed beside the pad.

3. The method according to claim 1, wherein the blind hole penetrates the pad.

4. The method according to claim 1, wherein in the step (f) the blind hole is filled with the solder by plating.

5. The method according to claim 1, further comprising a step of forming a passivation layer on the conductive layer to protect the conductive layer after the step (h).

6. The method according to claim 1, wherein in the step (i) a part of the second surface of the wafer and a part of the isolation layer are etched, so as to expose a part of the conductive layer.

7. The method according to claim 1, wherein the step (i) comprises: (i1) grinding the second surface of the wafer; and(i2) etching a part of the second surface of the wafer and a part of the isolation layer, so as to expose a part of the conductive layer.

8. The method according to claim 1, further comprising a step of forming a barrier layer covering the exposed conductive layer after the step (i).

9. The method according to claim 1, further comprising a step of forming a lower solder connected to the exposed conductive layer after the step (i).

10. The method according to claim 1, further comprising a step of forming at least one solder ball below the three-dimensional package structure after the step (k).

11. A method of making a three-dimensional package, comprising the following steps: (a) providing a wafer, having a first surface and a second surface, the first surface having at least one pad and a protection layer exposing the pad;(b) forming at least one blind hole on the first surface of the wafer;(c) forming an isolation layer on the side wall of the blind hole;(d) forming a conductive layer covering the pad, the protection layer and the isolation layer;(e) forming a dry film on the conductive layer, the dry film having an opening at the position corresponding to the blind hole;(f) filling the blind hole with a solder;(g) removing the dry film;(h) patterning the conductive layer;(i) removing a part of the second surface of the wafer and a part of the isolation layer, so as to expose a part of the conductive layer;(j) cutting the wafer to form a plurality of units; and(k) stacking the units, and performing the reflow process, so as to form a plurality of three-dimensional packages.

12. The method according to claim 11, wherein the blind hole is disposed beside the pad.

13. The method according to claim 11, wherein the blind hole penetrates the pad.

14. The method according to claim 11, wherein in the step (f) the blind hole is filled with the solder by plating.

15. The method according to claim 11, further comprising a step of forming a passivation layer on the conductive layer to protect the patterning conductive layer after the step (h).

16. The method according to claim 11, wherein in the step (i) a part of the second surface of the wafer and a part of the isolation layer are etched, so as to expose a part of the conductive layer.

17. The method according to claim 11, wherein the step (i) comprises: (i1) grinding the second surface of the wafer; and(i2) etching a part of the second surface of the wafer and a part of the isolation layer, so as to expose a part of the conductive layer.

18. The method according to claim 11, further comprising a step of forming a barrier layer covering the exposed conductive layer after the step (i).

19. The method according to claim 11, further comprising a step of forming a lower solder connected to the exposed conductive layer after the step (i).

20. The method according to claim 11, further comprising a step of forming at least one solder ball below the three-dimensional package structure after the step (k).