Patent Application
20230116440
The present invention relates to the electrical, electronic, and computer arts, and more specifically, to sub-10 nanometer process nodes.
As semiconductor fabrication continues a trend toward smaller process dimensions, structural imperfections are becoming increasingly important in the performance of semiconductor products. Materials begin to be selected not for their bulk properties, but rather for their tolerance of imperfections at nanometer and angstrom scales. A salient example is the burgeoning use of “alternative metals” in semiconductor circuit designs. Although copper (Cu) has long been the favorite for integrated circuits, due to its very high bulk conductivity and lower cost than silver, imperfect line or via profiles at the smaller modern process dimensions can introduce electron scattering effects that detract from conductivity at the nanoscale.
Conductivity losses due to electron scattering are driven by structural variations or imperfections (roughness) on the order of or smaller than the mean free path length of the conductive material. Alternative metals, such as ruthenium (Ru), cobalt (Co), vanadium (Va), iridium (Ir), rhodium (Rh), molybdenum (Mo), or nickel (Ni) all have shorter mean free path lengths than copper and, accordingly, exhibit less electron scattering in response to imperfections at nanoscale. As a result, in modern chip designs, these and similar alternative metals may be favored over copper due to their better performance in real fabricated circuits (despite the better performance of copper in as-designed circuits).
Principles of the invention provide techniques for a top via structure made with a bi-layer template. In one aspect, an exemplary semiconductor structure, according to an aspect of the invention, includes a substrate defining a first trench; a first refractory metal liner coating the first trench; a heavy metal liner coating the first refractory metal liner; a copper structure filling the heavy metal liner; a generally planar capping dielectric layer on top of the substrate and the copper structure; a low-k dielectric layer on top of the capping dielectric layer; and a titanium nitride (TiN) layer on top of the low-k dielectric layer.
According to another aspect, an exemplary semiconductor structure includes a substrate defining a first trench; a first refractory metal liner coating the first trench; a heavy metal liner coating the first refractory metal liner; a copper structure filling the first trench over the heavy metal liner; a generally planar capping dielectric layer on top of the substrate and the copper structure; a low-k dielectric layer on top of the capping dielectric layer, wherein the low-k dielectric layer defines a second trench; a second refractory metal liner coating the second trench; a metal line filling the second refractory metal liner; and a metal via protruding from the metal line.
Another aspect provides an exemplary method for fabricating a semiconductor structure. The method includes obtaining a precursor structure. The precursor structure includes a substrate; a refractory metal liner coating a trench in the substrate; a heavy metal liner coating the refractory metal liner; and a copper structure filling the heavy metal liner. The precursor structure also includes a generally planar capping dielectric layer on top of the substrate and the copper structure; a low-k dielectric layer on top of the capping dielectric layer; a titanium nitride (TiN) layer on top of the low-k dielectric layer; and an etch stop layer between the low-k dielectric layer and the TiN layer. The method also includes depositing a hard mask and photoresist on the precursor structure; patterning a trench template in the photoresist and hard mask; etching a trench from the trench template through the TiN layer and the low-k dielectric layer to the copper structure; and depositing a liner in the trench and then filling the liner with an alternative filler metal.
In view of the foregoing, techniques of the present invention can provide substantial beneficial technical effects. For example, one or more embodiments provide one or more of:
Integrated circuit using alternative metal without significant line wiggling.
Integrated circuit with reduced damage to low-k dielectric from forming metal structures.
Integrated circuit with improved (reduced) variability of metal line and via dimensions.
Some embodiments may not have these potential advantages and these potential advantages are not necessarily required of all embodiments. These and other features and advantages of the present invention will become apparent from the following detailed description of illustrative embodiments thereof, which is to be read in connection with the accompanying drawings.
In damascene-based back-end-of-line (BEOL) interconnects, the dielectric that separates the metal lines becomes mechanically weaker as the spacing between the metal lines is reduced. This weak dielectric is susceptible to wiggling/flopping over during the metallization process, particularly when alternative metals (generally having higher elastic moduli and thermal coefficients of expansion, compared to copper) are used as discussed above. We have discovered that using a high modulus template is very effective to alleviate this line wiggling issue. We consider titanium nitride (TiN) to be a good template because of its high modulus. However, replacing a TiN template with low-k dielectric, after metallization, is very challenging. In case TiN residues remain after replacing with low-k, line-to-line leakage is a significant concern.
Accordingly, we have found that it is desirable to provide a semiconductor fabrication process that combines the benefits of low-k dielectric and TiN modulus. By providing bi-layer TiN/low-k templates and associated processes, embodiments of the present invention mitigate line wiggling, reduce variability of metal dimensions in a finished product, and mitigate damage formerly caused to the low-k dielectric during etching for trenches to form metal structures.
Referring to
Referring to
At 910, produce a fifth intermediate structure 1400 (as shown in
Semiconductor device manufacturing includes various steps of device patterning processes. For example, the manufacturing of a semiconductor chip may start with, for example, a plurality of CAD (computer aided design) generated device patterns, which is then followed by effort to replicate these device patterns in a substrate. The replication process may involve the use of various exposing techniques and a variety of subtractive (etching) and/or additive (deposition) material processing procedures. For example, in a photolithographic process, a layer of photo-resist material may first be applied on top of a substrate, and then be exposed selectively according to a pre-determined device pattern or patterns. Portions of the photo-resist that are exposed to light or other ionizing radiation (e.g., ultraviolet, electron beams, X-rays, etc.) may experience some changes in their solubility to certain solutions. The photo-resist may then be developed in a developer solution, thereby removing the non-irradiated (in a negative resist) or irradiated (in a positive resist) portions of the resist layer, to create a photo-resist pattern or photo-mask. The photo-resist pattern or photo-mask may subsequently be copied or transferred to the substrate underneath the photo-resist pattern.
There are numerous techniques used by those skilled in the art to remove material at various stages of creating a semiconductor structure. As used herein, these processes are referred to generically as “etching”. For example, etching includes techniques of wet etching, dry etching, chemical oxide removal (COR) etching, and reactive ion etching (ME), which are all known techniques to remove select material(s) when forming a semiconductor structure. The Standard Clean 1 (SC1) contains a strong base, typically ammonium hydroxide, and hydrogen peroxide. The SC2 contains a strong acid such as hydrochloric acid and hydrogen peroxide. The techniques and application of etching is well understood by those skilled in the art and, as such, a more detailed description of such processes is not presented herein.
Although the overall fabrication method and the structures formed thereby are novel, certain individual processing steps required to implement the method may utilize conventional semiconductor fabrication techniques and conventional semiconductor fabrication tooling. These techniques and tooling will already be familiar to one having ordinary skill in the relevant arts given the teachings herein. Moreover, one or more of the processing steps and tooling used to fabricate semiconductor devices are also described in a number of readily available publications, including, for example: James D. Plummer et al., Silicon VLSI Technology: Fundamentals, Practice, and Modeling 1st Edition, Prentice Hall, 2001 and P. H. Holloway et al., Handbook of Compound Semiconductors: Growth, Processing, Characterization, and Devices, Cambridge University Press, 2008, which are both hereby incorporated by reference herein. It is emphasized that while some individual processing steps are set forth herein, those steps are merely illustrative, and one skilled in the art may be familiar with several equally suitable alternatives that would be applicable.
It is to be appreciated that the various layers and/or regions shown in the accompanying figures may not be drawn to scale. Furthermore, one or more semiconductor layers of a type commonly used in such integrated circuit devices may not be explicitly shown in a given figure for ease of explanation. This does not imply that the semiconductor layer(s) not explicitly shown are omitted in the actual integrated circuit device.
Given the discussion thus far, it will be appreciated that, in general terms, an exemplary semiconductor structure 500, according to an aspect of the invention, includes a substrate 510 defining a first trench; a first refractory metal liner 512 coating the first trench; a heavy metal liner 514 coating the first refractory metal liner; a copper structure 516 filling the heavy metal liner; a generally planar capping dielectric layer 518 on top of the substrate and the copper structure; a low-k dielectric layer 502 on top of the capping dielectric layer; and a titanium nitride (TiN) layer 506 on top of the low-k dielectric layer.
In one or more embodiments, the semiconductor structure 500 also includes an etch stop layer 504 between the low-k dielectric layer and the TiN layer.
In one or more embodiments, the semiconductor structure 500 also includes a hard mask 1002 on the TiN layer; and a photoresist 1004 on the hard mask. In one or more embodiments, the photoresist and the hard mask define a trench template 1102. In one or more embodiments, a trench 1202 extends from the trench template through the TiN layer, the low-k dielectric layer, and the capping dielectric layer to the copper structure.
In one or more embodiments, the semiconductor structure 500 also includes alternative metal 1304 filling the trench.
In one or more embodiments, the semiconductor structure 500 also includes a hard mask 1502 formed atop the alternative metal; and photoresist 1504 deposited atop the hard mask.
According to another aspect, an exemplary semiconductor structure 800 includes a substrate 510 defining a first trench; a first refractory metal liner 512 coating the first trench; a heavy metal liner 514 coating the first refractory metal liner; a copper structure 516 filling the first trench over the heavy metal liner; a generally planar capping dielectric layer 518 on top of the substrate and the copper structure; a low-k dielectric layer 502 on top of the capping dielectric layer, wherein the low-k dielectric layer defines a second trench; a second refractory metal liner 804 coating the second trench; a metal line 802 filling the second refractory metal liner; and a metal via 806 protruding from the metal line.
In one or more embodiments, the semiconductor structure 800 also includes a hard mask 1502 atop the metal via.
In one or more embodiments, the semiconductor structure 800 also includes an etch stop layer 504 atop the low-k dielectric layer.
In one or more embodiments, the refractory metal liner coats the metal via.
Another aspect provides an exemplary method 900 for fabricating a semiconductor structure. The method 900 includes, at 901, obtaining a precursor structure 500. The precursor structure 500 includes a substrate 510; a refractory metal liner 512 coating a trench in the substrate; 514 a heavy metal liner coating the refractory metal liner; and a copper structure 516 filling the heavy metal liner. The precursor structure 500 also includes a generally planar capping dielectric layer 518 on top of the substrate and the copper structure; a low-k dielectric layer 502 on top of the capping dielectric layer; a titanium nitride (TiN) layer 506 on top of the low-k dielectric layer; and an etch stop layer 504 between the low-k dielectric layer and the TiN layer. The method 900 also includes, at 902, depositing a hard mask and photoresist on the precursor structure; at 904, patterning a trench template in the photoresist and hard mask; at 906, etching a trench from the trench template through the TiN layer and the low-k dielectric layer to the copper structure; and, at 908, depositing a liner in the trench and then filling the liner with an alternative filler metal.
In one or more embodiments, the method 900 also includes, at 910 performing chemical mechanical planarization.
In one or more embodiments, the method 900 also includes, at 912 patterning vias with a hard mask and a photoresist.
In one or more embodiments, the method 900 also includes, at 914 removing the TiN layer.
In one or more embodiments, the method 900 also includes, at 916 removing portions of the liner above the etch stop layer.
In one or more embodiments, the method 900 also includes, at 918 etching the filler metal to form vias and lines.
In one or more embodiments, the method 900 also includes, at 920 removing the etch stop layer; and at 922 removing the via etch hard mask.
In one or more embodiments, the method 900 also includes, at 924 filling with low-k dielectric around the vias, wherein the low-k dielectric contacts sides of the vias.
In one or more embodiments, the method 900 also includes, at 926 producing a finished semiconductor structure by chemical mechanical polishing.
The descriptions of the various embodiments of the present invention have been presented for purposes of illustration, but are not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein was chosen to best explain the principles of the embodiments, the practical application or technical improvement over technologies found in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.
