Patent Application
20240234516
The present application relates to manufacturing of semiconductor integrated circuits. More particularly, it relates to method of forming gate stack of semiconductor transistor for reliability improvement and the structure formed thereby.
In forming semiconductor transistors, in particular in forming gate stack of the semiconductor transistors, a high-k dielectric layer is first formed on top of a silicon channel region of the transistors and the structure is then subjected to a thermal anneal process such as a laser spike anneal (LSA) or a rapid thermal anneal (RTA) process. However, the anneal process, while being a necessary process step in forming the gate stack, has been found to inadvertently and frequently cause negative bias temperature instability (NBTI) of the transistors. The NBTI is likely due to the fact that the anneal process also has caused nitrogen diffusion into the high-k dielectric layer that surrounds the silicon channel region of the transistors. NBTI is one of the key reliability concerns that limit the circuit lifetime and performance boost.
Embodiments of present invention provide a transistor structure. The transistor structure includes a channel region of a gate structure of a transistor; a high-k dielectric layer above the channel region; and a silicon-nitride layer directly on top of the high-k dielectric layer, where the high-k dielectric layer is substantially free of nitrogen.
In one embodiment, the channel region is a silicon nanosheet; the high-k dielectric layer surrounds the silicon nanosheet to form a gate-all-around structure; and the silicon-nitride layer surrounds the high-k dielectric layer.
In another embodiment, the high-k dielectric layer is a first high-k dielectric layer, and the transistor structure further includes a second high-k dielectric layer, where the second high-k dielectric layer is above and surrounds the silicon-nitride layer, the first high-k dielectric layer, and the silicon nanosheet.
In yet another embodiment, the first high-k dielectric layer has a first thickness and the second high-k dielectric layer has a second thickness, wherein the first thickness is larger than the second thickness.
In one more embodiment, the second high-k dielectric layer includes nitrogen to have a nitrogen concentration level that is higher than a nitrogen concentration level of the first high-k dielectric layer.
In one embodiment, the silicon-nitride layer is a nitrogen-containing monolayer transformed from a silicon monolayer after the silicon monolayer has trapped nitrogen during a thermal anneal process of the gate structure.
Embodiments of present invention provide a method of forming a gate structure of a transistor. The method includes forming a channel region of the gate structure; forming a first set of spacers at a first end of the channel region and a second set of spacers at a second end of the channel region; forming a high-k dielectric layer covering the channel region between the first set of spacers and the second set of spacers; forming a silicon monolayer covering the high-k dielectric layer; forming a sacrificial metal layer covering the silicon monolayer; forming a sacrificial silicon layer covering the sacrificial metal layer; subjecting the gate structure to a thermal anneal process, thereby transforming the silicon monolayer into a nitrogen-containing monolayer; and removing the sacrificial silicon layer and the sacrificial metal layer.
In one embodiment, the method further includes forming a gate metal covering the nitrogen-containing monolayer to form the gate structure. In another embodiment, the method further includes removing the nitrogen-containing monolayer. In yet another embodiment, the method further includes forming a gate metal covering the high-k dielectric layer to form the gate structure.
In one embodiment, the high-k dielectric layer is a first high-k dielectric layer, the method further includes forming a second high-k dielectric layer covering the silicon monolayer before forming the sacrificial metal layer and includes forming a gate metal covering the second high-k dielectric layer to form the gate structure.
In one embodiment, the sacrificial metal layer is a nitrogen scavenging layer. In another embodiment, forming the silicon monolayer includes depositing the silicon monolayer through an atomic layer deposition process. In yet another embodiment, subjecting the gate structure to the thermal anneal process includes subjecting the gate structure to an environment of high temperature ranging from about 700 degrees C. to about 1300 degrees C.
The present invention will be understood and appreciated more fully from the following detailed description of embodiments of present invention, taken in conjunction with accompanying drawings of which:
It will be appreciated that for simplicity and clarity purpose, elements shown in the drawings have not necessarily been drawn to scale. Further, and if applicable, in various functional block diagrams, two connected devices and/or elements may not necessarily be illustrated as being connected. In some other instances, grouping of certain elements in a functional block diagram may be solely for the purpose of description and may not necessarily imply that they are in a single physical entity, or they are embodied in a single physical entity.
In the below detailed description and the accompanying drawings, it is to be understood that various layers, structures, and regions shown in the drawings are both demonstrative and schematic illustrations thereof that are not drawn to scale. In addition, for the ease of explanation, one or more layers, structures, and regions of a type commonly used to form semiconductor devices or structures may not be explicitly shown in a given illustration or drawing. This does not imply that any layers, structures, and regions not explicitly shown are omitted from the actual semiconductor structures. Furthermore, it is to be understood that the embodiments discussed herein are not limited to the particular materials, features, and processing steps shown and described herein. In particular, with respect to semiconductor processing steps, it is to be emphasized that the descriptions provided herein are not intended to encompass all of the processing steps that may be required to form a functional semiconductor integrated circuit device. Rather, certain processing steps that are commonly used in forming semiconductor devices, such as, for example, wet cleaning and annealing steps, are purposefully not described herein for economy of description.
It is to be understood that the terms “about” or “substantially” as used herein with regard to thicknesses, widths, percentages, ranges, etc., are meant to denote being close or approximate to, but not exactly. For example, the term “about” or “substantially” as used herein implies that a small margin of error may be present such as, by way of example only, 1% or less than the stated amount. Likewise, the terms “on”, “over”, or “on top of” that are used herein to describe a positional relationship between two layers or structures are intended to be broadly construed and should not be interpreted as precluding the presence of one or more intervening layers or structures.
To provide spatial context to different structural orientations of the semiconductor structures shown in the drawings, XYZ Cartesian coordinates may be provided in some of the drawings. The terms “vertical” or “vertical direction” or “vertical height” as used herein denote a Z-direction of the Cartesian coordinates shown in the drawings, and the terms “horizontal” or “horizontal direction” or “lateral direction” as used herein denote an X-direction and/or a Y-direction of the Cartesian coordinates shown in the drawings.
Moreover, although various reference numerals may be used across different drawings, the same or similar reference numbers are used throughout the drawings to denote the same or similar features, elements, or structures, and thus detailed explanations of the same or similar features, elements, or structures may not be repeated for each of the drawings for economy of description. Labelling for the same or similar elements in some drawings may be omitted as well in order not to overcrowd the drawings.
More particularly, embodiments of present invention provide forming a nanosheet 100 such as a silicon (Si) nanosheet, a germanium (Ge) nanosheet, a silicon-germanium (SiGe) nanosheet, or other types of suitable semiconductor materials. In
Embodiments of present invention provide forming a first set of spacers 101 at a first end 100A of the nanosheet 100; a second set of spacers 102 at a second end 100B of the nanosheet 100; and a high-k dielectric layer 110 surrounding the nanosheet 100 between the first set of spacers 101 and the second set of spacers 102, thereby forming a gate-all-around structure. The first set of spacers 101 and the second set of spacers 102 may include one or more spacers. The first set of spacers 101 and the second set of spacers 102 may be made of a dielectric material such as silicon-nitride (SiN) and the high-k dielectric layer 110 may be a layer of hafnium-oxide (HfO2) that has a dielectric constant k larger than, for example, 4. The high-k dielectric layer 110 may be formed substantially nitrogen-free through a chemical vapor deposition (CVD) process, an atomic layer deposition (ALD) process, and/or a physical vapor deposition (PVD) process. Forming a high-k dielectric layer 110 of substantially nitrogen-free helps improve performance reliability of the transistor structure 10.
According to one embodiment, in order to keep the high-k dielectric layer 110 substantially nitrogen-free during subsequent process steps, a nitrogen trapping layer may be formed to surround and protect the high-k dielectric layer 110. For example, the nitrogen trapping layer may serve to capture or trap nitrogen during a thermal anneal process by preventing nitrogen from diffusing into the high-k dielectric layer 110, which would otherwise be detrimental to the performance of the transistor structure 10 in terms of reliability.
More specifically, embodiments of present invention provide forming a silicon monolayer 120, as a nitrogen trapping layer, to surround the high-k dielectric layer 110. The silicon monolayer 120, as the name suggests, may have a thickness as thin as around 1Å to 10Å, and may be formed through an ALD, a CVD, or a PVD process directly above, on top of, and surrounding the high-k dielectric layer 110, between the first set of spacers 101 and the second set of spacers 102.
After forming the silicon monolayer 120, embodiments of present invention provide forming a sacrificial metal layer 130 on top of and surrounding the silicon monolayer 120 and forming a sacrificial silicon layer 140 on top of and surrounding the sacrificial metal layer 130. The sacrificial metal layer 130 may be a nitrogen scavenging layer formed of thermally stable metal alloy including, for example, titanium-nitride (TiN), titanium-carbide (TiC), tantalum-nitride (TaN), or tantalum-carbide (TaC). The sacrificial metal layer 130 may be formed to have a thickness ranging from about 1 nm to 5 nm. In the meantime, the sacrificial silicon layer 140 may be a layer of amorphous silicon or poly-crystalline silicon.
According to embodiments of present invention, during the LSA process, the silicon monolayer 120 may capture or trap elements of nitrogen such as, for example, nitrogen from an ambient environment or existing surrounding films and/or layers that contains nitrogen, thereby preventing nitrogen from diffusing into the high-k dielectric layer 110 underneath the silicon monolayer 120. In other words, the high-k dielectric layer 110 may remain substantially nitrogen-free, which helps improve or maintain performance reliability of the transistor structure 10. In the meantime, by capturing or trapping nitrogen, the silicon monolayer 120 may be transformed into a silicon-nitride layer 121, as being demonstratively illustrated in
Following the LSA process, a millisecond anneal process may optionally be used to further treat the transistor structure 10. The millisecond anneal process may be, for example, a laser anneal or a flash lamp anneal process, and may last for a duration of about 1 to 100 milliseconds as part of a process of forming the gate structure 10.
More specifically, embodiments of present invention provide forming a nanosheet 100 that serves as a channel region of a gate structure of the transistor structure 20; forming a first set of spacers 101 at a first end 100A of the nanosheet 100; a second set of spacers 102 at a second end 100B of the nanosheet 100; and a first high-k dielectric layer 210 on top of and surrounding the nanosheet 100 between the first set of spacers 101 and the second set of spacers 102. The first high-k dielectric layer 210 may be formed substantially nitrogen-free through a CVD, an ALD, or a PVD process in a nitrogen-free environment such as, for example, a nitrogen-free chamber. Forming a first high-k dielectric layer 210 of substantially nitrogen-free helps improve performance reliability of the transistor structure 20.
According to one embodiment, a silicon monolayer 220, working as a nitrogen trapping layer, is then formed to surround the first high-k dielectric layer 210. The nitrogen trapping layer serves to capture or trap nitrogen during a subsequent thermal anneal process such that it prevents nitrogen from diffusing into the first high-k dielectric layer 210. The silicon monolayer 220, may have a thickness as thin as around 1Å to 10Å, and may be formed through an ALD, a CVD, or a PVD process directly above, on top of, and surrounding the first high-k dielectric layer 210.
According to one embodiment, after forming the silicon monolayer 220, a second high-k dielectric layer 211 may be formed on top of the silicon monolayer 220. In other words, the silicon monolayer 220 may be sandwiched between the first and second high-k dielectric layers 210 and 211. Generally, it is preferable to place the silicon monolayer 220 further away from the channel region of the nanosheet 100 such that after trapping nitrogen, the silicon monolayer 220, if not being removed, will have less impact on device reliability performance. Therefore, in one embodiment, the second high-k dielectric layer 211 may have a thickness that is thinner than a thickness of the first high-k dielectric layer 210.
Embodiments of present invention further provide forming a sacrificial metal layer 230, on top of the second high-k dielectric layer 211 and a sacrificial silicon layer 240 on top of the sacrificial metal layer 230. The sacrificial metal layer 230 may be a layer of TiN, TiC, TaN, or TaC material and may function as a nitrogen scavenging layer. The sacrificial silicon layer 240 may be a layer of amorphous silicon or poly-crystalline silicon.
More specifically, embodiments of present invention provide forming a nanosheet 100 that serves as a channel region of a gate structure of the transistor structure 30; forming a first set of spacers 101 at a first end 100A of the nanosheet 100; a second set of spacers 102 at a second end 100B of the nanosheet 100; and a high-k dielectric layer 310 on top of and surrounding the nanosheet 100 between the first set of spacers 101 and the second set of spacers 102. The high-k dielectric layer 310 may be formed substantially nitrogen-free through a CVD, an ALD, or a PVD process in a nitrogen-free environment such as, for example, a nitrogen-free chamber. Forming a high-k dielectric layer 310 of substantially nitrogen-free helps improve performance reliability of the transistor structure 30.
According to one embodiment, a first sacrificial metal layer 320 may be formed to surround the high-k dielectric layer 310 and a nitrogen trapping layer 330 may then be formed to surround the first sacrificial metal layer 320. In one embodiment, the nitrogen trapping layer 330 may be a metal oxide layer, such as a titanium-oxide (TiO) layer, or a silicon monolayer. The nitrogen trapping layer 330 serves to capture or trap nitrogen during a subsequent thermal anneal process such that it prevents nitrogen from diffusing into the high-k dielectric layer 310. The nitrogen trapping layer 330 may have a thickness around 1Å to 30Å, and may be formed through an ALD, a CVD, or a PVD process directly above, on top of, and surrounding the first sacrificial metal layer 320.
Next, a second sacrificial metal layer 321 may be formed on top of the nitrogen trapping layer 330. By doing so, the nitrogen trapping layer 330 becomes sandwiched between the first and second sacrificial metal layers 320 and 321. The first and second sacrificial metal layers 320 and 321 may be formed to have a same or different thicknesses. In one instance, the thickness of the first sacrificial metal layer 320 is substantially close to zero and the transistor structure 30 is substantially identical to the transistor structure 10. After forming the second sacrificial metal layer 321, a sacrificial silicon layer 340 may be formed on top of and surrounding the second sacrificial metal layer 321. The first and second sacrificial metal layers 320 and 321 may be layers of TiN, TiC, TaN, or TaC and may both be nitrogen scavenging layers. The sacrificial silicon layer 340 may be a layer of amorphous silicon or poly-crystalline silicon. The sacrificial silicon layer 340 may also be replaced with a metal oxide layer to trap nitrogen.
It is to be understood that the exemplary methods discussed herein may be readily incorporated with other semiconductor processing flows, semiconductor devices, and integrated circuits with various analog and digital circuitry or mixed-signal circuitry. In particular, integrated circuit dies can be fabricated with various devices such as field-effect transistors, bipolar transistors, metal-oxide-semiconductor transistors, diodes, capacitors, inductors, etc. An integrated circuit in accordance with the present invention can be employed in applications, hardware, and/or electronic systems. Suitable hardware and systems for implementing the invention may include, but are not limited to, personal computers, communication networks, electronic commerce systems, portable communications devices (e.g., cell phones), solid-state media storage devices, functional circuitry, etc. Systems and hardware incorporating such integrated circuits are considered part of the embodiments described herein. Given the teachings of the invention provided herein, one of ordinary skill in the art will be able to contemplate other implementations and applications of the techniques of the invention.
Accordingly, at least portions of one or more of the semiconductor structures described herein may be implemented in integrated circuits. The resulting integrated circuit chips may be distributed by the fabricator in raw wafer form (that is, as a single wafer that has multiple unpackaged chips), as a bare die, or in a packaged form. In the latter case the chip may be mounted in a single chip package (such as a plastic carrier, with leads that are affixed to a motherboard or other high-level carrier) or in a multichip package (such as a ceramic carrier that has surface interconnections and/or buried interconnections). In any case the chip may then be integrated with other chips, discrete circuit elements, and/or other signal processing devices as part of either an intermediate product, such as a motherboard, or an end product. The end product may be any product that includes integrated circuit chips, ranging from toys and other low-end applications to advanced computer products having a display, a keyboard or other input device, and a central processor.
The descriptions above have been presented for the purposes of illustration of various embodiments of present invention and they are not intended to be exhaustive and present invention are not limited to the embodiments disclosed. The terminology used herein was chosen to best explain the principles of the embodiments, practical application or technical improvement over technologies found in the marketplace, and to enable others of ordinary skill in the art to understand the embodiments disclosed herein. Many modifications, substitutions, changes, and equivalents will now occur to those of ordinary skill in the art. Such changes, modification, and/or alternative embodiments may be made without departing from the spirit of present invention and are hereby all contemplated and considered within the scope of present invention. It is, therefore, to be understood that the appended claims are intended to cover all such modifications and changes as fall within the spirit of the invention.
