Patent Application
20240088215
The present invention relates to the technical field of semiconductors, and particularly relates a trench MOSFET device and a manufacturing method therefor.
At present, with the development of semiconductor technology, power devices, as an important part of integrated circuits, are widely used in automobile electronics, communication equipment and other fields. In the prior art, unipolar power devices made of the third generation of semiconductor SiC material are mostly used as power semiconductor switching devices, and the concept of super junction and the polysilicon technology of separated trenches are mostly used to fabricate Si-based devices. At present, the main SiC power devices on the market are planar MOS and trench MOS, the concept of single trench or double trenches is mainly adopted by the trench MOS, and a gate trench and a source trench are horizontally divided into a left structure and a right structure when the concept of double trenches is adopted.
However, the concept of super junction and the polysilicon technology of separated trenches are not utilized at the same time to fabricate SiC devices in prior art, and the existing trench MOSFET devices are not compact enough in structure and have high on-resistance, which directly affects the performance of the MOSFET devices.
Therefore, how to combine the concept of super junction and the polysilicon technology of separated trenches to provide a manufacturing method for a MOSFET device with a compact structure and a low on-resistance is a problem to be urgently solved by those skilled in the art.
In view of this, the present invention provides a trench MOSFET device and a manufacturing method therefor, in which a smaller on-resistance is obtained by the concept of super junction, the Miller capacitance from a gate electrode to a drain electrode is reduced by the polysilicon technology of separated trenches, and a trench MOSFET device with a compact structure and a high primitive cell density per unit area can be produced.
To achieve the above purpose, the present invention adopts the following technical solution:
A trench MOSFET device manufacturing method, comprising:
Preferably, the step of epitaxially forming a base area on a substrate specifically comprises:
Preferably, the step of forming a P-type layer on the inner surface of the first trench specifically comprises:
Preferably, the step of forming a second trench above the first trench specifically comprises:
Preferably, the step of forming a gate structure in the second trench specifically comprises: forming a gate structure by a sacrificial oxidation process, a photolithography process, a gate oxidation process, a polysilicon filling process, a polysilicon photolithography process and an etching process, forming a gate oxide layer on the side walls and bottom of the second trench, and forming gate polysilicon in the gate oxide layer.
Preferably, the trench MOSFET device manufacturing method further comprises: forming an interlayer medium on the surface of the gate structure by depositing, forming a contact opening by etching, implanting ions to form a P+ layer, growing a metal on the upper surface of the interlayer medium as the source electrode, connecting the source electrode respectively with the source layer and the P-type body layer, wherein the P+ layer is located at the contact plane between the source electrode and the P-type body layer at the bottom of the contact opening, and forming a drain electrode after the lower surface of the substrate is ground and the backside metal is deposited.
A trench MOSFET device, comprising: the substrate, the base area, the first trench and the second trench;
The base area is located on the upper surface of the substrate, the second trench is located above the first trench, and both trenches are formed in the base area;
The P-type layer is formed on the inner surface of the first trench, and the P-type layer is filled with polysilicon.
Preferably, the base area comprises the source layer, the P-type body layer and the epitaxial layer distributed sequentially from top to bottom;
Preferably, the source polysilicon is arranged in the P-type layer;
The gate oxide layer is formed on the side walls and bottom of the second trench, and the gate polysilicon is formed in the gate oxide layer.
Preferably, trench MOSFET device further comprises: the source electrode, the P+ layer, the interlayer medium and the drain electrode;
The interlayer medium is located on the upper surface of the gate polysilicon, the P+ layer is located at the contact plane between the source electrode and the P-type body layer at the bottom of the contact opening, the source electrode is located on the upper surface of the interlayer medium, the source electrode is respectively connected with the source layer and the P-type body layer, and the drain electrode is located on the lower surface of the substrate.
It can be known from the above technical solution that compared with the prior art, the present invention provides a trench MOSFET device and a manufacturing method therefor, in which a super junction structure is formed by the P-type layer and the epitaxial layer to obtain an on-resistance smaller than that of a conventional trench structure, the Miller capacitance from a gate electrode to a drain electrode is reduced by the polysilicon technology of separated trenches, and a trench MOSFET device with a compact structure, a high primitive cell density per unit area and a high current density can be produced, which can significantly increase the power density of the device, reduce the cost and improve the reliability of the product.
To more clearly describe the technical solutions in the embodiments of the present invention or in the prior art, the drawings required to be used in the description of the embodiments or the prior art will be simply presented below. Apparently, the drawings in the following description are merely the embodiments of the present invention, and for those ordinary skilled in the art, other drawings can also be obtained according to the provided drawings without contributing creative labor.
Reference signs: 1—substrate, 2—epitaxial layer; 3—P-type body layer; 4—source layer; 5—first hard mask; 6—first trench; 7—P-type layer; 8—polysilicon; 9—second hard mask; 10—second trench; 11—gate polysilicon; 12—gate oxide layer; 13—source polysilicon; 14—interlayer medium; 15—P+ layer; 16—source electrode; 17—drain electrode.
The technical solution in the embodiments of the present invention will be clearly and fully described below in combination with the drawings in the embodiments of the present invention. Apparently, the described embodiments are merely part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments in the present invention, all other embodiments obtained by those ordinary skilled in the art without contributing creative labor will belong to the protection scope of the present invention.
As shown in
As shown in
Preferably, the substrate 1 is made of SiC material, and nitrogen or phosphorus is doped during the formation of the SiC substrate to reduce the resistivity.
Preferably, the thickness and resistivity of the epitaxial layer 2 are set according to the target voltage of a device.
As shown in
Preferably, the P-type body layer 3 is formed by implanting aluminum ions or boron ions, and is a SiC layer containing the second class of conductivity (P-type conduction); the source layer 4 is formed by implanting nitrogen ions or phosphorus ions, and is a SiC layer containing the first class of conductivity.
As shown in
Preferably, the first hard mask 5 is made of silicon dioxide.
Preferably, after the first hard mask 5 is formed, the base area is etched to form the first trench 6.
Preferably, the depth of the first trench 6 is set according to the target voltage of the device; the deeper the trench, the higher the voltage.
As shown in
Preferably, the preset angle is set according to the width and the depth of the trench and the thickness of the layer to be implanted.
As shown in
Preferably, the polysilicon 8 filled is doped with boron or other P-type doping element, thus the purpose of reducing the resistance is realized.
As shown in
As shown in
Preferably, the gate polysilicon 11 is separated from the source polysilicon 13 by the gate oxide layer 12.
As shown in
Preferably, good ohmic contact is guaranteed by the P+ layer 15.
Preferably, after the gate structure is formed, a gate contact opening and a source contact opening are formed based on a standard power device manufacturing process; the source electrode 16 is connected with the source polysilicon 13, and a gate electrode is connected with the gate polysilicon 11.
As shown in
The base area is located on the upper surface of the substrate 1, the second trench is located above the first trench, and both trenches are formed in the base area;
The P-type layer 7 is formed on the inner surface of the first trench, and the P-type layer 7 is filled with the polysilicon 8.
Preferably, the base area comprises the source layer 4, the P-type body layer 3 and the epitaxial layer 2 distributed sequentially from top to bottom;
Preferably, the trench enclosed by the P-type layer 7 is filled with the source polysilicon 13, and the source polysilicon 13 is separated from the epitaxial layer 2 by the P-type layer 7;
A gate oxide layer 12 is formed on the side walls and bottom of the second trench, and the trench enclosed by the gate oxide layer 12 is filled with the gate polysilicon 11.
Preferably, trench MOSFET device further comprises: the source electrode 16, the P+ layer 15, the interlayer medium 14 and the drain electrode 17;
The interlayer medium 14 is located on the upper surface of the gate structure, the P+ layer 15 is located at the contact plane between the source electrode 16 and the P-type body layer 3 at the bottom of the contact opening, the source electrode 16 is located on the upper surface of the interlayer medium 14, the source electrode 16 is respectively connected with the source layer 4 and the P-type body layer 3, and the drain electrode 17 is located on the lower surface of the substrate 1.
Each embodiment in the description is described in a progressive way. The difference of each embodiment from each other is the focus of explanation. The same and similar parts among all of the embodiments can be referred to each other. For a device disclosed by the embodiments, because the device corresponds to a method disclosed by the embodiments, the device is simply described. Refer to the description of the method part for the related part.
The above description of the disclosed embodiments enables those skilled in the art to realize or use the present invention. Many modifications to these embodiments will be apparent to those skilled in the art. The general principle defined herein can be realized in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to these embodiments shown herein, but will conform to the widest scope consistent with the principle and novel features disclosed herein.
| Number | Date | Country | Kind |
|---|---|---|---|
| 202310875766.3 | Jul 2023 | CN | national |
