BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 shows an embodiment of the trench step channel cell transistor of the subject invention.
FIG. 2 shows a top view of a substrate that has an active area, a shallow trench isolation structure, and a trench capacitor.
FIG. 3 is a top view showing a photoresist located on the first sacrificial oxide and partially covering the active area and shallow trench isolation structure.
FIG. 4 is a top view showing the first sacrificial oxide formed on the active area.
FIG. 5 is a top view showing the formation of an anisotropic step silicon layer.
FIG. 6 is a cross-section view showing the formation of a gate oxide.
FIG. 7 is a cross-section view showing a gate electrode deposited on the gate insulating layer.
FIG. 8 is a top view showing a formed gate electrode.
FIG. 9 is a cross-section view showing a bit contact window located on the anisotropic step silicon layer.
DESCRIPTION OF THE PREFERRED EMBODIMENT
FIG. 1 is a schematic diagram showing the related location of each element contained in a trench step channel cell transistor according to the subject invention. The trench step channel cell transistor primarily contains a step silicon layer 110 and an active area 120 in a substrate 100. The substrate 100 has a trench capacitor 170, which has a deep trench structure and comprises a first electrode 260, an insulating layer 270, a second electrode 280, and a buried strap 290.
As shown in FIG. 1, the step silicon layer 110 is located above the active area 120. The trench capacitor 170 is located in the substrate 100. The first electrode 260 is located in the substrate 100 and surrounds the lower portion of the trench capacitor 170. The insulating layer 270 is located on the sidewall and on the bottom of the trench capacitor 170. The second electrode 280 is filled in the trench capacitor 170 and sandwiches the insulating layer 270 with the first electrode 260. The buried strap 290 is located in the trench capacitor 170 and directly comes into contact with the substrate 100 such that the second electrode 280 electrically connects with the first source/drain of the transistor.
One characteristic of the subject invention lies in the step silicon layer that is an anisotropic step silicon layer. Preferably, the anisotropic step silicon layer is formed by a single orientation epitaxial growth with selectivity. The anisotropic step silicon layer not only increases the channel length formed between the source and the drain but also reduces the probability of the occurrence of leakage resulting from the punch-through phenomenon. As will be described below, one example is illustrated to describe the method for manufacturing the trench step channel cell transistor of the subject invention. The steps of the method can be respectively referred to the figures.
Referring to FIG. 1 and FIG. 2, FIG. 2 shows a top view before the anisotropic step silicon layer 110 depicted in FIG. 1 has been formed, illustrating a memory array of the subject invention. The method for manufacturing each memory unit of the subject invention first provides a substrate that has at least one trench capacitor and an active area corresponding to the trench capacitor. As shown in FIG. 1, each memory unit comprises an active area 120, a shallow trench isolation structure 160 and a trench capacitor 170. The trench capacitor 170 has a deep trench structure and comprises a collar oxide layer 150 and a buried strap 290. The collar oxide layer 150 is located on the sidewall of the trench capacitor 170. The active area 120 and the shallow trench isolation structure 160 are adjacent to each other. The trench capacitor 170 is separately arranged between the active areas 120. It should be mentioned that the manufacturing processes for forming the collar oxide layer 150, the shallow trench isolation structure 160, and the trench capacitor 170 are known technology and can be referred to in the prior art publications such as in Taiwan Patent Publication No. 1231968.
Thereafter, a first sacrificial oxide layer 190 is deposited on the substrate 100. The first sacrificial oxide has a thickness ranging from about 40 Å to about 50 Å. Then, referring to FIG. 3, a mask 180 is provided on the first sacrificial oxide layer 190, partially covering the active area 120 and the shallow trench isolation structure 160. Specifically, the mask 180 exposes a portion of the first sacrificial oxide layer 190 that covers a first predetermined area 120a of the active area 120, and the unexposed portion of the first sacrificial oxide layer 190 covers a second predetermined area 120b of the active area 120. The second predetermined area 120b connects with the corresponding trench capacitor 170.
Referring to FIG. 3 in combination with FIG. 4, the mask 180 depicted therein is a patterned mask. A portion of the first sacrificial oxide 190 exposed by the mask 180 is etched to expose the first predetermined area 120a on the active area 120. After, the patterned mask 180 is removed to expose the remained portion of the first sacrificial oxide 190 that covers the second predetermined area 120b on the active area 120.
FIG. 5 shows the use of the remained portion of the first sacrificial oxide layer 190 as a mask to form an anisotropic step silicon layer 110 on the first predetermined area 120a by selective growth. Preferably, the anisotropic step silicon layer is a single orientation silicon layer formed with selective epitaxial growth. Afterwards, the first sacrificial oxide layer 190 is removed and a second sacrificial oxide layer (not shown) is deposited on the substrate 100. The second sacrificial oxide layer is then used as a mask for implanting ions into the active area 120 of substrate 100 and the step silicon layer 110 to adjust the working voltage of area 120. After the ion implantation, the second sacrificial oxide layer is removed.
In FIG. 6, after removing the second sacrificial oxide layer, a gate insulating layer 200 is deposited onto the substrate 100. The gate insulating layer 200 can be formed by depositing a gate dielectric layer. The material of the dielectric layer is selected from a group consisting of silicon dioxide, silicon nitride, silicon oxynitride, and a combination thereof.
Referring to FIG. 7, a gate electrode 240 is formed on the gate insulating layer 200 to cover the active area 120 and step silicon layer 110. In this embodiment, the step of forming the gate electrode 240 comprises sequentially depositing a polysilicon layer 210, a tungsten silicide layer 220 and a silicon nitride layer 230, and thus forms the cross-section view depicted in FIG. 7. Afterwards, a gate electrode 240 is finally formed above a portion of the active area 120 and a portion of the step silicon layer 110 by using proper developing and etching processes. A configuration of thus formed gate electrode 240 is shown in FIGS. 8 and 9, with FIG. 8 representing the top view. Nonetheless, the abovementioned is a preferred embodiment only of the subject invention, but is not intended to limit the composition of the gate electrode 240 and the arrangement order of the metal layer(s) thereof.
After forming a gate electrode 240, a spacer is formed. That is, a pair of insulating spacers 300 are formed on the sidewall of the gate electrode 240. Afterwards, an ion doping process is conducted to form a first source/drain 130 in the active area 120 and a second source/drain 140 in the step silicon layer 110. The first source/drain 130 electrically connects with the trench capacitor 170. Particularly, the first source/drain 130 is located in the substrate 100 under the first side of the gate electrode 240 and electrically connects with the buried strap 290 of the trench capacitor 170. The second source/drain 140 is located in the step silicon layer 110 that is above the substrate 100, and is under the second side of the gate electrode 240 opposite to the trench capacitor 170. The trench step channel formed in the transistor unit of the subject invention is located above a portion of the substrate 100 and a portion of the upper surface and the sidewall of the step silicon layer 110. The channel connects the first source/drain 130 and the second source/drain 140 to increase the length of the current channel and resolve the leakage problem resulting from the punch-through phenomenon occurring in conventional recess channel array transistors.
Lastly, a series of processes, such as forming an insulating layer 320, patterning by using a photoresist, and etching, are executed to form the structure depicted in the cross-sectional view of FIG. 9. These processes are known techniques, and thus are not further described herein. Moreover, it should be mentioned that a bit contact window 250 is located above the step silicon layer 110 and is used to contact a bit line (not shown). Therefore, the subject invention further provides a raised second source/drain 140 such that the formation of the bit contact window 250 is easier.
As compared with the prior technology, the trench step channel cell transistor of the subject invention utilizes the anisotropic selective epitaxial growth to deposit silicon on the active area of the transistor and increase the length of the current channel with a step channel. Moreover, the superiority of the transistor of the subject invention over conventional recess channel array transistors lies in providing a trench step channel that is located above the active area of the transistor. Accordingly, the leakage resulting from the punch-through phenomenon that occurs in conventional recess channel array transistors can be reduced. In other words, the leakage resulted from the diffusion of the buried strap due to the recess channel can be prevented. Moreover, the method disclosed in the subject invention can also resolve the problem of sub-threshold voltage and enhance the performance of the cell transistor.
As known by persons skilled in the art, the above disclosure is just related to preferred embodiments of the subject invention and is not intended to limit the scope of the claims. Other equivalent changes or modifications without departing from the spirit disclosed in the subject invention should be covered in the following claims as appended.
Patent Application
20070246763
