Claims
- 1. A method of fabricating transistor which has an npn or pnp junction formed from quantum dots arrayed on the surface of a substrate having an insulation layer on the surface thereof, which comprises the step of arraying donor impurities and accepter impurities with a pitch of the size of said metalloprotein complex on the surface of said substrates said method composing the steps of:(a) fabricating metalloprotein complex hetero-trimer by holding accepter impurities or donor impurities on both sides of said donor impurities and said accepter impurities formed from metal atom aggregates; (b) having metalloprotein complex hetero-trimer adsorbed onto an LB membrane developed on the surface of an aqueous solution; (c) placing said LB membrane having said metalloprotein complex hetero-trimer adsorbed thereon on a substrate which is durable to temperatures beyond the burn-out temperature of protein; (d) burning out said protein through heat treatment in an inert gas that does not react with said substrate; and (e) reducing said metal atom aggregates in a reducing atmosphere; which further comprises the steps of: (f) forming an n-type region, a p-type region and a pn junction by diffusing the donor impurities and the accepter impurities via said insulation layer into said substrate by heat treatment; (g) forming an electrode section by patterning electrodes of a specified configuration; and (h) irradiating said n-type region, p-type region and said electrode section with electron beam of a scanning electron microscope, of which beam width is set to be not greater than said pitch, in vacuum in the presence of a trace of carbon compound, while scanning said electron beam to have carbon vapor-deposited between the n-type region and the electrode section, and between the p-type region and the electrode section, thereby forming lead wires.
- 2. The method according to claim 1, further comprising the step of adsorbing ferritin as said metalloprotein complex onto an LB membrane developed on the surface of an aqueous solution.
- 3. A method of fabricating transistor array comprising transistors arrayed in two-dimensional configuration, with said transistor having an npn or pnp junction formed from quantum dots arranged on a surface of a semiconductor substrate having an insulation layer on the surface thereof, said method comprising the steps of:(a) fabricating metalloprotein complex hetero-trimer by holding accepter impurities or donor impurities on both sides of said donor impurities and said accepter impurities formed from metal atom aggregates; (b) bonding at least one layer of apoprotein around said metalloprotein complex hetero-trimer; (c) having metalloprotein complex hetero-trimer with said apoprotein being bonded thereon adsorbed onto an LB membrane developed on the surface of an aqueous solution; (d) placing said LB membrane, whereon said metalloprotein complex hetero-trimer with said apoprotein being bonded thereon has been adsorbed, on a substrate which is durable to temperatures beyond the burn-out temperature of the protein and has an insulation layer at least on the surface thereof; (e) burning out the protein through heat treatment in an inert gas that does not react with said substrate; and (f) reducing said metalloprotein complex in a reducing atmosphere; and which further comprises the steps of: (g) forming an n-type region, a p-type region and a pn junction by diffusing the donor impurities and the accepter impurities via said insulation layer into said substrate by heat treatment; (h) forming an electrode section by patterning electrodes of a specified configuration; and (i) irradiating between said n-type region, p-type region and said electrode section with electron beam of a scanning electron microscope, of which beam width is set to be not greater than said pitch, in vacuum in the presence of a trace of carbon compound, while scanning said electron beam to have carbon vapor-deposited between the n-type region and the electrode section, and between the p-type region and the electrode section, thereby forming lead wires.
Priority Claims (1)
Number |
Date |
Country |
Kind |
9-157436 |
May 1997 |
JP |
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Parent Case Info
This application is a divisional of Ser. No. 09/228,276, filed Jan. 11, 1999, now U.S. Pat. No. 6,121,075 which is a divisional of Ser. No. 09/086,672, filed May 29, 1998.
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