Patent Application
20230260996
Vertical power transistors, in which the current flows from the top surface of the transistor to the back or bottom surface of the transistor substrate, are commonly used for controlling high currents and high voltages, since they can be formed with a reduced area compared to devices in which current flow through the transistor is lateral.
III-nitride materials, and in particular, gallium nitride (GaN), allow vertical field effect transistor-based power transistors to be fabricated with high breakdown voltages (e.g., in excess of 1200 V) while offering significant reductions in the specific on-resistance (i.e., the on-resistance of the device multiplied by the device area) compared to silicon or silicon carbide materials.
Despite the progress made in the area of vertical power transistors, there is a need in the art for improved methods and systems related to vertical power transistors.
The present invention generally relates to the field of electronics, including field effect transistor (FET) devices and junction FET (JFET) devices, and more specifically to semiconductor manufacturing technology. In a particular embodiment, structures and methods of forming vertical fin-based FETs (FinFETs) with varying electrical conductivity regions are provided. Embodiments of the present invention are applicable to a variety of different, vertical FET structures and gate configurations.
According to an embodiment of the present invention, a vertical fin-based field effect transistor (FinFET) device is provided. The vertical FinFET device includes an array of FinFETs comprising a plurality of rows and columns of active fins with source contacts, one or more rows of first inactive fins disposed on a first set of sides of the array of FinFETs, and one or more columns of second inactive fins disposed on a second set of sides of the array of FinFETs. The first inactive fins and the second inactive fins are characterized by a reduced electrical conductivity compared to an electrical conductivity of the active fins of the array of FinFETs. The vertical FinFET device also includes an active gate region surrounding the FinFETs of the array of FinFETs and an additional gate region surrounding the first inactive fins and the second inactive fins. At least a portion of the additional gate region is a neutralized gate region.
The first inactive fins and the second inactive fins can comprise ion implanted fins. The first inactive fins and the second inactive fins can comprise neutralized regions formed by plasma treatment. The reduced electrical conductivity can be reduced by at least 90% or 99%. The neutralized gate region can be characterized by a second reduced electrical conductivity compared to a second electrical conductivity of the active gate region. The neutralized gate region can comprise an ion implanted gate region. The neutralized gate region can comprise a neutralized region formed by plasma treatment. The second reduced electrical conductivity can be reduced by at least 90% or 99%. The additional gate region can be the neutralized gate region. The active fins, the first inactive fins, and the second inactive fins can comprise a III-N semiconductor.
According to another embodiment of the present invention, a method of fabricating a transistor array is provided. The method includes forming an array of FinFETs comprising a plurality of rows and columns of active fins with source contacts. Each of the active fins is surrounded by an active gate region. The method also includes forming one or more rows of first inactive fins disposed on a first set of sides of the array of FinFETs. Each of the first inactive fins is surrounded by an additional gate region. The method further includes forming one or more columns of second inactive fins disposed on a second set of sides of the array of FinFETs. Each of the second inactive fins is surrounded by the additional gate region. Additionally, the method includes forming a neutralization mask having openings exposing the first inactive fins, the second inactive fins, and a portion of the additional gate region, and reducing an electrical conductivity of the first inactive fins, the second inactive fins, and the portion of the additional gate region.
Reducing the electrical conductivity can include ion implanting a dopant into the first inactive fins, the second inactive fins, and the portion of the additional gate region. Reducing the electrical conductivity can include performing a hydrogen plasma treatment process on the first inactive fins, the second inactive fins, and the portion of the additional gate region. Reducing the electrical conductivity can include reducing the electrical conductivity by at least 90% or by at least 99%. A portion of the additional gate region can be the additional gate region. The method can also include providing a III-N substrate structure comprising providing a III-nitride substrate, epitaxially growing a first III-nitride layer coupled to the III-nitride substrate, and epitaxially growing a second III-nitride layer coupled to the first III-nitride layer. Forming the array of FinFETs can include forming a hard mask layer on the second III-nitride layer and patterning the hard mask layer to form a patterned hard mask. Forming the array of FinFETs can further include etching the second III-nitride layer and a portion of the first III-nitride layer using the patterned hard mask to form a plurality of trenches and selectively regrowing a third III-nitride layer in the plurality of trenches. The active fins can be characterized by a first electrical conductivity and the first inactive fins and the second inactive fins can be characterized by a second electrical conductivity less than the first electrical conductivity.
Numerous benefits are achieved by way of the present invention over conventional techniques. For example, embodiments of the present invention provide methods and systems that provide uniform dimensions and lower junction leakage in arrays of gate-all-around vertical transistors by providing neutralized fins (i.e., inactive fins with a reduced conductivity). The neutralized fins are not connected to the source electrode, therefore do not contribute to the current carrying capability of the array of gate-all-around vertical transistors. The neutralized fins and the gate regions surrounding the neutralized fins are implanted with neutralizing ions and are characterized by reduced electrical conductivities. As a result, the neutralized fins have a reduced contribution or do not contribute to junction leakage of the transistor array. These and other embodiments of the disclosure, along with many of its advantages and features, are described in more detail in conjunction with the text below and corresponding figures.
The present invention generally relates to the field of electronics, and more specifically to semiconductor manufacturing technology. In a particular embodiment, structures and methods of forming vertical FinFETs with varying conductivity regions are provided. Embodiments of the present invention are applicable to a variety of different, vertical FET structures and gate configurations.
Power semiconductor devices including transistors and diodes are widely used today in such applications as industrial power supplies, motor drives, consumer electronics, etc. A common application of power semiconductor transistors is their use as switches in switch-mode power supplies or motor drives. In such applications, the ability of the device to operate at high voltages (650V or 1200V, for example) and to withstand momentary overvoltage conditions (line surges or lightning strikes on power lines, for example) are extremely important.
In addition, in order to reduce the resistance of the switch and reduce parasitic capacitances, etc., that limit switch speed, an increased conductance per unit area is desirable. Switch transistors in which the current flow is primarily vertical offer reduced resistance per area. This benefit can be further improved by arranging the control channel of the transistor to lie in the vertical direction, e.g., a “trench” channel transistor. The resistance of the transistor has several components, including the resistance of transistor channel (i.e., the region where current is directly controlled by the input gate voltage), the resistance of the “drift” region (i.e., the region designed to hold the breakdown voltage of the transistor), and the resistance of the starting substrate, contacts, metals, etc.
Transistors with vertical current flow are typically designed with the drain contact at the bottom surface of the chip, and the gate and source contacts at the top surface of the chip.
In order to maximize the switch conductivity (i.e., minimize the switch resistance) and provide a uniform transient response for the device, the transistor may be fabricated using an array of many small, vertical-channel switch devices surrounded by control gates, which can be referred to as an array of “gate-all-around” transistors. The finished device has all sources connected to a single electrode, a common gate electrode, and a drain electrode.
Improvements in switch resistance and capacitance can be made by changing the semiconductor material from silicon to a wide bandgap material such as gallium nitride, which offers a higher critical field for breakdown. Additionally, this change allows the high-voltage drift region of the device to be made thinner and more heavily doped than with similar silicon devices, reducing the “specific resistance” (i.e., the resistance X area) of the drift region, and reduces the device on-resistance for a given die size.
Accordingly, for such wide bandgap transistors, the gate-all-around array has a small area, and is typically fabricated with fine lithographic features (e.g., minimum geometries of <0.5 μm). The control of these features is critical to the uniform operation of the device. For example, if the individual device in the gate-all-around array is a vertical JFET or accumulation-mode MOSFET built on a vertical “fin,” variations in the width of the fin can cause significant variation in the individual device leakage or threshold voltage. Such variations impact the overall leakage of the array or the on-resistance of the array, and can affect the maximum voltage or switching efficiency of the device.
Accordingly, methods and systems that provide uniform dimensions in arrays of gate-all-around vertical transistors are described herein.
A vertical FET transistor structure is described in U.S. Pat. No. 9,117,839 (Kizilyalli, et al.) (the “'839 structure”), the disclosure of which is hereby incorporated by reference in its entirety for all purposes. In the '839 structure, the transistor conducting channel is formed using a semiconductor “fin” created by patterning and etching surrounding material to a certain depth. A semiconductor material with an opposite doping type is epitaxially regrown (e.g., using metalorganic vapor phase epitaxy (MOVPE)) to be substantially planar with the top of the semiconductor fin. The regrown material serves as the gate electrode of a vertical FET and application of control voltages to the gate electrode modulates the conduction of current in the vertical fin channel between the top of the fin (i.e., the source) and the bottom of the fin (i.e., normally, the drift region, which is further connected to the drain electrode via the semiconductor substrate).
In the '839 structure, the regrown gate material surrounds the fin. An array of fins can be fabricated with a common gate using this approach, with, for example, fins arranged in a number of rows and columns so that the total number of transistors achieves the desired on-resistance target for the final device.
Dimensional control of the fins is utilized to maintain uniform device characteristics for each individual fin. Fin width control is particularly useful to achieve a narrow threshold voltage and leakage current distribution. Accordingly, methods and systems are provided to achieve the local uniformity of the lithography process that creates the masking layer that defines the fin geometry. Local uniformity of the etch processes that transfer the masking layer pattern into the hard mask and the GaN to create the fin structures are also provided by embodiments of the present invention.
The inventors have determined that the uniformity of both the lithography process and the etch processes can vary significantly between a region with a regular pattern and a region with a sparse pattern. Such a transition occurs at the edges of the array of fins. For example, the presence of a large sparse area next to a regular array can lead to differences in exposure dose due to proximity effects, which will cause the resist linewidth to vary between the center of the array and the edges of the array, with a resulting increase in the electrical variation of the fin devices near the edge of the array. Additionally, the presence of a large sparse pattern area next to a regular pattern array can lead to differences in etch rate caused by variation in the amount of etchant consumed in the sparse pattern region vs. the amount consumed in the regular pattern array. Such differences in etch rate can affect both fin width and fin height, with a resulting increase in the electrical variation of the fin devices near the edge of the array.
In addition, the inventors have determined that the uniformity of the regrown-gate process may be dependent on the local pattern density in the array as discussed in U.S. Patent Application Publication No. 2021/0210624, the disclosure of which is hereby incorporated by reference in its entirety for all purposes. The regrown-gate process in the '839 patent uses a selective area regrowth, where the top of the fins is protected by a hard mask. GaN does not grow on the hard mask, and the gallium-containing species that arrive on the hard mask diffuse to the exposed GaN surrounding the hard mask, thereby enhancing the epitaxial growth rate in the array relative to the growth rate on a uniform GaN surface such as is found outside the array. Such variations in the growth rate can lead to non-uniform height of growth on the fin sidewalls, which will affect the effective channel length of the switch, and can cause variation in leakage current at high voltage and in threshold voltage, for fins near the edges of the array. Variation in the growth rate may also affect the uniformity of dopant incorporation in the GaN during regrowth, which in turn can cause variation in threshold voltage.
Similarly, the local incorporation rate of dopant species in the regrown gate (or through the use of a gas-phase doping technique, e.g., as described in U.S. Patent Application Publication No. 2022/0254918, the disclosure of which is hereby incorporated by reference in its entirety for all purposes, can be affected by the presence of a local mask or local topography. Doping of the regrown gate using a Mg-containing species (e.g., bis(cyclopentadienyl)magnesium (Cp2Mg)) can vary near the edge of the array, causing local variations in threshold voltage or leakage characteristics of the vertical devices in that region.
Therefore, methods and structures that can improve uniformity of lithography control, etch control, and regrowth control (if used) to ensure uniform device characteristics for the individual vertical fin-based transistors in the array are provided by embodiments of the present invention and described herein.
As described more fully herein, in some embodiments, an array of fins is created in a second epitaxial layer disposed on a first epitaxial layer on a substrate, to form a vertical power device, as described, for example, in U.S. Pat. No. 11,335,810 and U.S. Patent Application Publication No. 2022/0020743, the disclosures of which are hereby incorporated by reference in their entirety for all purposes. The array is arranged in a regular pattern of rows and columns. For the discussion below, the fins are assumed to be rectangular in plan view, with the long axis arranged in the direction of the column (i.e., the y-direction) and the narrow axis arranged in the direction of the row (i.e., the x-direction). Various other arrangements of the fin array are possible, for example, as discussed in U.S. Patent Application Publication No. 2021/0210624, the disclosure of which is hereby incorporated by reference in its entirety for all purposes. In an embodiment, the conductivity type of the first and second epitaxial layers and the substrate are n-type.
According to embodiments of the present invention, the array is designed to include one or more extra fins (i.e., inactive fins) at the ends of each row, and one or more extra fins (i.e., inactive fins) at the top and bottom of each column, thereby providing an excess number of fins compared to the number of fins utilized to achieve the desired on-resistance and current capacity for the transistor array. In some embodiments, the number of extra fins at each end of a row is between one and ten. In an embodiment, the number of extra fins at each end of a row is five. In an embodiment, the extra fin at the top and bottom of each column is shorter in the y-direction than the other fins in the column. These extra fins can be referred to as inactive fins, additional fins, extra fins, or dummy fins.
The methods provided according to embodiments of the present invention can also include forming a gate region around the fins using one of several methods. Forming the gate region can include regrowing an epitaxial layer in the region between the fins, as described in U.S. Pat. No. 11,335,810 and U.S. Patent Application Publication No. 2022/0020743. In some embodiments, this epitaxial layer is p-GaN. Forming the gate region can include implanting a gate region in the region between the fins (and optionally, in the sidewalls of the fins), where the conductivity type of the gate region is opposite that of the first and second epitaxial layers. In an embodiment, the gate region is p-type. These implantation methods are discussed in U.S. Pat. No. 11,575,000 and U.S. Patent Application Publication Nos. 2021/0407815 and 2022/0254918, the disclosures of which are hereby incorporated by reference in their entirety for all purposes. Forming the gate region can further include diffusing a gate region in the region between the fins (and optionally, in the sidewalls of the fins), where the conductivity type of the gate region is opposite that of the first and second epitaxial layers. In an embodiment, the gate region is p-type. In an embodiment, the dopant is diffused from a solid source. In an embodiment, the dopant is diffused from a gas-phase source. In an embodiment, the dopant is one of Mg, Zn or Be. These diffusion methods are discussed in U.S. Pat. No. 11,575,000 and U.S. Patent Application Publication Nos. 2021/0407815 and 2022/0254918.
Referring to
In an embodiment, substrate 101 is an N+ doped III-nitride substrate that is heavily doped with N-type dopants in a dopant concentration in a range of about 5×1017 atoms/cm3 to about 1×1019 atoms/cm3 and a resistivity of less than 0.020 ohm-cm. In one embodiment, the resistivity of the N+ doped III-nitride substrate may be from about 0.001 ohm-cm to 0.018 ohm-cm, preferably less than 0.016 ohm-cm, and more preferably, less than 0.012 ohm-cm. First semiconductor layer 102 is a drift layer having a thickness of about 12 μm and a dopant concentration in a range of about 1×1016 atoms/cm3. Second semiconductor layer 103 is a fin conduction layer having a uniform doped region with N-type dopants of about 1.3×1017 atoms/cm3 and a thickness of about 12 μm. In the embodiment illustrated in
Referring to
It is noted that the bottom portion of the fins may have a shape different form the shape shown in
In one embodiment, after forming the trench (i.e., recess region 108), a cleaning process is carried using a tetramethylammonium hydroxide (TMAH) solution of about 25% by weight, at a temperature of about 85° C., and for a duration of about 30 minutes. In another embodiment, prior to performing a cleaning using the TMAH solution, a pre-cleaning such as piranha clean using a H2SO4:H2O in a volume ratio 2:1 for 2 minutes may also be performed.
Referring to
Referring to
In one exemplary embodiment, the fin length L is about 25 μm, the fin width W is about 0.2 μm, the fin thickness or fin height measured along the z-direction is about 0.8 μm, the pitch P is in the range between 1.5 μm and 2.5 μm. In one embodiment, a ratio between a fin width W and a pitch P between two adjacent fins is in the range between about 0.08 and 0.13, preferably in the range between 0.1 and 0.12. In one embodiment, a ratio between a fin length L and the pitch P between two adjacent fins is in the range between 5 and 25, preferably between and 20, and more preferably between 12 and 16. In one embodiment, the fin length L is about 25 μm and the fin width W is in the range between 0.15 μm and 0.7 μm.
In operation, the fins will form the channels of the FinFET and the gate metal will be deposited between adjacent fins. As a result, the design illustrated in
In
As described above and more fully in relation to
In addition to regrowth thickness uniformity, improvements in fin width uniformity are provided by embodiments of the present invention. At the boundary 312 of the active fin array 310, the amount of photoresist developer outside the active fin array is different than the amount of photoresist developer inside the active fin array, resulting in a gradient of developer across the active fin array 310. In conditions in which the developer concentration is lower inside the active fin array in comparison with outside the active fin array, the linewidth of the fin definition mask, e.g., the patterned hard mask or patterned metal mask, can vary. This will result, during the fin definition process, in differences in the fin critical dimension (CD) near the edges of the active fin array compared to the center of the active fin array. Moreover, the etch process can be impacted by edge effects. During etching of the gate trench, a large area outside the active fin array is etched in comparison to a smaller area inside the active fin array. As a result, the etch loading will vary near the edges of the active fin array, resulting in variations in the etch rate and, as a result, variation in the depth of the gate trench across the active fin array. Variation in the depth of the gate trench can then result in variation in the uniformity of the thickness of the regrown material disposed between fins.
Referring to
Referring to
Although the inactive fins in the inactive fin columns 320/321 have the same fin width and fin pitch as the active fins in the active fin array 310, this is not required by the present invention and the fin width and the fin pitch in the inactive fin columns 320/321 can differ from that in the active fin array 310. As an example, the pitch of the inactive fins in the inactive fin columns 320/321 could not only be different than the pitch in the active fin array 310, but the pitch could vary across the inactive fin columns 320/321. Additionally, the inactive fins in the inactive fin columns 320/321 can have different fin heights than the active fins in the active fin array 310. Moreover, the inactive fins in the inactive fin row 330/331, although they are illustrated as having the same fin width and fin pitch as the active fins in the active fin array 310, do not have to have the same fin width and the fin pitch as the active fins in the active fin array 310. Additionally, the inactive fins in the inactive fin row 330/331 can be offset along the x-direction with respect to the active fins in the active fin array 310, providing a variation on the embodiment illustrated in
Irregular edges (e.g., fitting the array to a circular arc of an edge termination) may be accommodated by, for example, “stair-stepping” the active fin array boundary with appropriate combinations of additional rows of inactive fins and additional columns of inactive fins.
Referring to
In addition to regrowth thickness non-uniformity, the regrown material may also be characterized by variation in doping concentration. Because regrowth rates are different on different planes of the GaN hexagonal crystal, for example, the m-planes and the c-planes, the dopant incorporation can vary depending on the growth plane.
Moreover, in addition to regrowth thickness, the fin width can vary as a function of lateral dimension (i.e., along the x-direction). As illustrated, in
Thus,
Referring to
Thus, near the end of the fin, the gate growth may be irregular, exposing (or overfilling above) the fin. Similarly, p-GaN dopant incorporation may be irregular near the end of the fin, and the fin dimensions may vary in the same region.
It should be noted that the source contacts 105′ are only formed on fins in the active fin array 310 and not on the fins in the inactive fin columns 320 since the inactive fins do not contribute to current flow through the FET device. It should be noted that the source contacts 105′ are shown in
Referring to
As shown in the cross-section illustrated in
Embodiments of the present invention are applicable to arrays of vertical fin-based FETs in which the current runs vertically along the fin and the arrays of fins are enclosed by a gate-all-around structure so that all fins have a common gate. The gate-channel interface can be located on the vertical sidewall of the vertical fin. The FETs may be JFETs with regrown gates, implanted gates, or diffused gates, or they may be MOSFETs, including accumulation-mode MOSFETs. The vertical fin-based FETs can be fabricated using III-nitride semiconductors. In an embodiment, the vertical fin-based FETs are fabricated using GaN. In an embodiment, the number of inactive fin columns is between 1 and 10, and the number of inactive fin rows is between 1 and 5. In an embodiment, the inactive fin rows use fins of shorter height (see
In
Gate metal contact structure 914 is formed on the upper portion of semiconductor gate region 911. In some embodiments, the gate metal contact structure 914 can include a metallic structure. For example, the metallic structure may include nickel, palladium, silver, gold, combinations thereof, and the like. The metallic structure can make an ohmic contact with the semiconductor gate region 911, which can be a p-type semiconductor gate region. An edge termination 916 is formed on the p-type layer used as the semiconductor gate region 911 to enable high-voltage operation of the device. The p-type layer may also be connected to the source in some embodiments. A drain metal contact structure 918 is formed on a second side, i.e., the backside, of III-nitride substrate 902. The drain metal contact structure 918 can form an ohmic contact to the III-nitride substrate 902. In some embodiments, the drain metal contact structure 918 can include titanium, aluminum, or combinations thereof. In some embodiments, the drain metal contact structure 918 can further include a solderable metal structure such as silver, lead, tin, combinations thereof, or the like.
The semiconductor gate region 911 can be a diffused gate structure in which a diffusion source is utilized in a process in which diffusion dopants are incorporated into second III-nitride layer 906 and first III-nitride layer 904. As an example, a layer of a diffusion dopant material may be applied to the surfaces of the fins and first III-nitride layer 904. In some embodiments, the layer of diffusion dopant material may include either a metal layer formed with a p-type dopant (e.g., Mg, Zn, combinations thereof, and the like) or a metallic oxide layer formed with a p-type dopant (e.g., MgO, ZnO, combinations thereof, and the like), in contact with the exposed III-nitride surfaces of the fins. In some embodiments, the thickness of the metal or metallic oxide layer is 50-100 nm. In some embodiments, the layer of diffusion dopant material may further include a second layer of dielectric material (e.g., SiO2, Si3N4 or the like) disposed on the metal or metallic oxide layer.
A thermal treatment can be used to diffuse the p-type dopant into the exposed surfaces of the first III-nitride layer 904 and the second III-nitride layer 906. The resulting channel can have a width of the fin width minus twice the diffusion depth. In some embodiments, the thermal treatment may be performed in a furnace at temperatures from 900° C. to 1100° C. In some embodiments, the thermal treatment may be performed in a rapid thermal annealer at temperatures from 1000° C. to 1450° C. In some embodiments, the thermal treatment may be performed at a high ambient pressure (e.g., at 1 GPa in a N2 ambient), with or without the protective layer. In some embodiments, the heating may be a result of a series of rapid pulses (e.g., microwave). After diffusion, the diffusion dopant material may be removed, for example, by using a wet etch.
The alternate, vertical fin-based gate-all-around JFET structure using implanted or diffused gates illustrated in
In other embodiments, rather than diffusion, ion implantation is utilized to form implanted gate regions. Accordingly, the discussion provided in relation to
Thus, in a manner similar to that discussed with respect to the JFET device discussed in relation to
In addition to the above, the inventors have determined that, in order to achieve improved device performance, it is further desirable to fabricate additional structures that are electrically neutral (i.e., not conducting or having reduced conductivity), in order to reduce or minimize deleterious electrical effects, including extraneous junction leakage, floating semiconductor nodes, and the like. As shown in
In the embodiment illustrated in
Thus, the neutralization of the inactive fins 1106 and the portion 1122′ of the gate region 1120 reduces the electrical conductivity at these regions, thereby reducing leakage. As discussed herein, neutralization does not require that the conductivity of the semiconductor material is equal to that of undoped material; rather, it includes reductions in conductivity compared to the conductivity of the material prior to a neutralization process. Thus, starting with a given doping level and initial conductivity in the third semiconductor layer making up the fins, the neutralization processes described herein can reduce the conductivity to a value lower than the value of the initial conductivity. As an example, neutralization as described herein includes a reduction in conductivity of at least 90%, at least 95%, at least 96%, at least 97%, at least 98%, at least 99%, at least 99.9%, at least 99.99%, at least 99.999%, at least 99.9999%, and the like. In other words, the sheet resistance value for the un-neutralized material (e.g., p-GaN material) can be on the order of 30 kΩ/□ and the sheet resistance value for the neutralized material can be on the order 107 Ω/□, 108 Ω/□, 109 Ω/□, or more, achieving a modification in the resistivity/conductivity of four orders of magnitude or more.
Neutralizing the inactive fins 1106 and the portion 1122′ of the gate region 1120 as described herein reduces the electrical conductivity of the inactive fins 1106 and the portion 1122′ of the gate region 1120, thereby reducing their electrical activity or making them electrically inactive, resulting in many advantages. First, the junction leakage is significantly reduced. Second, the complexity of the masking step, the implant step, and the photoresist strip step are low. Third, implant energies are well controlled and can be easily modified to achieve any desired neutralization depth. Fourth, this implant can be combined with an existing implant step of the right implant energy, making the whole process flow very efficient.
In one embodiment, the neutralization process is an ion implantation process during which a neutralizing species is implanted into the areas exposed by the mask openings. The neutralizing species may be N, Ar, He, Si, or O, other suitable implant ions, or combinations thereof. In an embodiment, the dose of the neutralizing species is between 1×1011 cm−2 and 5×1013 cm−2. In an embodiment, the energy of the implantation is between 15 KeV and 700 KeV. In an embodiment, the energy of the implant for N is less than 500 KeV. In an embodiment, the energy of the implant for He is less than 200 KeV. In an embodiment, the energy of the implant for He is less than 170 KeV. In some embodiments, ion implantations with multiple energies are performed. In some embodiments, each of those ion implantations with multiple energies may have a different dose.
As an example, instead of nitrogen, other neutral species (e.g., argon, helium, or any combination of nitrogen, argon, and helium) can be used to perform ion implantation to neutralize the inactive fins 1106 and the portion 1122′ of the gate region 1120. As another example, the implant depth can be controlled by changing implant energy. In one embodiment, the entire depth of the fins is fully implanted to neutralize the bottom of each fin. In another embodiment, shallow implantation is conducted, and the region close to the top surface of each fin is neutralized. In yet another embodiment, the implantation is intermediate between the full implant and shallow implantation.
The ion implantation processes used herein implant ionic species to increase the resistivity (i.e., decrease the conductivity) of predetermined portions of the semiconductor layer to provide a spatial variation or modulation in the conductivity. Without limiting embodiments of the present invention, the inventors believe that the implantation process reduces the conductivity by at least one of the following mechanisms: compensating for dopants, annihilating dopants, increasing vacancy density, increasing void density, decreasing the total net charge in the epitaxial layer, or decreasing the density of ionized acceptors (donors for n-type material). Some or all of these mechanisms may provide for increased resistivity. Throughout the specification, reference is made to decreased conductivity or increased resistivity, which can also be referred to as a decrease in active charge, a decrease in active dopant species, or the like. Due to the robust nature of GaN-based materials, ion implantation can produce implanted ions interspersed with unchanged epitaxial material, effectively reducing the conductivity in an averaged sense, with voids or vacancies interspersed in the lattice with as-grown epitaxial material. Embodiments of the present invention are not limited by the physical mechanism resulting in the spatial conductivity modulation. Additionally, the mechanisms associated with ion implantation are also applicable to diffusion processes and hydrogen plasma treatments are appropriate.
It should be understood that, although ion implantation is used as an example neutralization process, this is not intended to be limiting. In another embodiment, the neutralization process may further include a hydrogen plasma treatment process, which deactivates the dopant atoms in the p-GaN layer, or a plasma treatment process using other elements, e.g., N, O, Ar, or the like. Exposure of the p-GaN surface to a hydrogen plasma introduces H atoms into the p-GaN, where they can subsequently bond with Mg acceptors, forming Mg—H complexes, which neutralize the Mg as an acceptor.
Plasma treatments of the GaN surface with other species (e.g., N, O, Ar) can induce physical damage to the surface region to a depth dependent on the plasma energy. This damage can neutralize the conductivity of the GaN in a manner similar to that of implantation.
A plasma approach is not the only way that hydrogenation can be used to compensate holes in p-GaN. Thermal annealing in an NH3-ambient at temperatures above 600° C. has been shown to increase p-GaN resistivity. This result is consistent with atomic hydrogen produced by NH3 dissociation creating an Mg—H complex that neutralizes Mg as an acceptor. Such a process may be further included in the neutralization approach described herein.
Thus, some embodiments of the present invention form a non-conducting region in the exposed GaN surface by neutralizing the inactive fins 1106 present in the neutralized fin row 1108 and the neutralized fin columns 1110, for example, using ion implantation. Specifically, in these embodiments, an ion implantation process is performed to implant dopants into the third semiconductor layer 107. The implanted dopants pass through the opening in the implantation mask and stop in a region of the third semiconductor layer that includes the inactive fins and the area surrounding each of the inactive fins. In some embodiments, the implant dopants may include nitrogen, helium, or argon.
In some embodiments, the ion implantation process may introduce compensating donor levels in the third semiconductor layer to form the neutralized regions as a semi-insulating semiconductor region. In such embodiments, dopants may include oxygen and silicon. Such dopants may also introduce damage and traps into the third semiconductor layer.
In some embodiments, the ion implantation process may implant metallic ions into the third semiconductor layer. In such embodiments, the implant dopants may introduce deep levels in the third semiconductor layer to form the neutralized regions as a semi-insulating semiconductor region. Such dopants may include iron, titanium, and nickel.
In some embodiments, the ion implantation process may implant ions that physically damage the crystal lattice of the third semiconductor layer to create the neutralized regions as a non-conducting region. The damage may be extreme enough to create amorphous semiconductor material. A variety of ions can be used for this purpose, as long as the total dose is high enough to damage the semiconductor material.
Referring to
In yet other embodiments, the width WO is substantially equal to the pitch between inactive fins, resulting in implantation of substantially all the material in the third semiconductor layer 107 surrounding the inactive fins 1106. In these embodiments, the neutralization mask 1302 is open in area 1350, thereby resulting in neutralization of all of area 1350. In an alternative embodiment, the neutralization mask 1302 exposes a portion of, rather than all of, the inactive fins 1106 and the additional gate region 1122 surrounding each of the exposed inactive fins 1106. Therefore, only a portion of the inactive fins 1106 and the additional gate region 1122 are neutralized. One of ordinary skill in the art would recognize many variations, modifications, and alternatives.
In the example illustrated in
As a result of the ion implantation, the inactive fins 1106 are characterized by a reduced electrical conductivity compared to an electrical conductivity of the active fins 1104 in the active fin array 310. Accordingly, the inactive fins 1106 contribute significantly less to junction leakage in the transistor array. In one embodiment, the reduced electrical conductivity is reduced by at least 90%. In another embodiment, the reduced electrical conductivity is reduced by at least 99%. In yet another embodiment, the inactive fins 1106 are electrically neutral, and so do not contribute to junction leakage in the transistor array. As an example, since the top of each inactive fin 1106 can act like a floating node, reducing the conductivity of these inactive fins 1106 can reduce charging of the inactive fin 1106 and improve device performance by preventing breakdown.
Likewise, the neutralized gate material in the additional gate region 1122 surrounding the inactive fins 1106 is characterized by a second reduced electrical conductivity compared to an electrical conductivity of the gate region 1120 surrounding the active fins 1104 in the active fin array 310, i.e., the primary array of fins. Accordingly, the neutralized gate material in the additional gate region 1122 contributes significantly less to junction leakage in the transistor array. In one embodiment, the second reduced electrical conductivity is reduced by at least 90%. In another embodiment, the second reduced electrical conductivity is reduced by at least 99%. In yet another embodiment, the neutralized gate material surrounding the inactive fins 1106 is electrically neutral, and so do not contribute to junction leakage in the transistor array.
As illustrated in
Referring to
As mentioned above, various neutralization techniques can be employed to neutralize the inactive fins 1106 as well as the portion 1122′ of the additional gate region 1122 adjacent to each inactive fin 1106. In addition to ion implantation, hydrogen plasma treatment, plasma treatment using elements other than hydrogen, and/or diffusion processes can be utilized.
The method also includes forming one or more rows of first inactive fins disposed on a first set of sides of the array of FinFETs (1704). Each of the first inactive fins is surrounded by an additional gate region. As illustrated in
The method also includes forming one or more columns of second inactive fins disposed on a second set of sides of the array of FinFETs (1706). Each of the second inactive fins is surrounded by the additional gate region. As illustrated in
The method also includes forming a neutralization mask having openings exposing the first inactive fins, the second inactive fins, and a portion of the additional gate region (1708). In an embodiment, a portion of the additional gate region is the entire area of the additional gate region. As illustrated in
The method also includes reducing an electrical conductivity of the first inactive fins, the second inactive fins, and the portion of the additional gate region (1710). As illustrated in
In the embodiment shown in
In the embodiment shown in
In yet another embodiment, reducing the electrical conductivity comprises performing a hydrogen plasma treatment process on the inactive fins and the portion of the additional gate region.
The methods provided according to embodiments of the present invention can also include removing the neutralization mask. In an embodiment, the neutralization mask is removed using an oxygen plasma. In another embodiment, the neutralization mask is removed using a wet cleaning process. In yet another embodiment, the neutralization mask is removed using a combination of an oxygen plasma and a wet cleaning process.
The methods provided according to embodiments of the present invention can also include forming a junction terminated extension (JTE) region, for example, as described in U.S. Patent Application Publication Nos. 2022/0013626, and 2022/0238643, the disclosures of which are hereby incorporated by reference in their entirety for all purposes. In some embodiments, the neutralization implantation may be performed simultaneously with the formation of the JTE region.
The methods provided according to embodiments of the present invention can also include forming a gate metal contact to the gate region and after forming the gate metal contact, depositing an interlayer dielectric. The work function of the gate metal is such that the gate metal electrode depletes the fin at zero bias as described in U.S. Patent Application Publication No. 2021/0407815, the disclosure of which is hereby incorporated by reference in its entirety for all purposes. The interlayer dielectric can be patterned and etched to form vias to the source metal contacts.
While various embodiments of the disclosure have been described above, it should be understood that they have been presented by way of example only, and not by way of limitation. Likewise, the various diagrams may depict an example architectural or other configuration for the disclosure, which is done to aid in understanding the features and functionality that can be included in the disclosure. The disclosure is not restricted to the illustrated example architectures or configurations, but can be implemented using a variety of alternative architectures and configurations. Additionally, although the disclosure is described above in terms of various exemplary embodiments and implementations, it should be understood that the various features and functionality described in one or more of the individual embodiments are not limited in their applicability to the particular embodiment with which they are described. They instead can be applied alone or in some combination, to one or more of the other embodiments of the disclosure, whether or not such embodiments are described, and whether or not such features are presented as being a part of a described embodiment. Thus, the breadth and scope of embodiments of the present invention should not be limited by any of the above-described exemplary embodiments.
It will be appreciated that, for clarity purposes, the above description has described embodiments of the disclosure with reference to different functional units and processors. However, it will be apparent that any suitable distribution of functionality between different functional units, processors or domains may be used without detracting from the disclosure. For example, functionality illustrated to be performed by separate processors or controllers may be performed by the same processor or controller. Hence, references to specific functional units are only to be seen as references to suitable means for providing the described functionality, rather than indicative of a strict logical or physical structure or organization.
Terms and phrases used in this document, and variations thereof, unless otherwise expressly stated, should be construed as open ended as opposed to limiting. As examples of the foregoing: the term “including” should be read as meaning “including, without limitation” or the like; the term “example” is used to provide exemplary instances of the item in discussion, not an exhaustive or limiting list thereof; and adjectives such as “conventional,” “traditional,” “normal,” “standard,” “known”, and terms of similar meaning, should not be construed as limiting the item described to a given time period, or to an item available as of a given time. Instead, these terms should be read to encompass conventional, traditional, normal, or standard technologies that may be available, known now, or at any time in the future. Likewise, a group of items linked with the conjunction “and” should not be read as requiring that each and every one of those items be present in the grouping, but rather should be read as “and/or” unless expressly stated otherwise. Similarly, a group of items linked with the conjunction “or” should not be read as requiring mutual exclusivity among that group, but rather should also be read as “and/or” unless expressly stated otherwise. Furthermore, although items, elements or components of the disclosure may be described or claimed in the singular, the plural is contemplated to be within the scope thereof unless limitation to the singular is explicitly stated. The presence of broadening words and phrases such as “one or more,” “at least,” “but not limited to”, or other like phrases in some instances shall not be read to mean that the narrower case is intended or required in instances where such broadening phrases may be absent.
It is also understood that the examples and embodiments described herein are for illustrative purposes only and that various modifications or changes in light thereof will be suggested to persons skilled in the art and are to be included within the spirit and purview of this application and scope of the appended claims.
This application claims priority to U.S. Provisional Patent Application No. 63/310,998, filed on Feb. 16, 2022, entitled “Fin-Based Vertical Field Effect Transistor (FinFET) with Varying Conductivity Regions,” the disclosure of which is hereby incorporated by reference in its entirety for all purposes.
| Number | Date | Country | |
|---|---|---|---|
| 63310998 | Feb 2022 | US |
