Claims
- 1. An improvement in a method for generating a delayed precharging signal in a memory having word lines which are selectively discharged comprising the steps of:
- precharging a dummy word line high;
- presetting a timing control signal OWDN low;
- discharging said dummy word line low;
- switching said timing control signal OWDN high when said dummy word line has been discharged low, said dummy word line being discharged sufficiently to allow an end of said selected word line to discharge to ground; and
- initiating a precharge clock signal, PC0.
- 2. The improvement of claim 1 where said step of initiating said precharge clock PC0 initiates the first one of a series of sequentially trigger precharge clock signals including PC0 and PC1 used to precharge said memory.
- 3. The improvement of claim 1 wherein said dummy word line is comprised of a plurality of dummy line segments and where said step of precharging said dummy word line high comprises the step of simultaneously precharging each of said segments high and said step of discharging said dummy word line segment low comprises the step of sequentially discharging said plurality of segments, said plurality of segments being coupled in series for discharge purposes.
- 4. The improvement of claim 1 further comprising the step of preventing power dissipation in a timing control circuit after said timing control signal OWDN is switched high.
RELATED CASES
This is a divisional of application Ser. No. 08/426,037 filed on Apr. 21, 1995, now U.S. Pat. No. 5,546,544, which is a continuation-in-part of U.S. patent application, Ser. No. 07/538,185, entitled Improved Semiconductor Read-Only VLSI Memory, which is incorporated herein by reference, filed on Jun. 14, 1990, now abandoned.
US Referenced Citations (2)
Number |
Name |
Date |
Kind |
4982367 |
Miyatake |
Jan 1991 |
|
4989182 |
Mochizuki et al. |
Jan 1991 |
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Divisions (1)
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Number |
Date |
Country |
Parent |
426037 |
Apr 1995 |
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Continuation in Parts (1)
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Number |
Date |
Country |
Parent |
538185 |
Jun 1990 |
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