Patent Application
20240178000
This application is based on and claims priority under 35 U.S.C. § 119 to Korean Patent Application No. 10-2022-0162032, filed on Nov. 28, 2022, in the Korean Intellectual Property Office, the disclosure of which is incorporated by reference herein in its entirety.
The inventive concept relates to a wafer dicing method and a method of manufacturing a semiconductor device by using the wafer dicing method, and more particularly, to a wafer dicing method in which a stealth dicing process is performed, and a method of manufacturing a semiconductor device by using the wafer dicing method.
A laser processing process may refer to a process of processing a shape or physical property of a surface of a workpiece by scanning a laser beam onto the surface of the workpiece. For example, the laser processing process includes a patterning process for forming a pattern on a surface of a workpiece, a process of modifying a property of a workpiece, such as wafer annealing, a molding process for changing a shape of a workpiece through heating and melting, and a breaking process for breaking a workpiece into a plurality of units through heating and melting.
In a wafer dicing method using a laser beam, a workpiece may be broken by heating and melting the workpiece by irradiating the workpiece with laser light of a wavelength band having a high absorption rate. When a wafer is melted and broken, not only the broken area but also the surrounding area is melted, causing damage to part of a semiconductor device formed on the wafer.
To resolve this, a stealth dicing process may be used to induce internal cracks by focusing a laser beam on the inside of the wafer.
The inventive concept provides a wafer dicing method with improved reliability, and a method of manufacturing a semiconductor device by using the wafer dicing method.
According to an embodiment of the inventive concept, a wafer dicing method includes preparing a wafer having a plurality of device formation areas and a scribe lane area defining the plurality of device formation areas, forming a plurality of semiconductor devices in the plurality of device formation areas of the wafer, forming, in the scribe lane area, a plurality of first grooves partially passing through at least a portion of the wafer in a vertical direction, forming a plurality of second grooves by planarizing lower surfaces of the plurality of first grooves, forming one or more internal cracks in the wafer by radiating a laser beam along lower surfaces of the plurality of second grooves, and separating the plurality of semiconductor devices from each other along the one or more internal cracks.
According to an embodiment of the inventive concept, a method of manufacturing a semiconductor device includes preparing a wafer having a plurality of device formation areas and a scribe lane area defining the plurality of device formation areas, forming a plurality of semiconductor devices in the plurality of device formation areas of the wafer, forming a plurality of insulating layers and a wiring layer on the wafer, forming, in the scribe lane area, a plurality of first grooves partially passing through at least a portion of the wafer in a vertical direction, forming a plurality of second grooves by planarizing lower surfaces of the plurality of first grooves, forming one or more internal cracks in the wafer by radiating a laser beam along lower surfaces of the plurality of second grooves, separating the plurality of semiconductor devices from each other along the one or more internal cracks, and packaging each of the plurality of separated semiconductor devices, wherein the plurality of first grooves are formed to pass through at least one of the plurality of insulating layers and the wiring layer in the vertical direction.
According to an embodiment of the inventive concept, a method of manufacturing a semiconductor device includes preparing a plurality of device formation areas and a scribe lane area defining the plurality of device formation areas, forming a plurality of semiconductor devices in the plurality of device formation areas of the wafer, forming a plurality of insulating layers and a wiring layer on the wafer, forming, in the scribe lane area, a plurality of first grooves partially passing through at least a portion of the wafer in a vertical direction, forming a plurality of second grooves by planarizing lower surfaces of the plurality of first grooves, forming one or more internal cracks in the wafer by irradiating the scribe lane area with a laser beam along lower surfaces of the plurality of second grooves, separating the plurality of semiconductor devices from each other along the one or more internal cracks, and packaging each of the plurality of separated semiconductor devices, wherein the forming of the plurality of first grooves in the scribe lane area includes performing at least one of a laser etching method using a first laser device, and a plasma etching method, the planarizing of the lower surfaces of the plurality of first grooves includes performing at least one of a laser etching method using a second laser device, and a chemical mechanical polish (CMP) method, the forming of the one or more internal cracks includes performing a laser etching method using a third laser device, and the plurality of first grooves are formed to pass through at least one of the plurality of insulating layers and the wiring layer in the vertical direction.
Embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, wherein like reference numerals (when used) indicate corresponding elements throughout the several views, and in which:
Hereinafter, embodiments of the inventive concept are described in detail with reference to the accompanying drawings. In the drawings, the same reference symbols are used to indicate the same device, and redundant descriptions thereof are omitted.
Referring to
The wafer W may include, for example, silicon (Si). The wafer W may include a semiconductor element, such as germanium (Ge), and a compound semiconductor, such as silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), and indium phosphide (InP). It is to be appreciated that embodiments of the inventive concept are not limited to the specific type of material used in forming the wafer W.
In some embodiments, the wafer W may have a silicon-on-insulator (SOI) structure. The wafer W may include a buried oxide layer on the front surface thereof. In some embodiments, the wafer W may include a conductive area formed on the front surface of the wafer W, for example, a well doped with impurities. In some embodiments, the wafer W may have various device isolation structures, such as, for example, a shallow trench isolation (STI) for isolating doped wells from each other, or a local oxidation of silicon (LOCOS) area for isolating adjacent transistors or other circuit elements. Although not shown, a plurality of material layers may be formed on the front surface of the wafer W. At least one material layer may be formed on a back surface of the wafer W.
The semiconductor device SD formed in the wafer W may be any of a memory device and a non-memory device. In some embodiments, the memory device may be a non-volatile memory semiconductor device, such as flash memory, phase-change random access memory (PRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FeRAM), or resistive random access memory (RRAM). The flash memory may be, for example, a vertical not AND (V-NAND) flash memory. In some other embodiments, the memory device may be a volatile memory semiconductor device, such as dynamic random access memory (DRAM) or static random access memory (SRAM). The memory device may be a volatile memory device that loses data when power is cut off. In some embodiments, the non-memory device may be a logic chip, such as a central processing unit (CPU), a graphics processing unit (GPU), or an application processor (AP). In some embodiments, the non-memory device may be a measuring device, a communication device, a digital signal processor (DSP), or a system-on-chip (SoC).
Although the overall fabrication method(s) and the structures formed thereby are entirely novel, certain individual processing steps required to implement the method may utilize some conventional semiconductor fabrication techniques and conventional semiconductor fabrication tooling. These techniques and tooling will already be familiar to those having ordinary skill in the relevant art. For example, a process of forming the semiconductor device SD may be an oxidation process for forming an oxide layer, a lithography process including spin coating, exposure, and development, a thin-film deposition process, a dry or wet etching process, and a metal wiring process.
The oxidation process is a process of forming a thin and uniform silicon oxide layer by chemically reacting oxygen or water vapor with a surface of a silicon substrate at a high temperature of about 800° C. to about 1200° C. The oxidation process may include dry oxidation and wet oxidation. The dry oxidation may form an oxide layer by reacting with oxygen gas, and the wet oxidation may form an oxide layer by reacting oxygen and water vapor with each other.
The lithography process is a process of transferring a circuit pattern pre-formed on a lithography mask onto a substrate through exposure. The lithography process may be performed in an order of spin coating, exposure, and a development process.
For example, the thin-film deposition process may be any of atomic layer deposition (ALD), chemical vapor deposition (CVD), plasma-enhanced CVD (PECVD), metal organic CVD (MOCVD), physical vapor deposition (PVD), reactive pulsed laser deposition, molecular beam epitaxy, and direct current (DC) magnetron sputtering.
For example, the dry etching process may be any of reactive ion etching (RIE), deep RIE (DRIE), ion beam etching (IBE), and argon (Ar) milling. In another example, the dry etching process that may be performed on the wafer W may be atomic layer etching (ALE). In addition, the dry etching process that may be performed on the wafer W may use at least one of Cl2, HCl, CHF3, CH2F2, CH3F, H2, BCL3, SiCl4, Br2, HBr, NF3, CF4, C2F6, C4F8, SF6, O2, SO2, and COS, as etchant gas. The phrase “at least one of A, B and C,” the format of which may be used and extended throughout the present application, is intended to mean A alone, B alone, C alone, or any combination of A, B and/or C (e.g., A and B, A and C, B and C, or A and B and C).
The metal wiring process may be a process of forming a conductive wiring (metal line) to implement a circuit pattern for an operation of the semiconductor device SD. Through the metal wiring process, electrical transfer paths of ground, power, and signals for operating the semiconductor device SD may be formed. The metal wiring may include at least one metal element from among gold (Au), platinum (Pt), silver (Ag), copper (Cu), aluminum (Al), titanium (Ti), tantalum (Ta), and tungsten (W).
In some embodiments, in the process of forming the semiconductor device SD, a planarization process, such as a chemical mechanical polish (CMP) process or an etchback process, or an ion implantation process may also be performed.
The wafer W may be disposed on a stage ST. The stage ST may support the wafer W processed by using a laser. In some embodiments, the stage ST may be a vacuum chuck configured to support the wafer W by using vacuum pressure. Alternatively, the stage ST may be an electrostatic chuck configured to support the wafer W by using electrostatic force, or a chuck including a clamp means for physically supporting the wafer W.
The stage ST may include a stage driving unit (not explicitly shown, but implied) for moving and rotating the stage ST. While the wafer W is processed by using a laser, the stage ST may be configured to move and/or rotate in a state in which the wafer W is supported by an actuator included in the stage driving unit.
As a non-limiting example,
The plurality of insulating layers 110 may be disposed on the plurality of device formation areas SR and the scribe lane area SL. For example, the plurality of insulating layers 110 may surround at least part of the wiring layer 120. Each of the plurality of insulating layers 110 may include, for example, an insulating polymer, an epoxy, or a combination thereof. Each of the plurality of insulating layers 110 may be formed from a material layer including an organic polymer material. Alternatively, each of the plurality of insulating layers 110 may include an oxide or nitride. For example, each of the plurality of insulating layers 110 may include a silicon nitride. The plurality of insulating layers 110 may include the same materials as each other, or may include different materials from each other.
According to an embodiment of the inventive concept, the plurality of insulating layers 110 may include, for example, a low-k material or tetraethyl orthosilicate (TEOS). The low-k material may include a material having a lower dielectric constant than silicon oxide (SiO2). For example, the low-k material may include carbon (C), fluorine (F), boron (B), and/or a combination thereof.
For example, the wiring layer 120 may include a redistribution layer. For example, the wiring layer 120 may include Cu and/or Al. The wiring layer 120 may be disposed on the plurality of device formation areas SR. For example, at least a portion of the wiring layer 120 may be covered by one or more of the plurality of insulating layers 110.
As a non-limiting example,
The redistribution line 122 may extend in a horizontal direction (X direction and/or Y direction), and the conductive via 124 may extend in a vertical direction (Z direction). The redistribution line 122 and the conductive via 124 may be configured to transfer an electrical signal and/or heat. The redistribution pad 126 may be disposed on insulating layers 110 and may electrically connect the redistribution line 122 and the conductive via 124 to an external connection terminal 150. For example, the redistribution pad 126 may be an under bump metallization (UBM). For example, the external connection terminal 150 may be a solder ball or a solder bump.
Herein, a direction parallel to an extension direction of a main surface of the wafer W may be defined as a horizontal direction (X direction and/or Y direction), and a direction perpendicular to the horizontal direction (X direction and/or Y direction) may be defined as a vertical direction (Z direction).
In another embodiment, the external connection terminal 150 may be attached after a second dicing operation.
Referring to
The operation of forming the plurality of first grooves GR1 in the wafer W may be referred to as a first dicing operation. In the first dicing operation, the wafer W is not completely broken to separate one wafer W into a plurality of wafers W (e.g., singulated dies). The first dicing operation described above may be referred to as half-dicing because only part of the wafer W is removed.
The plurality of first grooves GR1 may be generated by a first laser device 200. The plurality of first grooves GR1 may be formed by passing through the plurality of insulating layers 110 and/or at least part of the wafer W in the vertical direction (Z direction). A front surface of the wafer W may be partially exposed through the plurality of first grooves GR1. The plurality of first grooves GR1 may be arranged to be adjacent to the front surface of the wafer W. In other words, the first laser device 200 may radiate a first laser beam LB1 adjacent to the front surface of the wafer W. For example, through the first dicing operation, the plurality of insulating layers 110 and the at least part of the wafer W may be removed. In addition, the first dicing operation may include removing other materials, such as a metal pattern, covering the plurality of insulating layers 110 in addition to the plurality of insulating layers 110.
For example, a first width W1, which is a width of each of the plurality of first grooves GR1, may be about 10 micrometers to about 100 micrometers, but is not limited to any specific width. For example, the first width W1 may be greater than or equal to about 50 micrometers.
The first laser device 200 may generate and emit the first laser beam LB1 of a wavelength having absorptivity with respect to the wafer W and the plurality of insulating layers 110. For example, the first laser beam LB1 may include a laser beam having a wavelength of an ultraviolet band.
The first laser device 200 may include a first light source 210 and a first condensation optical system 220 (e.g., collimator, lens, etc.). The first light source 210 may generate and emit the first laser beam LB1. The first laser device 200 may include one or more laser light sources. The first laser beam LB1 emitted from the first light source 210 may reach the first condensation optical system 220. The first condensation optical system 220 may condense (i.e., focus) the first laser beam LB1 inside the wafer W. The first condensation optical system 220 may be configured to be connected to a predetermined actuator (not explicitly shown, but implied) and move, so that a position of a condensing (i.e., focal) point at which the first laser beam LB1 is focused inside the wafer W may be controlled.
The first laser device 200 may be configured to break the wafer W while moving the first laser beam LB1 along the scribe lane area SL of the wafer W. For example, the first laser beam LB1 is radiated onto the wafer W in a state in which the first laser device 200 is fixed, and the stage ST may move in a horizontal direction (for example, X direction and/or Y direction) so that the first laser beam LB1 is radiated along the scribe lane area SL of the wafer W. Alternatively, in a state in which the stage ST is fixed, the first laser device 200 may emit the first laser beam LB1 to the wafer W while moving in a horizontal direction (for example, X direction and/or Y direction) along the scribe lane area SL of the wafer W. Also, in order to break the wafer W along the scribe lane area SL of the wafer W, a movement of the first laser device 200 and a movement of the stage ST may be performed concurrently.
When the insulating layer 110 includes a low-k material, a strength of the insulating layer 110 may be less than a strength of Si included in the wafer W. The term “strength” as used herein is intended to broadly refer to the ability of a material to resist deformation (e.g., plastic strain) under a load. The mechanical strength of a material is typically considered based on a maximum load that can be borne before failure occurs, taking into account stresses and strains. Accordingly, when the plurality of first grooves GR1 are formed and the wafer W and the insulating layer 110 are cut using a physical method, the insulating layer 110 may be delaminated. Thus, instead of using a physical method, the first laser device 200 may be used to cut the insulating layer 110 and form the plurality of first grooves GR1. Because the plurality of first grooves GR1 are formed, at least part of an upper surface of the wafer W may be exposed.
For example, lower surfaces GR1BS of the plurality of first grooves GR1 may be at a vertical level lower than the top surface of the wafer W. The upper surface of the wafer W may have a concavo-convex shape. Herein, the upper surface of the wafer W may denote a front surface of the wafer W on which the semiconductor device SD is formed, and a lower surface of the wafer W may denote a surface opposite to the upper surface of the wafer W. In addition, a lower surface of an element disposed on the wafer W may denote a surface closer to the upper surface of the wafer W from among two surfaces facing each other in a vertical direction (Z direction). However, lower surfaces GR1BS of the plurality of first grooves GR1 may have a relatively high surface roughness (Ra).
Surface roughness Ra may provide a general measure of the height of the texture across a surface (measured in a Z direction). More particularly, surface roughness Ra may be defined as an average of how far each point on the surface deviates in height from a mean height.
Immediately after the first dicing operation is performed, a cleaning process using deionized (DI) water or the like may be further performed.
Referring to
A second laser device 300 may generate and emit a second laser beam LB2. The second laser device 300 may radiate the second laser beam LB2 adjacent to the front surface of the wafer W. The second laser device 300 may radiate the second laser beam LB2 to the lower surfaces GR1BS of the plurality of first grooves GR1 (see
The second laser device 300 may include a second light source 310 and a second condensation optical system 320. The second light source 310 and the second condensation optical system 320 may be approximately similar to the first light source 210 and the first condensation optical system 220, respectively.
Although described below, when roughness (Ra) of the lower surface GR2BS of each of the plurality of second grooves GR2 is less than or equal to about 0.08 micrometers, it may be easy to perform a stealth dicing process. Stealth dicing is a technology that focuses a laser beam of a prescribed wavelength that permeates through materials, focuses internally and forms a starting point for cracking the wafer W along its scribe lane area SL, then applies external stress to the wafer to separate the individual dies (SD). In more detail, when the roughness (Ra) of the lower surface GR2BS of each of the plurality of second grooves GR2 is less than or equal to about 0.08 micrometers, it may be easy to condense (i.e., focus) laser light on a point or region within (i.e., internal to) the wafer W with a third laser device 400 (
Referring to
The internal crack IB of the wafer W may be formed by a third laser beam LB3 of the third laser device 400. The internal crack IB may have an elongated conical shape in which a width in a vertical direction (Z direction) is greater than a width in a horizontal direction (X direction and/or Y direction). An operation in which the internal crack IB is formed in the wafer W may be referred to as an operation in which a reformed pattern is formed.
The third laser device 400 may include a third light source 410 and a third condensation optical system 420. The third light source 410 may generate and emit the third laser beam LB3. The third condensation optical system 420 may focus the third laser beam LB3 of the third light source 410 at positions set inside the wafer W. The third condensation optical system 420 may include a single lens or a plurality of lenses.
For example, the third laser device 400 may form the internal crack IB within the wafer W by using a stealth dicing technique. Stealth dicing is a process of separating the wafer W on which the semiconductor device SD is formed with high precision and high speed. As previously stated, stealth dicing is a technique of focusing a laser beam of a wavelength band (i.e., a wavelength band in which the wafer W has low absorptivity) in which the laser beam may transmit through a surface of the wafer W to a location inside the wafer W through a surface of the wafer W.
In the stealth dicing technique, a laser beam may be repeatedly radiated with pulses lasting for a very short time (e.g., 1 μs or less), and focused on a narrow area on the wafer W. In other words, the third laser beam LB3 may have a high peak power density, for example, about 1×108 W/cm2, spatially (through focusing) and temporally (through pulsing) near a focal point set inside the wafer W. The laser beam of the high peak power density causes a non-linear absorption effect on the wafer W near the focal point, so that the laser beam transmitting through the surface of the wafer W may be absorbed at high absorptivity near the focal point inside the wafer W. Accordingly, high-density defects (for example, a dislocation) may occur in a portion of the wafer W that absorbs the laser beam, and vertical cracks of the wafer W may be easily generated.
The first laser device 200, the second laser device 300, and the third laser device 400 may be different from each other, since each of the laser devices may be configured for a different function. For example, the first laser device 200 may be a laser device for forming the plurality of first grooves GR1 in the wafer W. The second laser device 300 may be a laser device for planarizing the lower surface GR1BS of each of the plurality of first grooves GR1. The third laser device 400 may be a laser device for forming the internal cracks IB inside the wafer W. In one or more embodiments, the same light source (e.g., 210, 310, 410) may be used with different condensation optical systems (e.g., 220, 320, 420) configured to perform a respective one of the functions.
For example, a horizontal condensation area of the first laser beam LB1 of the first laser device 200 may be greater than a horizontal condensation area of the third laser beam LB3 of the third laser device 400. A horizontal condensation area of the second laser beam LB2 of the second laser device 300 may be greater than the horizontal condensation area of the third laser beam LB3 of the third laser device 400. For example, the horizontal condensation areas of the first laser beam LB1 and the second laser beam LB2 may be similar to a horizontal area of each of the plurality of first grooves GR1. A wavelength of the first laser beam LB1 may be shorter than a wavelength of the third laser beam LB3. A wavelength of the second laser beam LB2 may be shorter than the wavelength of the third laser beam LB3.
Accordingly, the first laser device 200 and the second laser device 300 may radiate the first laser beam LB1 and the second laser beam LB2 to a relatively wide horizontal area, respectively, and the third laser device 400 may intensively radiate the third laser beam LB3 to a relatively narrow horizontal area.
In an embodiment of the inventive concept, the plurality of internal cracks IB may be formed inside the wafer W. The plurality of internal cracks IB may be spaced apart from each other in a horizontal direction (X direction and/or Y direction). For example, the plurality of internal cracks IB may have the same horizontal separation distances therebetween and may be arranged inside the wafer W.
In some embodiments, in order to reduce a thickness of the wafer W before the internal crack IB of the wafer W is formed, a pre-grinding process may be performed on the lower surface of the wafer W.
Referring to
The dicing tape may be a film having adhesive force capable of fixing or supporting the wafer W when the wafer W is diced. The dicing tape may include a base film including polymer resin and an adhesive layer provided on one surface of the base film. For example, the base film may include polyvinyl chloride (PVC), polyolefin (PO), polyethylene terephthalate (PET), or the like. In addition, the adhesive layer may include acryl-based resin or the like.
The operation of separating the plurality of semiconductor devices SD may be referred to as the second dicing operation. Through the second dicing operation, the wafer W may be separated into a plurality of wafers W (i.e., singulated dies). In other words, through the second dicing operation, the wafer W may be completely broken. Accordingly, the wafer W and the semiconductor device SD may be separated into a plurality of semiconductor device chips SC.
The wafer W and the semiconductor devices SD may be separated into the plurality of semiconductor device chips SC, and the plurality of semiconductor device chips SC and the dicing tape DT may be separated from each other. For example, when the dicing tape DT includes an ultraviolet irradiation type, ultraviolet (UV) rays may be radiated to lower surfaces of the plurality of semiconductor device chips SC to cure an adhesive layer, thereby reducing adhesive force and peeling off the dicing tape DT from several semiconductor device chips SC.
In another embodiment, the second dicing operation may include at least one of a laser cutting process, a dry etching process, a wet etching process, a plasma process, and a process using a blade.
The semiconductor device SD that is separated may be packaged in operation S600. The packaging process may include a wire bonding process, a molding process, a marking process, a solder ball mounting process, and the like.
Operations S100 to S500 described above may be included in a wafer dicing method. In addition, when the wafer dicing method includes operation S600, the wafer dicing method may be referred to as a method of manufacturing a semiconductor device.
A general wafer dicing method and/or a method of manufacturing a semiconductor device does not include a step of planarizing a lower surface of a plurality of first grooves, and thus, when stealth dicing is performed, it is relatively difficult to focus a laser beam inside a wafer. When stealth dicing is performed in a state in which lower surfaces of a plurality of second grooves are not planarized, the laser beam may be irregularly reflected (e.g., scattered) from the lower surfaces of the plurality of first grooves.
On the other hand, the wafer dicing method and/or the method of manufacturing the semiconductor device according to one or more embodiments of the inventive concept includes an operation of irradiating the lower surfaces GR1BS of the plurality of first grooves GR with a laser beam of the second laser device 300, so as to planarize the lower surfaces GR1BS of the plurality of first grooves GR1 and form the plurality of second grooves GR2. Accordingly, when a stealth dicing process is performed with the third laser device 400 through the lower surfaces GR2BS of the plurality of second grooves GR2 which have been planarized, transmittance of the third laser beam LB3 in the wafer W may increase. Thus, the third laser beam LB3 may be relatively easily focused on a point or region inside the wafer W. In addition, when the stealth dicing process is performed with the third laser device 400 through the lower surfaces GR2BS of the plurality of second grooves GR2, a rate at which irregular reflection of the third laser beam LB3 occurs at the lower surfaces GR2BS of the plurality of second grooves GR2 may decrease. Accordingly, the internal crack IB may be easily formed inside the wafer W.
Referring to
Although not specifically shown in
Referring to
In an embodiment of the inventive concept, the polishing apparatus 500 may rotate about a shaft extending in a vertical direction (Z direction) and cut at least a portion of the wafer W. For example, the polishing apparatus 500 may rotate about a shaft extending in the vertical direction (Z direction) and cut the lower surfaces GR1BS of the plurality of first grooves GR1. The polishing apparatus 500 may be coupled to a rotation shaft RA, and may be configured to rotate based on rotation of the rotation shaft RA. In an embodiment, when the polishing apparatus 500 is viewed from a plane (X-Y plane) perpendicular to the vertical direction (Z direction) which is an extension direction of the rotation shaft RA, the polishing apparatus 500 may have a disk shape.
For example, a second width W2, which is a width of each of the plurality of second grooves GR2a, may be about 10 micrometers to about 100 micrometers, although embodiments of the present inventive concept are not limited to this specific range of widths. For example, the second width W2 may be greater than or equal to about 70 micrometers. For example, the first width W1 and the second width W2 of
Referring to
The side surface SCSS of the semiconductor device chip SC may include an upper surface SCSS1 and a lower surface SCSS2, which are spaced apart from each other in a horizontal direction (X direction and/or Y direction). In addition, the semiconductor device chip SC may include a connection surface SCCS connecting the upper surface SCSS1 and the lower surface SCSS2 to each other. Each of the upper surface SCSS1 and the lower surface SCSS2 may extend in the vertical direction (Z direction), and the connection surface SCCS may extend in the horizontal direction (X direction and/or Y direction).
For example, the upper surface SCSS1 may be at least a portion of side surfaces of the second grooves GR2 and GR2a, the connection surface SCCS may be at least a portion of the lower surfaces GR2BS and GR2aBS of the second grooves GR2 and GR2a, respectively, and the lower surface SCSS2 may be at least a portion of a broken surface formed by the second dicing process. Accordingly, the upper surface SCSS1 may be referred to as a non-planarization surface, the connection surface SCCS may be referred to as a planarized surface, and the lower surface SCSS2 may be referred to as a stealth dicing surface.
At least a portion of the upper surface SCSS1 may be located at the same vertical level as the insulating layer 110 and the wiring layer 120 (i.e., coplanar), and at least a portion of each of the connection surface SCCS and the lower surface SCSS2 may be located at the same vertical level as the semiconductor device SD. The upper surface SCSS1 may be at least one side surface of each of the insulating layer 110 and/or the wiring layer 120. The connection surface SCCS may be at least a portion of an upper surface of the semiconductor device SD. The lower surface SCSS2 may be at least a portion of a side surface of the semiconductor device SD. The upper surface SCSS1 may be located at a higher vertical level than the lower surface SCSS2.
The upper surface SCSS1, the connection surface SCCS, and the lower surface SCSS2 may have different roughnesses from each other. For example, the roughness of the lower surface SCSS2 may be less ness than each of the roughness of the upper surface SCSS1 and the roughness of the connection surface SCCS. In addition, the roughness of the connection surface SCCS may be less than or equal to the roughness of the upper surface SCSS1. For example, the roughness (Ra) of the connection surface SCCS may be less than or equal to about 0.08 micrometers, and the roughness (Ra) of the lower surface SCSS2 may be less than or equal to about 0.01 micrometers.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms “a,” “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” and/or “comprising,” when used in this specification, specify the presence of stated features, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, steps, operations, elements, components, and/or groups thereof. Spatially descriptive terms such as “above,” “below,” “upper” and “lower” may be used herein to indicate a position of elements, structures or features relative to one another as illustrated in the figures, rather than absolute positioning. Thus, the semiconductor device may be otherwise oriented (e.g., rotated 90 degrees or at other orientations), and the spatially relative descriptions used herein may be interpreted accordingly.
It will also be understood that when an element such as a layer, region or substrate is referred to as being “atop,” “above,” “on” or “over” another element, it is broadly intended that the element be in direct contact with the other element or intervening elements can also be present. In contrast, when an element is referred to as being “directly on” or “directly over” another element, it is intended that there are no intervening elements present. Likewise, it should be appreciated that when an element is referred to as being “connected” or “coupled” to another element, it can be directly connected or coupled to the other element or intervening elements can be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, there are no intervening elements present.
While the inventive concept has been particularly shown and described with reference to embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the following claims.
| Number | Date | Country | Kind |
|---|---|---|---|
| 10-2022-0162032 | Nov 2022 | KR | national |
