Wafer level chip scale package (WLCSP) with high reliability against thermal stress

Abstract

A wafer level chip scale package includes a semiconductor chip having a plurality of pads; a lower insulation layer having a high Young's modulus of 1˜5 GPa formed on the semiconductor chip to expose the plurality of pads; a plurality of metal patterns formed on the lower insulation layer to be connected to the respective pads; an upper insulation layer having a high Young's modulus of 1˜5 GPa formed on the lower insulation layer and the metal patterns to partially expose the metal patterns; and a plurality of solder balls formed on exposed portions of the metal patterns.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a cross-sectional view illustrating a conventional wafer level chip scale package.

FIGS. 2A through 2D are cross-sectional views sequentially illustrating a procedure in which cracks are formed in a metal pattern when conducting a thermal cycling test for the wafer level chip scale package shown in FIG. 1.

FIG. 3 is a cross-sectional view illustrating a wafer level chip scale package in accordance with a first embodiment of the present invention.

FIG. 4 is a plan view illustrating a wafer level chip scale package in accordance with a second embodiment of the present invention.

FIG. 5 is a cross-sectional view illustrating the semiconductor chip package of FIG. 4.

Claims

1. A wafer level chip scale package comprising: a semiconductor chip having a plurality of pads;a lower insulation layer having a high Young's modulus in the range of 1-5 GPa formed on the semiconductor chip to expose the plurality of pads;a plurality of metal patterns formed on the lower insulation layer, each metal pattern connected to one of the pads;a upper insulation layer having a high Young's modulus in the range of 1-5 GPa formed on the lower insulation layer and the metal patterns to partially expose the metal patterns; anda plurality of solder balls formed on the exposed portions of the metal patterns.

2. The wafer level chip scale package as set forth in claim 1, wherein the lower and upper insulation layers include an epoxy-based material or a rubber-based material or a silicon-based material or polyimide-based material or a benzocyclobutene-based material.

3. The wafer level chip scale package as set forth in claim 1, wherein the plurality of pads are positioned near the edges of the semiconductor chip, and the plurality of solder balls are positioned closer to the center portion of the semiconductor chip.

4. The wafer level chip scale package as set forth in claim 3, wherein the plurality of pads are positioned near the two or four edges of the semiconductor chip, and the plurality of solder balls are positioned closer to the center portion of the semiconductor chip.

5. The wafer level chip scale package as set forth in claim 1, wherein the plurality of pads are positioned on or near the center portion of the semiconductor chip,wherein a first subset of the solder balls and a second subset of the solder balls are positioned on the semiconductor chip such that the each solder ball of the first subset is located closer to the nearest one of the pads than the solder ball of the second subset that is located nearest the solder ball of the first subset,wherein each solder ball of the first subset is connected to one of the pads by one of the metal patterns formed to extend in a direction substantially free of sharp bending, andwherein each solder ball of the second subset is connected to one of the pads by one of the metal patterns formed in a substantially curved line.