Patent Application
20230011786
The present application is based upon and claims the benefit of priority to Japanese Patent Application No. 2021-114224, filed Jul. 9, 2021, the entire contents of which are incorporated herein by reference.
The present invention relates to a wiring substrate and a method for manufacturing the wiring substrate.
Japanese Patent Application Laid-Open Publication No. 2010-40625 describes a wiring substrate having a wiring layer having fine patterns. The entire contents of this publication are incorporated herein by reference.
According to one aspect of the present invention, a wiring substrate includes an insulating layer including resin and filler particles, and an embedded wiring layer including wirings and embedded in the insulating layer such that the wirings are filling grooves formed on a surface of the insulating layer, respectively. The embedded wiring layer is formed such that the smallest line width of the wirings in the embedded wiring layer is in the range of 2 μm to 8 μm, and the insulating layer is formed such that the maximum particle size of the filler particles is 50% or less of the smallest line width of the wirings in the embedded wiring layer.
According to another aspect of the present invention, a method for manufacturing a wiring substrate includes forming an insulating layer including resin and filler particles, and forming an embedded wiring layer including wirings in the insulating layer such that the embedded wiring layer is embedded in the insulating layer and that the wirings are filling grooves formed on a surface of the insulating layer, respectively. The forming of the embedded wiring layer includes forming the grooves in the insulating layer such that the smallest line width of the grooves is set in the range of 2 μm to 8 μm, forming a metal film layer covering the inner surfaces of the grooves, and forming a plating film layer on the metal film layer, and the forming of the insulating layer includes setting the maximum particle size of the filler particles to 50% or less of the smallest line width of the wirings in the embedded wiring layer.
A more complete appreciation of the invention and many of the attendant advantages thereof will be readily obtained as the same becomes better understood by reference to the following detailed description when considered in connection with the accompanying drawings, wherein:
Embodiments will now be described with reference to the accompanying drawings, wherein like reference numerals designate corresponding or identical elements throughout the various drawings.
A wiring substrate according to an embodiment of the present invention is described with reference to the drawings. The drawings to be referred to below are drawn such that features according to an embodiment of the present invention can be easily understood, without intending to show exact proportions of structural elements.
As illustrated in
In the description of the wiring substrate of the present embodiment, a side farther from the core insulating layer 101 is referred to as “upper,” “upper side,” “outer side,” or “outer,” and a side closer to the core insulating layer 101 is referred to as “lower,” “lower side,” “inner side,” or “inner.” Further, for the conductor layers and the insulating layers, a surface facing the opposite side with respect to the core substrate 100 is also referred to as an “upper surface,” and a surface facing the core substrate 100 side is also referred to as a “lower surface.” Therefore, for example, in the description of the structural elements of the first build-up part 10 and the second build-up part 20, a side farther from the core substrate 100 is also referred to as an “upper side,” “upper-layer side,” or “outer side,” or simply “upper” or “outer,” and a side closer to the core substrate 100 is also referred to as a “lower side,” “lower-layer side,” or “inner side,” or simply “lower” or “inner.”
A solder resist layer 110 is formed on the first build-up part 10. A solder resist layer 210 is formed on the second build-up part 20. Openings (110a) are formed in the solder resist layer 110, and conductor pads (12p) of the outermost conductor layer 12 in the first build-up part 10 are exposed from the openings (110a). Openings (210a) are formed in the solder resist layer 210, and conductor pads (22p) of the outermost conductor layer 22 in the second build-up part 20 are exposed from the openings (210a).
An outermost surface of the first build-up part 10 formed by exposed surfaces of the conductor layer 12 (the conductor pads (12p)) and the solder resist layer 110 is referred to as a first surface (FA). An outermost surface of the second build-up part 20 formed by exposed surfaces of the solder resist layer 210 and the conductor layer 22 (the conductor pads (22p)) is referred to as a second surface (FB). That is, the wiring substrate 1 has the first surface (FA) and the second surface (FB) on the opposite side with respect to the first surface (FA) as two surfaces that extend in a direction orthogonal to a thickness direction of the wiring substrate 1.
In the insulating layer 101 of the core substrate 100, through-hole conductors 103 are formed connecting the conductor layer 102 that forms the one surface (F1) of the core substrate 100 and the conductor layer 102 that forms the other surface (F2) in the core substrate 100. In the insulating layers (11, 111, 21), via conductors (13, 23) connecting the conductor layers sandwiching the insulating layers (11, 111, 21) are formed.
The conductor layers (102, 12, 112, 22), the via conductors (13, 23), and the through-hole conductors 103 are formed using any metal such as copper or nickel, and, for example, are each formed of a metal foil such as a copper foil and/or a metal film formed by plating or sputtering. The conductor layers (102, 12, 112, 22), the via conductors (13, 23), and the through-hole conductors 103 are each illustrated in
Each of the conductor layers (102, 12, 112, 22) of the wiring substrate 1 is patterned to have predetermined conductor patterns. In particular, in the illustrated example, as will be described in detail later, the conductor layer 112 is formed as an embedded wiring layer having a form of being embedded inward from an outer surface of the insulating layer 111 and is formed to have wirings (FW) formed in relatively fine patterns. Further, the outermost conductor layer 12 of the first build-up part 10 is formed to have patterns including the conductor pads (12p). The conductor pads (12p) are formed such that a component (not illustrated in the drawings) to be mounted on the wiring substrate 1 when the wiring substrate 1 is used can be placed. That is, the conductor pads (12p) are component mounting pads to be used as connecting parts when an external component is mounted on the wiring substrate 1, and the first surface (FA) of the wiring substrate 1 can be a component mounting surface on which a component can be mounted. Electrodes of an electronic component can be electrically and mechanically connected to the component mounting pads (conductor pads) (12p), for example, via a bonding material (not illustrated in the drawings) such as solder. Examples of components that can be mounted on the wiring substrate 1 include electronic components such as active components such as semiconductor integrated circuit devices and transistors.
The second surface (FB), which is a surface on the opposite side with respect to the first surface (FA) of the wiring substrate 1 in the example of
Each of the insulating layers (101, 11, 111, 21) is formed, for example, using an insulating resin such as an epoxy resin, a bismaleimide triazine resin (BT resin) or a phenol resin. Each of the insulating layers may contain a reinforcing material (core material) such as a glass fiber and/or inorganic filler such as silica or alumina. In particular, in the illustrated example, as will be described in detail later, dimensions of filler particles contained in the insulating layer 111, in which the conductor layer 112 is embedded as an embedded wiring layer, have predetermined values that are limited in relation to a line width of the wirings (FW) in the conductor layer 112. Each of the solder resist layers (110, 210) is formed using, for example, a photosensitive epoxy resin or polyimide resin, or the like.
The wiring substrate of the embodiment has at least one conductor layer in a form of an embedded wiring layer that includes fine wiring patterns having relatively small line width and inter-line distance. Specifically, in the illustrated wiring substrate 1, the conductor layer 112 forming the first build-up part 10 is an embedded wiring layer in a form of being embedded in the insulating layer 111 from an outer side, and has the wirings (FW) formed in relatively fine patterns. In addition, in the illustrated example, the embedded wiring layer (conductor layer) 112 includes, in addition to the wirings (FW), land parts (L) that can be connected to the upper-side conductor layer 12 via via conductors 13.
The wirings (FW) are formed as wiring patterns having relatively small line widths and inter-line distances. The wirings (FW) are illustrated in the cross-sectional view of
In the wiring substrate 1 of the illustrated example, among the conductor layers forming the first build-up part 10, the conductor layer 112 on the one-layer inner side of the outermost conductor layer 12 is formed as an embedded wiring layer. However, it is also possible that multiple conductor layers of such a form are formed in the wiring substrate. For example, in second build-up part 20, the conductor layer 22 of the same rank as the conductor layer 112 in the first build-up part 10 can be formed as an embedded wiring layer, and the insulating layer 21 of the same rank as the insulating layer 111 can be formed to have the same filler dimensions and filler content rate as the insulating layer 111. The term “rank” is a number assigned to each of the conductor layers (12, 112, 22) when the number that increases by 1 for each layer starting from the core substrate 100 side is sequentially assigned starting from 1 to each of the multiple conductor layers (12, 112, 22) laminated in each of the first build-up part 10 and the second build-up part 20. Due to that the same insulating layer and embedded wiring layer as those in the first build-up part 10 are formed in the second build-up part 20 at the same ranks as those in the first build-up part 10, it may be possible that the symmetry of the wiring substrate in the thickness direction is improved and warpage of the wiring substrate is suppressed.
Next, with reference to
The insulating layer 111 contains multiple granular filler particles (Fa, Fb, Fc). As illustrated in the drawings, the multiple granular filler particles (Fa, Fb, Fc) contained in the insulating layer 111 can have different particle sizes. Examples of these filler particles include particles of inorganic substances such as silicon oxide, alumina, or mullite. It is also possible that the filler particles are organic particles such as polyimide particles. The term “particle size” in the description of filler particles is a linear distance between two most distant points on an outer surface of a filler particle.
As described in detail in the description of a manufacturing method to be described later, the grooves (1g) formed in the insulating layer 111 can be formed by processing by laser irradiation from above the insulating layer 111, and a subsequent desmear treatment using a chemical solution. At the stage of processing with laser, it may be possible that filler particles are exposed on inner wall surfaces of the grooves (1g) and protrude into the grooves (1g). Therefore, as illustrated in the leftmost wiring (FW) among the four illustrated wirings (FW), it may be possible that the metal film layer (112a) covering the inner wall surfaces of the grooves (1g) is formed following shapes of filler particles protruding into the grooves (1g) and a distortion in shapes of the wirings (FW) occurs. Further, at the stage of the desmear treatment following the processing with laser, it may be possible that the chemical solution infiltrates into interfaces between filler particles exposed on inner sides of the grooves (1g) and the resin surrounding the filler particles, and thus, peeling between the filler particles and the resin occurs and the filler particles fall off from the resin. Therefore, for example, as in the rightmost wiring (FW) among the four illustrated wirings (FW), it may be possible that recesses corresponding to shapes of filler particles are formed on the inner wall surfaces of the grooves (1g) and the metal film layer (112a) is formed along shapes of the recesses.
In particular, when a distortion occurs in the wirings (FW) due to the protrusion of the filler particles into the grooves (1g), cross-sectional areas of the wirings (FW) can be partially reduced. Therefore, there is a risk that impedance of the wirings (FW) may locally increase, which may cause a transmission failure of a signal transmitted via the wirings (FW). Further, there is a risk that a local increase in impedance of the wirings (FW) may cause partial overheating of the wirings (FW) with energization and may also cause a disconnection of the wirings (FW) and damage to surrounding structural elements. Further, when the wirings (FW) are formed following the above-described recesses, there is a possibility that the cross-sectional areas of the wirings (FW) may partially increase, causing a local decrease in the impedance of the wirings (FW). Therefore, there is a risk of causing a transmission failure of a signal transmitted via the wirings (FW).
In the wiring substrate of the present embodiment, particle sizes of filler particles contained in an insulating layer in which a wiring layer having the form of the embedded wiring layer is embedded are limited in a maximum value thereof in relation to dimensions of wirings contained in the embedded wiring layer. Specifically, in the multiple filler particles (Fa, Fb, Fc) contained in the insulating layer 111 in the wiring substrate 1, a particle size (DM) of the largest filler particle (Fa) is 50% or less of the line width (W) of the wirings (FW). By limiting the maximum particle size (DM) of the multiple filler particles contained in the insulating layer 111 in this way, even when a distortion in the wirings occurs due to filler particles exposed on the inner wall surfaces of the grooves (1g), a degree of a change in the cross-sectional areas of the wirings (FW) can be relaxed. A transmission failure of a signal transmitted via the embedded wiring layer 112 can be suppressed, and occurrence of a defect such as a disconnection of the wirings (FW) can also be suppressed.
In addition to limiting the maximum particle size (DM) of the multiple filler particles (Fa, Fb, Fc) contained in the insulating layer 111 to 50% or less of the line width (W) as described above, as illustrated in
The wirings (FW) having relatively fine patterns in the embedded wiring layer 112 can have a thickness (T) of 5 μm or more and 10 μm or less as a smallest thickness thereof. From a point of view of suppressing a degree of a change in cross-sectional areas of the wirings (FW), the maximum particle size (DM) of the multiple filler particles contained in the insulating layer 111 is preferably 40% or less of the thickness (T) of the wirings (FW). A local change in impedance of the wirings (FW) can be effectively suppressed. As a specific example, when the wirings (FW) are formed to have a (line/space) (L/S) of, for example, (5 μm)/(5 μm) and a smallest thickness (T) of 5 the maximum particle size (DM) of the multiple filler particles contained in the insulating layer 111 is 2 μm or less, and preferably can be, for example, 1 μm.
It may be possible that the fine wirings (FW) are signal-transmission wirings, and the signals can be high frequency signals. Therefore, the insulating layer 111 in which the conductor layer 112 is embedded preferably has excellent high frequency characteristics. When an insulating layer in contact with a wiring has relatively high permittivity and dielectric loss tangent, a dielectric loss (transmission loss) of a high frequency signal transmitted via the wiring is relatively large. The dielectric loss tends to be large when the frequency of the signal is high. In particular, when a high frequency signal in the microwave or millimeter wave region is transmitted, the dielectric loss can be significantly large. Therefore, for the insulating layer 111 in which the conductor layer 112 is embedded, a material having relatively small permittivity and dielectric loss tangent is preferably used, and, for example, at a frequency of 1 GHz, a relative permittivity is preferably 3.5 or less and a dielectric loss tangent is preferably 0.005 or less.
Regarding the relative permittivity and the dielectric loss tangent of an insulating layer described above, it is more preferable that the insulating layer 11 directly above the conductor layer 112 similarly has a relative permittivity of 3.5 or less and a dielectric loss tangent of 0.005 or less at a frequency of 1 GHz. Since all the insulating layers in contact with the conductor layer 112 have excellent high frequency characteristics, the conductor layer 112 can have even more excellent signal transmission quality. Therefore, a material having relatively small permittivity and dielectric loss tangent is preferably used for the filler particles contained in the insulating layer 111 and the insulating layer 11 that are in contact with the embedded wiring layer 112. For example, filler particles containing silicon oxide or boron nitride can be preferably used.
With reference to
Next, as illustrated in
Next, as illustrated in 4C, the insulating layer 111 is laminated on the one surface (F1) side of the core substrate 100, and the insulating layer 21 is laminated on the conductor layer 22 on the other surface (F2) side. Through holes (13g) are formed in the insulating layer 111 by laser processing. The through holes (13g) are formed at positions where the via conductors 13 (see
For the formation of the insulating layer 111, a film-like resin containing multiple granular filler particles having a maximum particle size of 50% or less of the width of the grooves (1g) for the wirings to be subsequently described with reference to
Next, as illustrated in
Next, as illustrated in
Next, as illustrated in
Next, as illustrated in
Next, as illustrated in
By the above processes, the formation of the wiring substrate 1 is completed. A protective film (not illustrated in the drawings) may be formed on the exposed surface of each of the conductor pads (12p, 22p). For example, the protective film formed of Ni/Au, Ni/Pd/Au, Sn or the like can be formed by plating. An OSP film may be formed by spraying an organic material.
A wiring substrate according to an embodiment of the present invention is not limited to those having the structures illustrated in the drawings and those having the structures, shapes, and materials exemplified herein. For example, one or more conductor layers each having a form of an embedded wiring layer having fine wirings can be provided among the conductor layers forming the wiring substrate. In the description of the embodiment, an example is illustrated in which fine wirings having the same depth (thickness) are provided in one embedded wiring layer. However, multiple wirings having different thicknesses may be formed in the same embedded wiring layer. Each of the first build-up part and the second build-up part may include any number of insulating layers and any number of conductor layers. The number of insulating layers and conductor layers of the first build-up part and the number of insulating layers and conductor layers of the second build-up part formed on both sides of the core substrate may be different from each other.
A method for manufacturing a wiring substrate according to an embodiment of the present invention is not limited to the method described with reference to the drawings. Conditions, processing orders and the like of the method may be appropriately modified. Depending on a structure of an actually manufactured wiring substrate, some of the processes may be omitted, or other processes may be added.
Japanese Patent Application Laid-Open Publication No. 2010-40625 describes a wiring substrate having a wiring layer having fine patterns. By forming grooves with laser in a resin layer formed of, for example, an epoxy resin that forms an interlayer insulating layer, and filling the grooves with a conductor, fine wiring patterns having a form of being embedded in the resin layer are formed.
It is thought that, in the wiring layer having fine patterns formed in the wiring substrate described in Japanese Patent Application Laid-Open Publication No. 2010-40625, wirings have relatively small widths, which may cause a partial disconnection of the wirings or a transmission failure of an electrical signal transmitted via the wirings.
A wiring substrate according to an embodiment of the present invention includes: an insulating layer that contains multiple granular filler particles; and an embedded wiring layer that fills grooves formed on one of opposing surfaces in a thickness direction of the insulating layer. A smallest line width of wirings included in the embedded wiring layer is 2 μm or more and 8 μm or less, and a maximum particle size of the multiple filler particles is 50% or less of the line width.
A method for manufacturing a wiring substrate according to an embodiment of the present invention includes: forming an insulating layer containing multiple granular filler particles; and forming an embedded wiring layer in the insulating layer. The forming of the embedded wiring layer includes: forming grooves in the insulating layer; forming a metal film layer that covers inner surfaces of the grooves; and forming a plating film layer on the metal film layer. The forming of the grooves is performed such that a smallest width of the grooves is 2 μm or more and 8 μm or less. The insulating layer is formed using a resin containing the multiple filler particles having a maximum particle size of 50% or less of the width.
According to an embodiment of the present invention, a highly reliable wiring substrate and a method for manufacturing the wiring substrate are provided that allow a disconnection or a transmission failure of a signal in wirings in an embedded wiring layer to be suppressed.
Obviously, numerous modifications and variations of the present invention are possible in light of the above teachings. It is therefore to be understood that within the scope of the appended claims, the invention may be practiced otherwise than as specifically described herein.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2021-114224 | Jul 2021 | JP | national |
