Albert M. Chu

Person

Nashua, NH, US

People

Patents Grantslast 30 patents

Information Patent Grant
Staggered stacked semiconductor devices
- Patent number 12,142,656
- Issue date Nov 12, 2024
- International Business Machines Corporation
- Albert Chu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Ultra-short-height standard cell architecture
- Patent number 12,001,772
- Issue date Jun 4, 2024
- International Business Machines Corporation
- Albert Chu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Interconnects on multiple sides of a semiconductor structure
- Patent number 11,658,116
- Issue date May 23, 2023
- International Business Machines Corporation
- Junli Wang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Field effect transistor
- Patent number 11,355,401
- Issue date Jun 7, 2022
- International Business Machines Corporation
- Effendi Leobandung
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
3D vertical FET with top and bottom gate contacts
- Patent number 11,031,296
- Issue date Jun 8, 2021
- International Business Machines Corporation
- Brent A. Anderson
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Fabricating tapered semiconductor devices
- Patent number 10,832,971
- Issue date Nov 10, 2020
- International Business Machines Corporation
- Rajasekhar Venigalla
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Multi-patterning techniques for fabricating an array of metal lines...
- Patent number 10,755,969
- Issue date Aug 25, 2020
- International Business Machines Corporation
- Albert Chu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Cell placement in a circuit with shared inputs and outputs
- Patent number 10,755,017
- Issue date Aug 25, 2020
- International Business Machines Corporation
- Brent A. Anderson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Vertical transport logic circuit cell with shared pitch
- Patent number 10,742,218
- Issue date Aug 11, 2020
- International Business Machines Corpoartion
- Brent A. Anderson
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Reliable gate contacts over active areas
- Patent number 10,693,005
- Issue date Jun 23, 2020
- International Business Machines Corporation
- Emre Alptekin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
4T static random access memory bitcell retention
- Patent number 10,614,877
- Issue date Apr 7, 2020
- International Business Machines Corporation
- Albert Chu
- G11 - INFORMATION STORAGE
Information Patent Grant
3D vertical FET with top and bottom gate contacts
- Patent number 10,529,625
- Issue date Jan 7, 2020
- International Business Machines Corporation
- Brent A. Anderson
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Standard cell architecture with at least one gate contact over an a...
- Patent number 10,424,574
- Issue date Sep 24, 2019
- International Business Machines Corporation
- Albert M. Chu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Standard cell architecture with at least one gate contact over an a...
- Patent number 10,424,576
- Issue date Sep 24, 2019
- International Business Machines Corporation
- Albert M. Chu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Metal fill optimization for self-aligned double patterning
- Patent number 10,381,338
- Issue date Aug 13, 2019
- International Business Machines Corporation
- Albert M. Chu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Reliable gate contacts over active areas
- Patent number 10,381,480
- Issue date Aug 13, 2019
- International Business Machines Corporation
- Emre Alptekin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
3D vertical FET with top and bottom gate contacts
- Patent number 10,361,128
- Issue date Jul 23, 2019
- International Business Machines Corporation
- Brent A. Anderson
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
3D vertical FET with top and bottom gate contacts
- Patent number 10,074,570
- Issue date Sep 11, 2018
- International Business Machines Corporation
- Brent A. Anderson
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Ultra dense vertical transport FET circuits
- Patent number 9,954,529
- Issue date Apr 24, 2018
- International Business Machines Corporation
- Brent A. Anderson
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
High density vertical field effect transistor multiplexer
- Patent number 9,859,898
- Issue date Jan 2, 2018
- International Business Machines Corporation
- Brent A. Anderson
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Vertical transistors with merged active area regions
- Patent number 9,761,712
- Issue date Sep 12, 2017
- International Business Machines Corporation
- Brent A. Anderson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Metal fill optimization for self-aligned double patterning
- Patent number 9,735,029
- Issue date Aug 15, 2017
- International Business Machines Corporation
- Albert M. Chu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Ultra dense vertical transport FET circuits
- Patent number 9,680,473
- Issue date Jun 13, 2017
- International Business Machines Corporation
- Brent A. Anderson
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Read only memory (ROM) with redundancy
- Patent number 9,460,811
- Issue date Oct 4, 2016
- GLOBALFOUNDRIES Inc.
- George M. Braceras
- G11 - INFORMATION STORAGE
Information Patent Grant
Generating place and route abstracts
- Patent number 9,424,386
- Issue date Aug 23, 2016
- International Business Machines Corporation
- Albert M. Chu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and circuits for generating physically unclonable function
- Patent number 9,202,554
- Issue date Dec 1, 2015
- International Business Machines Corporation
- Albert M. Chu
- G11 - INFORMATION STORAGE
Information Patent Grant
Embedded photon emission calibration (EPEC)
- Patent number 9,052,356
- Issue date Jun 9, 2015
- International Business Machines Corporation
- Albert M. Chu
- G01 - MEASURING TESTING
Information Patent Grant
Process variation skew in an SRAM column architecture
- Patent number 8,934,312
- Issue date Jan 13, 2015
- International Business Machines Corporation
- Albert M. Chu
- G11 - INFORMATION STORAGE
Information Patent Grant
Systems and methods for determining adjustable wafer acceptance cri...
- Patent number 8,862,417
- Issue date Oct 14, 2014
- International Business Machines Corporation
- Albert M. Chu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Capacitor designs for integrated circuits utilizing self-aligned do...
- Patent number 8,856,715
- Issue date Oct 7, 2014
- GLOBALFOUNDRIES Inc.
- Jason Stephens
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
BACKSIDE LOCAL INTERCONNECT
- Publication number 20250022795
- Publication date Jan 16, 2025
- International Business Machines Corporation
- Nicholas Anthony Lanzillo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
STACKED FET WITH LOW PARASITIC-CAPACITANCE GATE
- Publication number 20250006786
- Publication date Jan 2, 2025
- International Business Machines Corporation
- Ruilong Xie
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PITCH CHANGE BETWEEN METAL LINES
- Publication number 20250006638
- Publication date Jan 2, 2025
- International Business Machines Corporation
- Ruilong Xie
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MERGED SELF-ALIGNED BACKSIDE CONTACT
- Publication number 20240429098
- Publication date Dec 26, 2024
- International Business Machines Corporation
- Albert M. Chu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PROTECTION DIODE FOR STACKED FIELD EFFECT TRANSISTOR
- Publication number 20240429226
- Publication date Dec 26, 2024
- International Business Machines Corporation
- HUIMEI ZHOU
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
STRUCTURE FOR BACKSIDE SIGNAL AND POWER
- Publication number 20240421087
- Publication date Dec 19, 2024
- International Business Machines Corporation
- Lawrence A. Clevenger
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CIRCUIT LAYOUTS WITH STAGGERED GATE AND SOURCE/DRAIN REGIONS
- Publication number 20240421145
- Publication date Dec 19, 2024
- International Business Machines Corporation
- Carl Radens
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
STACKED TRANSISTOR STRUCTURES WITH HYBRID GATE PITCH
- Publication number 20240421156
- Publication date Dec 19, 2024
- International Business Machines Corporation
- Ruilong Xie
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INVERTED GATE CUT REGION
- Publication number 20240420959
- Publication date Dec 19, 2024
- International Business Machines Corporation
- Ruilong Xie
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
REDUCTION OF MIDDLE-OF-LINE RESISTANCE AND CAPACITANCE
- Publication number 20240421078
- Publication date Dec 19, 2024
- International Business Machines Corporation
- Brent A. Anderson
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTERCONNECT LEVELS WITH MULTIPLE LINE TYPES
- Publication number 20240421079
- Publication date Dec 19, 2024
- International Business Machines Corporation
- Nicholas Anthony Lanzillo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
STACKED DEVICES WITH BACKSIDE CONTACTS
- Publication number 20240421038
- Publication date Dec 19, 2024
- International Business Machines Corporation
- Nicholas Anthony Lanzillo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
LEAKAGE REDUCTION FOR CONTINUOUS ACTIVE DESIGNS
- Publication number 20240421182
- Publication date Dec 19, 2024
- International Business Machines Corporation
- Jason J Stuffle
- G11 - INFORMATION STORAGE
Information Patent Application
INVERTED GATE CUT REGION
- Publication number 20240420960
- Publication date Dec 19, 2024
- International Business Machines Corporation
- Ruilong Xie
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SPLIT BACKSIDE POWER RAIL FOR ISOLATED SUPPLY
- Publication number 20240395711
- Publication date Nov 28, 2024
- International Business Machines Corporation
- Brent A. Anderson
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PLACEHOLDER PROFILE FORMATION FOR BACKSIDE CONTACT
- Publication number 20240379769
- Publication date Nov 14, 2024
- International Business Machines Corporation
- Ruilong Xie
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
BACKSIDE SELF ALIGNED SKIP VIA
- Publication number 20240371729
- Publication date Nov 7, 2024
- International Business Machines Corporation
- Ruilong Xie
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
BACKSIDE CONTACTS FOR SOURCE/DRAIN REGIONS
- Publication number 20240371728
- Publication date Nov 7, 2024
- International Business Machines Corporation
- Albert M. Chu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
GOUGED INTERCONNECT LINE
- Publication number 20240363524
- Publication date Oct 31, 2024
- International Business Machines Corporation
- Nicholas Anthony Lanzillo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ASYMMETRIC GATE EXTENSION IN STACKED FET
- Publication number 20240355679
- Publication date Oct 24, 2024
- International Business Machines Corporation
- Ruilong Xie
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
AIR POCKET BETWEEN TOP AND BOTTOM SOURCE/DRAIN REGIONS
- Publication number 20240339452
- Publication date Oct 10, 2024
- International Business Machines Corporation
- Brent A. Anderson
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
GATE CONTACTS FOR SEMICONDUCTOR DEVICES
- Publication number 20240332293
- Publication date Oct 3, 2024
- International Business Machines Corporation
- Ruilong Xie
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
IRREGULAR-SHAPED POWER RAIL IN CELL POWER DISTRIBUTION
- Publication number 20240321748
- Publication date Sep 26, 2024
- International Business Machines Corporation
- Lawrence A. Clevenger
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
STACKED LINEAR DOUBLE-LENGTH VTFETS
- Publication number 20240321879
- Publication date Sep 26, 2024
- International Business Machines Corporation
- Brent A. Anderson
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SELF-ALIGNED VIA IN DOUBLE DIFFUSION BREAK TO CONNECT TO BACKSIDE I...
- Publication number 20240312912
- Publication date Sep 19, 2024
- International Business Machines Corporation
- Reinaldo Vega
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CROSS COUPLED STACKED TRANSISTORS
- Publication number 20240304626
- Publication date Sep 12, 2024
- International Business Machines Corporation
- Tsung-Sheng Kang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FRONTSIDE TO BACKSIDE SIGNAL VIA IN EDGE CELL
- Publication number 20240304519
- Publication date Sep 12, 2024
- International Business Machines Corporation
- Albert M. Chu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SELF-ALIGNED BACKSIDE INTERCONNECT STRUCTURES
- Publication number 20240297167
- Publication date Sep 5, 2024
- International Business Machines Corporation
- Ruilong Xie
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PASS-THROUGH WIRING IN NOTCHED INTERCONNECT
- Publication number 20240290713
- Publication date Aug 29, 2024
- International Business Machines Corporation
- Nicholas Anthony Lanzillo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
BACKSIDE CONTACT WITH CONTACT JUMPER FOR STACKED FET
- Publication number 20240250136
- Publication date Jul 25, 2024
- International Business Machines Corporation
- Ruilong Xie
- H01 - BASIC ELECTRIC ELEMENTS

Albert M. Chu

Person

Patents Grantslast 30 patents

Staggered stacked semiconductor devices

Ultra-short-height standard cell architecture

Interconnects on multiple sides of a semiconductor structure

Field effect transistor

3D vertical FET with top and bottom gate contacts

Fabricating tapered semiconductor devices

Multi-patterning techniques for fabricating an array of metal lines...

Cell placement in a circuit with shared inputs and outputs

Vertical transport logic circuit cell with shared pitch

Reliable gate contacts over active areas

4T static random access memory bitcell retention

3D vertical FET with top and bottom gate contacts

Standard cell architecture with at least one gate contact over an a...

Standard cell architecture with at least one gate contact over an a...

Metal fill optimization for self-aligned double patterning

Reliable gate contacts over active areas

3D vertical FET with top and bottom gate contacts

3D vertical FET with top and bottom gate contacts

Ultra dense vertical transport FET circuits

High density vertical field effect transistor multiplexer

Vertical transistors with merged active area regions

Metal fill optimization for self-aligned double patterning

Ultra dense vertical transport FET circuits

Read only memory (ROM) with redundancy

Generating place and route abstracts

Methods and circuits for generating physically unclonable function

Embedded photon emission calibration (EPEC)

Process variation skew in an SRAM column architecture

Systems and methods for determining adjustable wafer acceptance cri...

Capacitor designs for integrated circuits utilizing self-aligned do...

Patents Applicationslast 30 patents

BACKSIDE LOCAL INTERCONNECT

STACKED FET WITH LOW PARASITIC-CAPACITANCE GATE

PITCH CHANGE BETWEEN METAL LINES

MERGED SELF-ALIGNED BACKSIDE CONTACT

PROTECTION DIODE FOR STACKED FIELD EFFECT TRANSISTOR

STRUCTURE FOR BACKSIDE SIGNAL AND POWER

CIRCUIT LAYOUTS WITH STAGGERED GATE AND SOURCE/DRAIN REGIONS

STACKED TRANSISTOR STRUCTURES WITH HYBRID GATE PITCH

INVERTED GATE CUT REGION

REDUCTION OF MIDDLE-OF-LINE RESISTANCE AND CAPACITANCE

INTERCONNECT LEVELS WITH MULTIPLE LINE TYPES

STACKED DEVICES WITH BACKSIDE CONTACTS

LEAKAGE REDUCTION FOR CONTINUOUS ACTIVE DESIGNS

INVERTED GATE CUT REGION

SPLIT BACKSIDE POWER RAIL FOR ISOLATED SUPPLY

PLACEHOLDER PROFILE FORMATION FOR BACKSIDE CONTACT

BACKSIDE SELF ALIGNED SKIP VIA

BACKSIDE CONTACTS FOR SOURCE/DRAIN REGIONS

GOUGED INTERCONNECT LINE

ASYMMETRIC GATE EXTENSION IN STACKED FET

AIR POCKET BETWEEN TOP AND BOTTOM SOURCE/DRAIN REGIONS

GATE CONTACTS FOR SEMICONDUCTOR DEVICES

IRREGULAR-SHAPED POWER RAIL IN CELL POWER DISTRIBUTION

STACKED LINEAR DOUBLE-LENGTH VTFETS

SELF-ALIGNED VIA IN DOUBLE DIFFUSION BREAK TO CONNECT TO BACKSIDE I...

CROSS COUPLED STACKED TRANSISTORS

FRONTSIDE TO BACKSIDE SIGNAL VIA IN EDGE CELL

SELF-ALIGNED BACKSIDE INTERCONNECT STRUCTURES

PASS-THROUGH WIRING IN NOTCHED INTERCONNECT

BACKSIDE CONTACT WITH CONTACT JUMPER FOR STACKED FET