Patent Application
20250118661
The present invention generally relates to semiconductor devices and processing methods, and more particularly to semiconductor devices having a power rail cut to provide multiple signal/power connections in chip circuits.
Integrated circuit devices are constructed by forming diffusion regions in a substrate and then building up wiring connections from the substrate through to a back end of line (BEOL) structure. Such devices present a diffusion region (e.g., source/drain region) on one side of the device formed in the substrate, and a contact is dropped down to connect with the diffusion region. Metal lines connect to the contacts and are themselves connected to by other contacts and metal lines to form a metal structure in accordance with a chip design. This region of a device is referred to as an active prime region. Electrical access to the active prime region can include the use of backside power rails, signal lines and backside power distribution rail networks (BSPDN) which supply power to the device.
In accordance with an embodiment of the present invention, a semiconductor structure includes an interconnect wiring level having metal lines. An insulating cut shape is disposed through a run length of at least one of the metal lines wherein the insulating cut shape divides the at least one of the metal lines into electrically isolated nets.
In accordance with another embodiment of the present invention, a method for fabricating a semiconductor structure includes forming a metal line in a dielectric layer of a metallization layer; etching trenches through the metal line along a run length of the metal line; depositing an insulating material in the trenches; and planarizing the insulating material to a surface of the dielectric layer and the metal line to form a cut shape that divides the metal line into electrically isolated nets.
In accordance with another embodiment of the present invention, a method for fabricating a semiconductor structure includes forming an insulating material on a dielectric layer; etching the insulating material to form at least one cut shape that extends along a metal line run length; depositing a conductive material over the at least one cut shape; and recessing the conductive material to expose the at least one cut shape to form electrically isolated nets on opposing sides of the at least one cut shape.
These and other features and advantages will become apparent from the following detailed description of illustrative embodiments thereof, which is to be read in connection with the accompanying drawings.
The following description will provide details of preferred embodiments with reference to the following figures wherein:
In accordance with embodiments of the present invention, devices and methods are described which include semiconductor devices having electrical paths added by cutting metal lines with a dielectric cut shape. In useful embodiments, the cut shapes or dividers are cut through the metal lines to provide electrical isolation between the two divided portions. The cut shapes are implemented longitudinally along a length of the metal line. This is especially useful in chip designs where a cell size does not permit patterning and forming a completely independent metal line.
In one embodiment, a chip can include a small cell size that does not permit multiple metal lines within the allotted space of the cell. This scenario occurs, e.g., in backside power and signal line routing. Further, capacitance coupling concerns places restrictions on distances between metal lines. In device architectures that include, e.g., stacked devices or multiple levels of devices, having the ability to include a separate supply voltage line without giving up space and without unduly introducing parasitic capacitance is particularly useful.
In some embodiments, the metal lines divided by cut shapes need not be centered along the metal line. In this way, different sized lines can be produced by a single cut line. The cut shape can be longitudinally straight, can include a wriggling pattern, or can include a repeating pattern along the longitudinal direction of the cut shape. Non-linear features along the cut shape can assist in reducing capacitive coupling between the portion of the metal line. In other embodiments, the cut shape can extend through and beyond the metal line that the cut shape is dividing. The portion of the cut shape that extends beyond the metal line can be used to assist in aligning a next metal feature that connects to the metal line.
For semiconductor device layouts, cell architecture is defined based on a cell height which is determined on the basis of a number of tracks and pitch of metal lines relative to devices (e.g., transistor widths). Cells are abutted together to implement a given design. Cells with similar height are aligned with each other to attain this similarity among the cells and avoid alignment issues. The height of a cell can be determined by considering a number of tracks needed for a power rail, a ground rail, input/output (I/O pins) and routing. The cell height puts restrictions on the size and pitch of possible metal lines. For example, going from a single line per cell to a double line per cell is often difficult due to very stringent design rules that make providing a second line within a same cell height nearly impossible. This is due in part to uneven or irregular widths which could occur due to the small line widths. In addition, spaces between lines would be too small (e.g., not enough space (resulting in crosstalk) or dielectric material between the lines (resulting in shorts)).
In accordance with the present embodiments, a semiconductor structure is provided with a level of interconnect wiring having one or more insulating cut shapes formed along a run length of a wiring level, dividing it into two or more electrically isolated networks (nets). The level of the interconnect could be formed on a frontside, a backside or both in the semiconductor structure. The cut shapes can be formed off-center from a middle of the line being cut. The cut shapes can include an extended portion to provide self-alignment for vias landing on that line. The cut material can include a single insulator layer or multiple layers including at least one ferroelectric to increase decoupling capacitance.
In useful embodiments, the cut shapes enable double or more of the metal wire resources for a given patterned pitch, e.g., at level of interconnect wiring, backside metal 1 (BM1). Cut shape width can be tuned for reliability/performance. For example, a wider cut shape can provide better reliability since the risk of shorting between positive supply voltage (VDD) and negative (or ground) supply voltage (VSS) is reduced, and a narrower cut shape can provide more decoupling capacitance since VDD and VSS nets would be closer to one another.
In one example use case, cut shapes can be employed to create power and ground supply (VDD and VSS supply, respectively) on a backside of a chip from a single wire. In another example, a wire can be cut and one segment could be used to carry a first VDD (“VDD1”) while the second segment could be used to carry a second VDD (“VDD2”), i.e., two positive supply voltages. The use of multiple voltages is helpful in power gating applications, wherein power can be turned on/off over a large section of a chip design. Cut shapes in accordance with embodiments of the present invention also provide direct backside contact connections within a cell and backside signal route connections within a cell.
Narrow cut shapes (˜10 nm), to put in between, e.g., VDD/VSS nets on a same wire for decoupling capacitance purposes, can be limited as being dependent on patterning process dimensions. If backside patterning employs, e.g., extreme ultraviolet lithography (EUV) then cut shapes down to ˜10 nm in width can be formed. If instead, less expensive immersion lithography is employed, a minimum cut size will be larger (e.g., about 20-30 nm). These dimensions are expected to be further reduced over time as further improvements occur in the patterning technology which can further provide the ability for reduced-dimensioned cut shapes.
Embodiments of the present invention can be employed in any type of semiconductor device or chip. For example, the present embodiments can include input/output (IO) circuits, high performance computing (HPC) circuits, clock buffers, processors, memory devices or any other integrated circuit chip or combinations thereof. Adding additional conductive paths to a device in accordance with embodiments of the present invention can be integrated into any fabrication process with minimal or no impact on expense or processing time.
Referring now to the drawings in which like-numerals represent the same or similar elements and initially to
A bottom metal layer 114 includes backside power and signal distribution networks (nets) 116 with wires that can deliver power to a backside redistribution layer (RDL) (not shown). A RDL is a layer of wiring metal interconnects that redistribute signal access to different parts of the chip. A power RDL wire can connect to back end of line (BEOL) metallizations. In one embodiment, vias 124, 126 to buried power rail (VBPR) can connect a backside power delivery network (BSPDN) that can be used for power distribution or electrical signal transmission. Buried power rails (BPR) of the BSPDN are connected to power wires through buried vias, and these power wires are connected to the back end of the line BEOL wires.
For this architecture, three nets 116 (e.g., VDD, VSS, signal) would normally be employed; however, to improve areal density and device count, additional nets are desirable. In accordance with an embodiment, nets 116 can be subdivided into net portions 140 by employing cut shapes 142 to enable additional nets or circuits. Instead of only one net per cell, two or more nets per cell 102, 104 can be provided. In useful embodiments, VDD, VSS, and signal nets 116 can be subdivided using cut shapes 142. The subdivided nets or net portions 140 can include any net type. In other words, VDD net and a VSS net can be separated by a cut shape 142, a signal net and a VSS net can be separated by a cut shape 142, VDD net and a signal net can be separated by a cut shape 142, etc.
Additional nets can serve a number of useful purposes. For example, another net at or near a cell boundary for backside signal routing might provide less crosstalk. Another net in a middle of the cell (e.g., VSS connection to contact 126) can provide greater access to powered components. A net at or near the cell boundary can provide, e.g., VDD to a top source region 134.
Cut shapes 142 can be employed in any metal layer on a frontside or backside of a device. For ease of description, the present embodiments will be described with reference to a first backside metal line (BM1) in the context of dividing buried supply power lines (e.g., VDD and VSS) and buried signal lines (signal).
Referring to
In accordance with embodiments of the present invention, a number of metal lines 224 is doubled by employing a cut shape 222 to divide the larger metals lines 224 resulting in two metal lines 226 per cell height 212. Metal lines 226 can be employed for a positive supply voltage (VDD) net and a negative or ground supply voltage (VSS) net in a same cell (e.g., within a same cell height 212) with appropriate distances maintained. By employing the cut shapes 222 metal line density can be increased without sacrificing reliability.
Referring to
In one embodiment, the cut shape 222 is formed with an extended portion 223 that extends beyond a surface of the metal line 226. This extended portion 223 increases the processing margin by helping to properly land the via 302 on the metal line 226. When etching the hole for the via 302, there is less likelihood that the via hole will connect to the other metal line 226 (VSS, in this case) which is not intended to be connected by via 302. The extended portion 223 forms a “fence” to ensure proper connections are made. The extended portion 223 gives some topography to promote self-alignment and provide overly margin to via 302 landing metal line 226.
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In other embodiments, multiple layers can be employed including at least one ferroelectric material to increase decoupling capacitance between metal lines 802 and 804. Ferroelectric materials show a dependence on an applied electric field and can provide capacitive decoupling between metal lines 802 and 804. One or more of materials 808 and 810 can include, e.g., HfO2, AlScN, or BaTiO3 (BTO), etc.
While
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The perturbations of the cut shape 906 can be included more easily with wider metal lines. The perturbations can be formed by tweaking features on etch masks, lithography images or exploiting settings/processing parameters. In some embodiments, the features of the perturbations may not be smooth but instead include a periodic pattern of larger and smaller width sections of the cut shape line.
The perturbations of the cut shape 906 can be formed during a damascene etching (as described with reference to
Referring to
The dielectric layer 1004 can include, e.g., silicon containing materials such as SiO2, Si3N4, SiOxNy, SiC, SiCO, SiCOH, and SiCH compounds, the above-mentioned silicon containing materials with some or all of the Si replaced by Ge, carbon doped oxides, inorganic oxides, inorganic polymers, hybrid polymers, organic polymers such as polyamides or SiLK™, other carbon containing materials, organo-inorganic materials such as spin-on glasses and silsesquioxane-based materials, and diamond-like carbon (DLC), also known as amorphous hydrogenated carbon, α-C:H). The dielectric layer 1004 can be deposited by any suitable deposition method(s). The metal lines 1006 can include materials, such as, e.g., Cu, Ru, Mo, Rh, W, Ir, and alloys or combinations of these and other conductive materials.
A top view 1020 and a cross-sectional view 1022 show cut shape trenches 1008 formed in metal layers 1004. The cut shape trenches 1008 can be formed by applying a hard mask (not shown), followed by lithographic processing to produce an etch pattern. The etch process can include a reactive ion etch (RIE) process that stops on the dielectric layer 1004.
A top view 1030 and a cross-sectional view 1032 show cut shapes 1040 formed in metal layers 1004. The cut shapes 1040 can be formed by depositing a dielectric material in the cut shape trenches 1008. The dielectric material for cut shapes 1040 can include, e.g., silicon containing materials such as SiO2, Si3N4, SiOxNy, SiC, SiCO, SiCOH, and SiCH compounds, the above-mentioned silicon containing materials with some or all of the Si replaced by Ge, carbon doped oxides, inorganic oxides, inorganic polymers, hybrid polymers, organic polymers such as polyamides or SiLK™, other carbon containing materials, organo-inorganic materials such as spin-on glasses and silsesquioxane-based materials, and diamond-like carbon (DLC), also known as amorphous hydrogenated carbon, α-C:H). The cut shapes 1040 can also include ferroelectric materials. The material for cut shapes in then planarized, e.g., by CMP, to provide a surface for further processing.
In one embodiment, cut shapes 1040 are formed in stages to make a component cut shape. In another embodiment, the metal lines 1042 and dielectric layer 1004 are recessed to form an extended portion or fence for the cut shape 1040. The cut shapes 1040 cut the metal lines 1006 in half to form portions of metal lines or nets (1042).
Referring to
The cut shapes 1140 can include, e.g., silicon containing materials such as SiO2, Si3N4, SiOxNy, SiC, SiCO, SiCOH, and SiCH compounds, the above-mentioned silicon containing materials with some or all of the Si replaced by Ge, carbon doped oxides, inorganic oxides, inorganic polymers, hybrid polymers, organic polymers such as polyamides or SiLK™, other carbon containing materials, organo-inorganic materials such as spin-on glasses and silsesquioxane-based materials, and diamond-like carbon (DLC), also known as amorphous hydrogenated carbon, α-C:H). The cut shapes 1140 can also include ferroelectric materials. The cut shapes 1104 can be deposited by any suitable deposition method(s).
A top view 1120 and a cross-sectional view 1122 show a conductive material 1124 deposited over the cut shapes 1104. The conductive material 1124 can include materials, such as, e.g., Cu, Ru, Mo, Rh, W, Ir, and alloys or combinations of these and other conductive materials.
A top view 1130 and a cross-sectional view 1132 show cut shapes 1140 formed through the conductive material 1124 to form metal lines 1142 or nets. The conductive material 1124 is recessed to expose the cut shapes 1140. This can be performed by a wet or dry etch. The cut shapes 1140 can also be planarized, e.g., by CMP, to expose the cut shapes 1140 and to provide a surface for further processing.
In one embodiment, cut shapes 1140 are formed in multiple layers to make a component cut shape. For example, cut shapes 1140 can be formed by depositing two or more layers of different materials before etching to form the cut shapes 1140. In another embodiment, the conductive material 1124 can be recessed to form an extended portion or fence on the cut shape 1140. The cut shapes 1140 divide the conductive material 1124 in half to form metal lines 1142 or nets.
It should be understood that cut shapes 1140 in
Wires on the backside of a chip can be used for power delivery, e.g., alternating wires that carry power (VDD) or ground (VSS). By cutting a wire using a cut shape in accordance with embodiment of the present invention, one segment of the wire is permitted to be used for VDD and the other segment to be used for VSS. If VDD and VSS short to one another, it presents a reliability risk. By making the cut shape wide, this risk can be minimized to maintain robust reliability. One other hand, capacitance between VDD and VSS (decoupling capacitance) acts to reduce power supply noise, which improves chip performance. By making a cut shape narrow, the space between VDD/VSS becomes smaller and thus the decoupling capacitance grows. The tradeoff between reliability and performance (wide versus narrow cut shapes) can be tuned depending on the application of the chip (e.g., high-performance supercomputers may need different decoupling than say, cellphones).
It should be understood that the damascene (
Referring to
In some embodiments a backside metal can include cut shapes that divide metal lines for power delivery. In one embodiment, one line per cell height can be used and use different sides of the cut for VDD and VSS. With adjacent VDD and VSS lines or nets, this can be good for capacitive decoupling. Different materials can be employed for cut shape in a same level depending on function. For example, a low-k dielectric can be employed for cut shapes between signal wires while high-k dielectric can be employed for cut shapes between power wires.
The embodiments described herein can include combinations of multiple features of the present invention. For example, a single cut shape can be asymmetrically aligned with the metal line it divides, can include an extended portion (“fence”), have a compound composition (multiple materials), include a wriggling effect for capacitive decoupling and any other feature of combination of features.
Exemplary applications/uses to which the present invention can be applied include, but are not limited to semiconductor devices. Semiconductor devices can include processors, memory devices, application specific integrated circuits (ASICs), logic circuits or devices, combinations of these and any other circuit device. In such devices, one or more semiconductor devices can be included in a central processing unit, a graphics processing unit, and/or a separate processor- or computing element-based controller (e.g., logic gates, etc.). The semiconductor devices can include one or more on-board memories (e.g., caches, dedicated memory arrays, read only memory, etc.). In some embodiments, the semiconductor devices can include one or more memories that can be on or off board or that can be dedicated for use by a hardware processor subsystem (e.g., ROM, RAM, basic input/output system (BIOS), etc.).
In some embodiments, the semiconductor devices can include and execute one or more software elements. The one or more software elements can include an operating system and/or one or more applications and/or specific code to achieve a specified result. In still other embodiments, the semiconductor devices can include dedicated, specialized circuitry that perform one or more electronic processing functions to achieve a specified result. Such circuitry can include one or more field programmable gate arrays (FPGAs), and/or programmable applications programmable logic arrays (PLAs).
It is to be understood that aspects of the present invention will be described in terms of a given illustrative architecture; however, other architectures, structures, substrate materials and process features and steps can be varied within the scope of aspects of the present invention.
It will also be understood that when an element such as a layer, region or substrate is referred to as being “on” or “over” another element, it can be directly on the other element or intervening elements can also be present. In contrast, when an element is referred to as being “directly on” or “directly over” another element, there are no intervening elements present. It will also be understood that when an element is referred to as being “connected” or “coupled” to another element, it can be directly connected or coupled to the other element or intervening elements can be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, there are no intervening elements present.
The present embodiments can include a design for an integrated circuit chip, which can be created in a graphical computer programming language, and stored in a computer storage medium (such as a disk, tape, physical hard drive, or virtual hard drive such as in a storage access network). If the designer does not fabricate chips or the photolithographic masks used to fabricate chips, the designer can transmit the resulting design by physical means (e.g., by providing a copy of the storage medium storing the design) or electronically (e.g., through the Internet) to such entities, directly or indirectly. The stored design is then converted into the appropriate format (e.g., GDSII) for the fabrication of photolithographic masks, which typically include multiple copies of the chip design in question that are to be formed on a wafer. The photolithographic masks are utilized to define areas of the wafer (and/or the layers thereon) to be etched or otherwise processed.
Methods as described herein can be used in the fabrication of integrated circuit chips. The resulting integrated circuit chips can be distributed by the fabricator in raw wafer form (that is, as a single wafer that has multiple unpackaged chips), as a bare die, or in a packaged form. In the latter case, the chip is mounted in a single chip package (such as a plastic carrier, with leads that are affixed to a motherboard or other higher level carrier) or in a multichip package (such as a ceramic carrier that has either or both surface interconnections or buried interconnections). In any case, the chip is then integrated with other chips, discrete circuit elements, and/or other signal processing devices as part of either (a) an intermediate product, such as a motherboard, or (b) an end product. The end product can be any product that includes integrated circuit chips, ranging from toys and other low-end applications to advanced computer products having a display, a keyboard or other input device, and a central processor.
It should also be understood that material compounds will be described in terms of listed elements, e.g., SiGe. These compounds include different proportions of the elements within the compound, e.g., SiGe includes SixGe1-x where x is less than or equal to 1, etc. In addition, other elements can be included in the compound and still function in accordance with the present principles. The compounds with additional elements will be referred to herein as alloys.
Reference in the specification to “one embodiment” or “an embodiment”, as well as other variations thereof, means that a particular feature, structure, characteristic, and so forth described in connection with the embodiment is included in at least one embodiment. Thus, the appearances of the phrase “in one embodiment” or “in an embodiment”, as well any other variations, appearing in various places throughout the specification are not necessarily all referring to the same embodiment.
It is to be appreciated that the use of any of the following “/”, “and/or”, and “at least one of”, for example, in the cases of “A/B”, “A and/or B” and “at least one of A and B”, is intended to encompass the selection of the first listed option (A) only, or the selection of the second listed option (B) only, or the selection of both options (A and B). As a further example, in the cases of “A, B, and/or C” and “at least one of A, B, and C”, such phrasing is intended to encompass the selection of the first listed option (A) only, or the selection of the second listed option (B) only, or the selection of the third listed option (C) only, or the selection of the first and the second listed options (A and B) only, or the selection of the first and third listed options (A and C) only, or the selection of the second and third listed options (B and C) only, or the selection of all three options (A and B and C). This can be extended, as readily apparent by one of ordinary skill in this and related arts, for as many items listed.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of example embodiments. As used herein, the singular forms “a,” “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises,” “comprising,” “includes” and/or “including,” when used herein, specify the presence of stated features, integers, steps, operations, elements and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and/or groups thereof.
Spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper,” “top,” “bottom” and the like, can be used herein for ease of description to describe one element's or feature's relationship to another element(s) or feature(s) as illustrated in the FIGS. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the FIGS. For example, if the device in the FIGS. is turned over, elements described as “below” or “beneath” other elements or features would then be oriented “above” the other elements or features. Thus, the term “below” can encompass both an orientation of above and below. The device can be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein can be interpreted accordingly. In addition, it will also be understood that when a layer is referred to as being “between” two layers, it can be the only layer between the two layers, or one or more intervening layers can also be present.
It will be understood that, although the terms first, second, etc. can be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. Thus, a first element discussed below could be termed a second element without departing from the scope of the present concept.
Having described preferred embodiments of devices and methods (which are intended to be illustrative and not limiting), it is noted that modifications and variations can be made by persons skilled in the art in light of the above teachings. It is therefore to be understood that changes may be made in the particular embodiments disclosed which are within the scope of the invention as outlined by the appended claims. Having thus described aspects of the invention, with the details and particularity required by the patent laws, what is claimed and desired protected by Letters Patent is set forth in the appended claims.
