Douglas B. Boyle

Person

Palo Alto, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Photonics-optimized processor system
- Patent number 9,495,295
- Issue date Nov 15, 2016
- PHOTONIC INTERNATIONAL PTE. LTD.
- Birendra Dutt
- G11 - INFORMATION STORAGE
Information Patent Grant
Placement method for integrated circuit design using topo-clustering
- Patent number 6,961,916
- Issue date Nov 1, 2005
- Synopsys, Inc.
- Majid Sarrafzadeh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for design optimization using logical and physical information
- Patent number 6,557,145
- Issue date Apr 29, 2003
- Monterey Design Systems, Inc.
- Douglas B. Boyle
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Optimization processing for integrated circuit physical design auto...
- Patent number 6,493,658
- Issue date Dec 10, 2002
- LSI Logic Corporation
- James S. Koford
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for accurate and efficient updates of timing information log...
- Patent number 6,449,756
- Issue date Sep 10, 2002
- Monterey Design Systems
- Sharad Malik
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Placement method for integrated circuit design using topo-clustering
- Patent number 6,442,743
- Issue date Aug 27, 2002
- Monterey Design Systems
- Majid Sarrafzadeh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for concurrent placement of gates and associated...
- Patent number 6,385,760
- Issue date May 7, 2002
- Monterey Design Systems, Inc.
- Lawrence Pileggi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for concurrent buffer insertion and placement of...
- Patent number 6,367,051
- Issue date Apr 2, 2002
- Monterey Design Systems, Inc.
- Lawrence Pileggi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for design optimization using logical and physical information
- Patent number 6,286,128
- Issue date Sep 4, 2001
- Monterey Design Systems, Inc.
- Lawrence Pileggi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for logic optimization for improving timing and congestion d...
- Patent number 6,192,508
- Issue date Feb 20, 2001
- Monterey Design Systems
- Sharad Malik
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cell placement representation and transposition for integrated circ...
- Patent number 6,155,725
- Issue date Dec 5, 2000
- LSI Logic Corporation
- Ranko Scepanovic
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Microprocessor having instruction set extensions for decryption and...
- Patent number 6,118,870
- Issue date Sep 12, 2000
- LSI Logic Corp.
- Douglas B. Boyle
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Method for providing performance-driven logic optimization in an in...
- Patent number 6,099,580
- Issue date Aug 8, 2000
- Monterey Design Systems, Inc.
- Douglas B. Boyle
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Single chip systems using general purpose processors
- Patent number 6,092,229
- Issue date Jul 18, 2000
- LSI Logic Corporation
- Douglas B. Boyle
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Single chip integrated circuit distributed shared memory (DSM) and...
- Patent number 5,963,975
- Issue date Oct 5, 1999
- LSI Logic Corporation
- Douglas B. Boyle
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Congestion based cost factor computing apparatus for integrated cir...
- Patent number 5,914,887
- Issue date Jun 22, 1999
- LSI Logic Corporation
- Ranko Scepanovic
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method of cell placement for an integrated circuit chip comprising...
- Patent number 5,903,461
- Issue date May 11, 1999
- LSI Logic Corporation
- Michael D. Rostoker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Simultaneous placement and routing (SPAR) method for integrated cir...
- Patent number 5,875,117
- Issue date Feb 23, 1999
- LSI Logic Corporation
- Edwin R. Jones
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Optimization processing for integrated circuit physical design auto...
- Patent number 5,870,313
- Issue date Feb 9, 1999
- LSI Logic Corporation
- Douglas B. Boyle
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for maintaining a shared cache look-up table
- Patent number 5,864,854
- Issue date Jan 26, 1999
- LSI Logic Corporation
- Douglas B. Boyle
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Computer implemented method for leveling interconnect wiring densit...
- Patent number 5,835,378
- Issue date Nov 10, 1998
- LSI Logic Corporation
- Ranko Scepanovic
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Fail-safe distributive processing method for producing a highest fi...
- Patent number 5,815,403
- Issue date Sep 29, 1998
- LSI Logic Corporation
- Edwin R. Jones
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cell placement alteration apparatus for integrated circuit chip phy...
- Patent number 5,793,644
- Issue date Aug 11, 1998
- LSI Logic Corporation
- James S. Koford
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for producing integrated circuit chip having optimized cell...
- Patent number 5,781,439
- Issue date Jul 14, 1998
- LSI Logic Corporation
- Michael D. Rostoker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Single chip multiprocessor architecture with internal task switchin...
- Patent number 5,761,516
- Issue date Jun 2, 1998
- LSI Logic Corporation
- Michael D. Rostoker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Optimization processing for integrated circuit physical design auto...
- Patent number 5,745,363
- Issue date Apr 28, 1998
- LSI Logic Corporation
- Michael D. Rostoker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Simultaneous placement and routing (SPAR) method for integrated cir...
- Patent number 5,742,510
- Issue date Apr 21, 1998
- LSI Logic Corporation
- Michael D. Rostoker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Optimization processing for integrated circuit physical design auto...
- Patent number 5,682,322
- Issue date Oct 28, 1997
- LSI Logic Corporation
- Douglas B. Boyle
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Computer implemented method for producing optimized cell placement...
- Patent number 5,636,125
- Issue date Jun 3, 1997
- LSI Logic Corporation
- Michael D. Rostoker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method of cell placement for an itegrated circuit chip comprising i...
- Patent number 5,619,419
- Issue date Apr 8, 1997
- LSI Logic Corporation
- Patrik D'Haeseleer
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
Photonics-Optimized Processor System
- Publication number 20160314091
- Publication date Oct 27, 2016
- PhotonIC International Pte. Ltd.
- Birendra Dutt
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Photonics-Optimized Processor System
- Publication number 20160313760
- Publication date Oct 27, 2016
- PhotonIC International Pte. Ltd.
- Birendra Dutt
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Photonics-Optimized Processor System
- Publication number 20160314003
- Publication date Oct 27, 2016
- PhotonIC International Pte. Ltd.
- Birendra Dutt
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Photonics-Optimized Processor System
- Publication number 20160314070
- Publication date Oct 27, 2016
- PhotonIC International Pte. Ltd.
- Birendra Dutt
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Photonics-Optimized Processor System
- Publication number 20160314088
- Publication date Oct 27, 2016
- PhotonIC International Pte. Ltd.
- Birendra Dutt
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and apparatus for mapping platform-based design to multiple...
- Publication number 20050034087
- Publication date Feb 10, 2005
- Christopher L. Hamlin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Placement method for integrated circuit design using topo-clustering
- Publication number 20020138816
- Publication date Sep 26, 2002
- Majid Sarrafzadeh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEM AND METHOD FOR CONCURRENT PLACEMENT OF GATES AND ASSOCIATED...
- Publication number 20010047507
- Publication date Nov 29, 2001
- LAWRENCE PILEGGI
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method for design optimization using logical and physical information
- Publication number 20010010090
- Publication date Jul 26, 2001
- Douglas B. Boyle
- G06 - COMPUTING CALCULATING COUNTING

Douglas B. Boyle

Person

Patents Grantslast 30 patents

Photonics-optimized processor system

Placement method for integrated circuit design using topo-clustering

Method for design optimization using logical and physical information

Optimization processing for integrated circuit physical design auto...

Method for accurate and efficient updates of timing information log...

Placement method for integrated circuit design using topo-clustering

System and method for concurrent placement of gates and associated...

System and method for concurrent buffer insertion and placement of...

Method for design optimization using logical and physical information

Method for logic optimization for improving timing and congestion d...

Cell placement representation and transposition for integrated circ...

Microprocessor having instruction set extensions for decryption and...

Method for providing performance-driven logic optimization in an in...

Single chip systems using general purpose processors

Single chip integrated circuit distributed shared memory (DSM) and...

Congestion based cost factor computing apparatus for integrated cir...

Method of cell placement for an integrated circuit chip comprising...

Simultaneous placement and routing (SPAR) method for integrated cir...

Optimization processing for integrated circuit physical design auto...

System and method for maintaining a shared cache look-up table

Computer implemented method for leveling interconnect wiring densit...

Fail-safe distributive processing method for producing a highest fi...

Cell placement alteration apparatus for integrated circuit chip phy...

Method for producing integrated circuit chip having optimized cell...

Single chip multiprocessor architecture with internal task switchin...

Optimization processing for integrated circuit physical design auto...

Simultaneous placement and routing (SPAR) method for integrated cir...

Optimization processing for integrated circuit physical design auto...

Computer implemented method for producing optimized cell placement...

Method of cell placement for an itegrated circuit chip comprising i...

Patents Applicationslast 30 patents

Photonics-Optimized Processor System

Photonics-Optimized Processor System

Photonics-Optimized Processor System

Photonics-Optimized Processor System

Photonics-Optimized Processor System

Method and apparatus for mapping platform-based design to multiple...

Placement method for integrated circuit design using topo-clustering

SYSTEM AND METHOD FOR CONCURRENT PLACEMENT OF GATES AND ASSOCIATED...

Method for design optimization using logical and physical information