Eric T. Stubbs

Person

Boise, ID, US

People

Patents Grantslast 30 patents

Information Patent Grant
Actively driven VREF for input buffer noise immunity
- Patent number 7,400,544
- Issue date Jul 15, 2008
- Micron Technology, Inc.
- Eric T. Stubbs
- G11 - INFORMATION STORAGE
Information Patent Grant
Per-bit set-up and hold time adjustment for double-data rate synchr...
- Patent number 7,274,605
- Issue date Sep 25, 2007
- Micron Technology, Inc.
- Eric T. Stubbs
- G11 - INFORMATION STORAGE
Information Patent Grant
Integrated semiconductor memory chip with presence detect data capa...
- Patent number 7,152,143
- Issue date Dec 19, 2006
- Micron Technology, Inc.
- Eric T. Stubbs
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Per-bit set-up and hold time adjustment for double-data rate synchr...
- Patent number 7,116,589
- Issue date Oct 3, 2006
- Micron Technology, Inc.
- Eric T. Stubbs
- G11 - INFORMATION STORAGE
Information Patent Grant
Variable delay line
- Patent number 6,959,062
- Issue date Oct 25, 2005
- Micron Technology, Inc.
- Eric T. Stubbs
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Integrated semiconductor memory chip with presence detect data capa...
- Patent number 6,947,341
- Issue date Sep 20, 2005
- Micron Technology, Inc.
- Eric T. Stubbs
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Actively driven VREF for input buffer noise immunity
- Patent number 6,898,144
- Issue date May 24, 2005
- Micron Technology, Inc.
- Eric T. Stubbs
- G11 - INFORMATION STORAGE
Information Patent Grant
Method of preparing to test a capacitor
- Patent number 6,882,587
- Issue date Apr 19, 2005
- Micron Technology, Inc.
- Kurt D. Beigel
- G11 - INFORMATION STORAGE
Information Patent Grant
System and method for operating a memory array
- Patent number 6,862,224
- Issue date Mar 1, 2005
- Micron Technology, Inc.
- Eric T. Stubbs
- G11 - INFORMATION STORAGE
Information Patent Grant
Per-bit set-up and hold time adjustment for double-data rate synchr...
- Patent number 6,838,712
- Issue date Jan 4, 2005
- Micron Technology, Inc.
- Eric T. Stubbs
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and apparatus for reducing the lock time of a DLL
- Patent number 6,791,381
- Issue date Sep 14, 2004
- Micron Technology, Inc.
- Eric T. Stubbs
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Circuit and method for voltage regulation in a semiconductor device
- Patent number 6,778,452
- Issue date Aug 17, 2004
- Micron Technology, Inc.
- Kurt D. Beigel
- G11 - INFORMATION STORAGE
Information Patent Grant
Compensation for a delay locked loop
- Patent number 6,727,739
- Issue date Apr 27, 2004
- Micron Technology, Inc.
- Eric T. Stubbs
- G11 - INFORMATION STORAGE
Information Patent Grant
High speed memory architecture
- Patent number 6,667,911
- Issue date Dec 23, 2003
- Micron Technology, Inc.
- Eric T. Stubbs
- G11 - INFORMATION STORAGE
Information Patent Grant
Compensation for a delay locked loop
- Patent number 6,636,093
- Issue date Oct 21, 2003
- Micron Technology, Inc.
- Eric T. Stubbs
- G11 - INFORMATION STORAGE
Information Patent Grant
Integrated semiconductor memory chip with presence detect data capa...
- Patent number 6,625,692
- Issue date Sep 23, 2003
- Micron Technology, Inc.
- Eric T. Stubbs
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method of compensating for a defect within a semiconductor device
- Patent number 6,600,687
- Issue date Jul 29, 2003
- Micron Technology, Inc.
- Kurt D. Beigel
- G11 - INFORMATION STORAGE
Information Patent Grant
Actively driven VREF for input buffer noise immunity
- Patent number 6,597,619
- Issue date Jul 22, 2003
- Micron Technology, Inc.
- Eric T. Stubbs
- G11 - INFORMATION STORAGE
Information Patent Grant
On-chip testing circuit and method for integrated circuits
- Patent number 6,581,174
- Issue date Jun 17, 2003
- Micron Technology, Inc.
- Eric T. Stubbs
- G11 - INFORMATION STORAGE
Information Patent Grant
Method for reducing capacitive coupling between conductive lines
- Patent number 6,570,258
- Issue date May 27, 2003
- Micron Technology, Inc.
- Kin F. Ma
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of compensating for a defect within a semiconductor device
- Patent number 6,469,944
- Issue date Oct 22, 2002
- Micron Technology, Inc.
- Kurt D. Beigel
- G11 - INFORMATION STORAGE
Information Patent Grant
Driver circuit for a voltage-pulling device
- Patent number 6,452,846
- Issue date Sep 17, 2002
- Micron Technology, Inc.
- Kurt D. Beigel
- G11 - INFORMATION STORAGE
Information Patent Grant
Method of stressing a memory device
- Patent number 6,445,629
- Issue date Sep 3, 2002
- Micron Technology, Inc.
- Kurt D. Beigel
- G11 - INFORMATION STORAGE
Information Patent Grant
Method of testing a memory cell
- Patent number 6,418,071
- Issue date Jul 9, 2002
- Micron Technology, Inc.
- Kurt D. Beigel
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and apparatus for reducing the lock time of DLL
- Patent number 6,388,480
- Issue date May 14, 2002
- Micron Technology, Inc.
- Eric T. Stubbs
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method of testing a memory array
- Patent number 6,353,564
- Issue date Mar 5, 2002
- Micron Technology, Inc.
- Kurt D. Beigel
- G11 - INFORMATION STORAGE
Information Patent Grant
Margin-range apparatus for a sense amp's voltage-pulling tr...
- Patent number 6,335,888
- Issue date Jan 1, 2002
- Micron Technology, Inc.
- Kurt D. Beigel
- G11 - INFORMATION STORAGE
Information Patent Grant
On-chip testing circuit and method for integrated circuits
- Patent number 6,286,115
- Issue date Sep 4, 2001
- Micron Technology, Inc.
- Eric T. Stubbs
- G11 - INFORMATION STORAGE
Information Patent Grant
Method for reducing capactive coupling between conductive lines
- Patent number 6,259,162
- Issue date Jul 10, 2001
- Micron Technology, Inc.
- Kin F. Ma
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of detecting a short from a digit line pair to ground
- Patent number 6,226,210
- Issue date May 1, 2001
- Micron Technology, Inc.
- Kurt D. Beigel
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
Per-Bit Set-Up and Hold Time Adjustment for Double-Data Rate Synchr...
- Publication number 20060250862
- Publication date Nov 9, 2006
- Micron Technology, Inc.
- Eric T. Stubbs
- G11 - INFORMATION STORAGE
Information Patent Application
Actively driven VREF for input buffer noise immunity
- Publication number 20050207227
- Publication date Sep 22, 2005
- Eric T. Stubbs
- G11 - INFORMATION STORAGE
Information Patent Application
Integrated semiconductor memory chip with presence detect data capa...
- Publication number 20050099863
- Publication date May 12, 2005
- Eric T. Stubbs
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Per-bit set-up and hold time adjustment for double-data rate synchr...
- Publication number 20050057978
- Publication date Mar 17, 2005
- Eric T. Stubbs
- G11 - INFORMATION STORAGE
Information Patent Application
Method of preparing to test a capacitor
- Publication number 20040240286
- Publication date Dec 2, 2004
- Kurt D. Beigel
- G11 - INFORMATION STORAGE
Information Patent Application
Actively driven VREF for input buffer noise immunity
- Publication number 20040120205
- Publication date Jun 24, 2004
- Eric T. Stubbs
- G11 - INFORMATION STORAGE
Information Patent Application
Circuit and method for voltage regulation in a semiconductor device
- Publication number 20040095822
- Publication date May 20, 2004
- Kurt D. Beigel
- G11 - INFORMATION STORAGE
Information Patent Application
High speed memory array architecture
- Publication number 20040052128
- Publication date Mar 18, 2004
- Eric T. Stubbs
- G11 - INFORMATION STORAGE
Information Patent Application
Integrated semiconductor memory chip with presence detect data capa...
- Publication number 20040017723
- Publication date Jan 29, 2004
- Eric T. Stubbs
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PER-BIT SET-UP AND HOLD TIME ADJUSTMENT FOR DOUBLE-DATA RATE SYNCHR...
- Publication number 20030099135
- Publication date May 29, 2003
- Micron Technology, Inc.
- Eric T. Stubbs
- G11 - INFORMATION STORAGE
Information Patent Application
High speed memory array architecture
- Publication number 20030072183
- Publication date Apr 17, 2003
- Eric T. Stubbs
- G11 - INFORMATION STORAGE
Information Patent Application
Method of compensating for a defect within a semiconductor device
- Publication number 20030021171
- Publication date Jan 30, 2003
- Kurt D. Beigel
- G11 - INFORMATION STORAGE
Information Patent Application
Actively driven V REF for input buffer noise immunity
- Publication number 20020093868
- Publication date Jul 18, 2002
- Eric T. Stubbs
- G11 - INFORMATION STORAGE
Information Patent Application
Compensation for a delay locked loop
- Publication number 20020089361
- Publication date Jul 11, 2002
- Eric T. Stubbs
- G11 - INFORMATION STORAGE
Information Patent Application
Method and apparatus for reducing the lock time of a DLL
- Publication number 20020057119
- Publication date May 16, 2002
- Micron Technology, Inc.
- Eric T. Stubbs
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
On-chip testing circuit and method for integrated circuits
- Publication number 20020026606
- Publication date Feb 28, 2002
- Eric T. Stubbs
- G11 - INFORMATION STORAGE
Information Patent Application
Method of testing a memory array
- Publication number 20020018381
- Publication date Feb 14, 2002
- Kurt D. Beigel
- G11 - INFORMATION STORAGE
Information Patent Application
Method for reducing capacitive coupling between conductive lines
- Publication number 20010028112
- Publication date Oct 11, 2001
- Kin F. Ma
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Margin-range apparatus for a sense amp's voltage-pulling transistor
- Publication number 20010009522
- Publication date Jul 26, 2001
- Kurt D. Beigel
- G11 - INFORMATION STORAGE
Information Patent Application
Method of compensating for a defect within a semiconductor device
- Publication number 20010004333
- Publication date Jun 21, 2001
- Kurt D. Beigel
- G11 - INFORMATION STORAGE
Information Patent Application
METHOD OF TESTING A MEMORY CELL
- Publication number 20010002888
- Publication date Jun 7, 2001
- Kurt D. Beigel
- G11 - INFORMATION STORAGE
Information Patent Application
Method of stressing a memory device
- Publication number 20010002889
- Publication date Jun 7, 2001
- Kurt D. Beigel
- G11 - INFORMATION STORAGE

Eric T. Stubbs

Person

Patents Grantslast 30 patents

Actively driven VREF for input buffer noise immunity

Per-bit set-up and hold time adjustment for double-data rate synchr...

Integrated semiconductor memory chip with presence detect data capa...

Per-bit set-up and hold time adjustment for double-data rate synchr...

Variable delay line

Integrated semiconductor memory chip with presence detect data capa...

Actively driven VREF for input buffer noise immunity

Method of preparing to test a capacitor

System and method for operating a memory array

Per-bit set-up and hold time adjustment for double-data rate synchr...

Method and apparatus for reducing the lock time of a DLL

Circuit and method for voltage regulation in a semiconductor device

Compensation for a delay locked loop

High speed memory architecture

Compensation for a delay locked loop

Integrated semiconductor memory chip with presence detect data capa...

Method of compensating for a defect within a semiconductor device

Actively driven VREF for input buffer noise immunity

On-chip testing circuit and method for integrated circuits

Method for reducing capacitive coupling between conductive lines

Method of compensating for a defect within a semiconductor device

Driver circuit for a voltage-pulling device

Method of stressing a memory device

Method of testing a memory cell

Method and apparatus for reducing the lock time of DLL

Method of testing a memory array

Margin-range apparatus for a sense amp&#x00027;s voltage-pulling tr...

On-chip testing circuit and method for integrated circuits

Method for reducing capactive coupling between conductive lines

Method of detecting a short from a digit line pair to ground

Patents Applicationslast 30 patents

Per-Bit Set-Up and Hold Time Adjustment for Double-Data Rate Synchr...

Actively driven VREF for input buffer noise immunity

Integrated semiconductor memory chip with presence detect data capa...

Per-bit set-up and hold time adjustment for double-data rate synchr...

Method of preparing to test a capacitor

Actively driven VREF for input buffer noise immunity

Circuit and method for voltage regulation in a semiconductor device

High speed memory array architecture

Integrated semiconductor memory chip with presence detect data capa...

PER-BIT SET-UP AND HOLD TIME ADJUSTMENT FOR DOUBLE-DATA RATE SYNCHR...

High speed memory array architecture

Method of compensating for a defect within a semiconductor device

Actively driven V REF for input buffer noise immunity

Compensation for a delay locked loop

Method and apparatus for reducing the lock time of a DLL

On-chip testing circuit and method for integrated circuits

Method of testing a memory array

Method for reducing capacitive coupling between conductive lines

Margin-range apparatus for a sense amp's voltage-pulling transistor

Method of compensating for a defect within a semiconductor device

METHOD OF TESTING A MEMORY CELL

Method of stressing a memory device

Margin-range apparatus for a sense amp's voltage-pulling tr...