Claims
- 1. A method of testing a memory array storing a test data pattern, comprising:allowing a defect to hinder an ability to accurately read said test data pattern; preventing said memory array from restoring said ability to accurately read said test data pattern, wherein said act of preventing comprises at least slowing an effect of a voltage applied to said memory array; reading said test data pattern; and checking said test data pattern for changes.
- 2. A method of testing a memory array storing a test data pattern, comprising:allowing a defect to hinder an ability to accurately read said test data pattern; preventing said memory array from restoring said ability to accurately read said test data pattern, wherein preventing further comprises preventing said memory array from fully restoring said ability to accurately read said test data pattern; reading said test data pattern; and checking said test data pattern for changes.
- 3. The method in claim 2, further comprising:changing said test data pattern; writing said test data pattern to said memory array; and repeating said allowing, preventing, reading, and checking.
- 4. A method of testing a memory array storing a test data pattern, comprising:allowing a defect to hinder an ability to accurately read said test data pattern; preventing said memory array from restoring said ability to accurately read said test data pattern, said preventing act comprising: providing a voltage to said memory array, wherein said voltage has a common magnitude with that applied to said memory array in a non-test mode, and retarding an effect of said voltage; reading said test data pattern; and checking said test data pattern for changes.
- 5. A method of testing a memory array storing a test data pattern, comprising:allowing a defect to hinder an ability to accurately read said test data pattern; preventing said memory array from restoring said ability to accurately read said test data pattern, said preventing act comprising: configuring a first portion of said memory array to receive a voltage, configuring a second portion of said memory array to receive said voltage, and affecting said first portion with said voltage to a greater degree than said second portion; reading said test data pattern; and checking said test data pattern for changes.
RELATED APPLICATIONS
This application is a continuation of U.S. application Ser. No. 09/483,549, filed Jan. 14, 2000 now U.S. Pat. No. 6,181,617; which is a continuation of U.S. application Ser. No. 09/260,232, filed on Mar. 1, 1999 and issued as U.S. Pat. No. 6,028,799; which is a divisional of U.S. application Ser. No. 08/855,555, filed May 13, 1997 and issued as U.S. Pat. No. 5,877,993.
US Referenced Citations (21)
Continuations (2)
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Number |
Date |
Country |
Parent |
09/483549 |
Jan 2000 |
US |
Child |
09/735157 |
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US |
Parent |
09/260232 |
Mar 1999 |
US |
Child |
09/483549 |
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US |