Claims
- 1. A method of testing a memory cell having an equilibrate voltage, a logic voltage corresponding to a logic value, and a margin representing the difference between said equilibrate voltage and said logic voltage, comprising:enabling any defect of said memory cell to alter said margin; and reading data from said memory cell.
- 2. The method in claim 1, further comprising exacerbating any margin alteration from said defect.
RELATED APPLICATIONS
This application is a continuation of U.S. application Ser. No. 09/483,549, filed Jan. 14, 2000 now U.S. Pat. No. 6,181,617; which is a continuation of U.S. application Ser. No. 09/260,232, filed Mar. 1, 1999 and issued as U.S. Pat. No. 6,028,799; which is a divisional of U.S. application Ser. No. 08/855,555, filed May 13, 1997 and issued as U.S. Pat. No. 5,877,993.
US Referenced Citations (21)
Continuations (2)
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Number |
Date |
Country |
Parent |
09/483549 |
Jan 2000 |
US |
Child |
09/735329 |
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US |
Parent |
09/260232 |
Mar 1999 |
US |
Child |
09/483549 |
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US |