Hiroshi Otori

Person

Mizuho, JP

People

Patents Grantslast 30 patents

Information Patent Grant
Semiconductor memory device and semiconductor device
- Patent number 7,403,408
- Issue date Jul 22, 2008
- Hitachi, Ltd.
- Hiroshi Otori
- G11 - INFORMATION STORAGE
Information Patent Grant
System with meshed power and signal buses on cell array
- Patent number 7,323,727
- Issue date Jan 29, 2008
- Hitachi, Ltd.
- Goro Kitsukawa
- G11 - INFORMATION STORAGE
Information Patent Grant
System with meshed power and signal buses on cell array
- Patent number 7,211,842
- Issue date May 1, 2007
- Hitachi, Ltd.
- Goro Kitsukawa
- G11 - INFORMATION STORAGE
Information Patent Grant
System with meshed power and signal buses on cell array
- Patent number 6,967,371
- Issue date Nov 22, 2005
- Hitachi, Ltd.
- Goro Kitsukawa
- G11 - INFORMATION STORAGE
Information Patent Grant
System with meshed power and signal buses on cell array
- Patent number 6,831,317
- Issue date Dec 14, 2004
- Hitachi, Ltd.
- Goro Kitsukawa
- G11 - INFORMATION STORAGE
Information Patent Grant
System with meshed power and signal buses on cell array
- Patent number 6,815,742
- Issue date Nov 9, 2004
- Hitachi, Ltd.
- Goro Kitsukawa
- G11 - INFORMATION STORAGE
Information Patent Grant
Semiconductor memory including a circuit for selecting redundant me...
- Patent number 6,563,750
- Issue date May 13, 2003
- Hitachi, Ltd.
- Hiroshi Otori
- G11 - INFORMATION STORAGE
Information Patent Grant
System with meshed power and signal buses on cell array
- Patent number 6,512,257
- Issue date Jan 28, 2003
- Hitachi, Inc.
- Goro Kitsukawa
- G11 - INFORMATION STORAGE
Information Patent Grant
System with meshed power and signal buses on cell array
- Patent number 6,396,088
- Issue date May 28, 2002
- Hitachi, Ltd.
- Goro Kitsukawa
- G11 - INFORMATION STORAGE
Information Patent Grant
Semiconductor device
- Patent number 6,388,941
- Issue date May 14, 2002
- Hitachi, Ltd.
- Hiroshi Otori
- G11 - INFORMATION STORAGE
Information Patent Grant
System with meshed power and signal buses on cell array
- Patent number 6,288,925
- Issue date Sep 11, 2001
- Hitachi, Ltd.
- Goro Kitsukawa
- G11 - INFORMATION STORAGE
Information Patent Grant
System with meshed power and signal buses on cell array
- Patent number 6,115,279
- Issue date Sep 5, 2000
- Hitachi Ltd.
- Goro Kitsukawa
- G11 - INFORMATION STORAGE
Information Patent Grant
System with meshed power and signal buses on cell array
- Patent number 6,069,813
- Issue date May 30, 2000
- Hitachi, Ltd.
- Goro Kitsukawa
- G11 - INFORMATION STORAGE
Information Patent Grant
Sense amplifier driver having variable power-supply voltage
- Patent number 6,028,800
- Issue date Feb 22, 2000
- Hitachi Ltd, of Japan
- Takesada Akiba
- G11 - INFORMATION STORAGE
Information Patent Grant
System with meshed power and signal buses on cell array
- Patent number 5,953,242
- Issue date Sep 14, 1999
- Hitachi Ltd.
- Goro Kitsukawa
- G11 - INFORMATION STORAGE
Information Patent Grant
Semiconductor integrated circuit device having a constant delay-tim...
- Patent number 5,881,005
- Issue date Mar 9, 1999
- Hitachi, Ltd.
- Hiroshi Otori
- G11 - INFORMATION STORAGE
Information Patent Grant
Semiconductor integrated circuit device having a controlled overdri...
- Patent number 5,859,807
- Issue date Jan 12, 1999
- Hitachi, Ltd.
- Hiroshi Otori
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory regulator control method with flexibility for a wide change...
- Patent number 5,844,853
- Issue date Dec 1, 1998
- Texas Instruments, Inc.
- Goro Kitsukawa
- G11 - INFORMATION STORAGE
Information Patent Grant
Semiconductor integrated circuit device having means for peak curre...
- Patent number 5,793,694
- Issue date Aug 11, 1998
- Hitachi, Ltd.
- Takesada Akiba
- G11 - INFORMATION STORAGE
Information Patent Grant
Dynamic RAM and information processing system using the same
- Patent number 5,426,603
- Issue date Jun 20, 1995
- Hitachi, Ltd.
- Masayuki Nakamura
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
SYSTEM WITH MESHED POWER AND SIGNAL BUSES ON CELL ARRAY
- Publication number 20070158695
- Publication date Jul 12, 2007
- Hitachi, Ltd
- Goro Kitsukawa
- G11 - INFORMATION STORAGE
Information Patent Application
Semiconductor memory device and semiconductor device
- Publication number 20050259500
- Publication date Nov 24, 2005
- Hitachi, Ltd.
- Hiroshi Otori
- G11 - INFORMATION STORAGE
Information Patent Application
System with meshed power and signal buses on cell array
- Publication number 20050237778
- Publication date Oct 27, 2005
- HITACHI, LTD.
- Goro Kitsukawa
- G11 - INFORMATION STORAGE
Information Patent Application
System with meshed power and signal buses on cell array
- Publication number 20050035403
- Publication date Feb 17, 2005
- HITACHI, LTD.
- Goro Kitsukawa
- G11 - INFORMATION STORAGE
Information Patent Application
SYSTEM WITH MESHED POWER AND SIGNAL BUSES ON CELL ARRAY
- Publication number 20040129974
- Publication date Jul 8, 2004
- Hitachi, Ltd
- Goro Kitsukawa
- G11 - INFORMATION STORAGE
Information Patent Application
System with meshed power and signal buses on cell array
- Publication number 20030067018
- Publication date Apr 10, 2003
- Hitachi, Ltd
- Goro Kitsukawa
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
System with meshed power and signal buses on cell array
- Publication number 20020140015
- Publication date Oct 3, 2002
- Goro Kitsukawa
- G11 - INFORMATION STORAGE
Information Patent Application
Semiconductor device
- Publication number 20020118587
- Publication date Aug 29, 2002
- Hiroshi Otori
- G11 - INFORMATION STORAGE
Information Patent Application
Semiconductor device
- Publication number 20020006062
- Publication date Jan 17, 2002
- Hiroshi Otori
- G11 - INFORMATION STORAGE
Information Patent Application
System with meshed power and signal buses on cell array
- Publication number 20020000583
- Publication date Jan 3, 2002
- Goro Kitsukawa
- G11 - INFORMATION STORAGE

Hiroshi Otori

Person

Patents Grantslast 30 patents

Semiconductor memory device and semiconductor device

System with meshed power and signal buses on cell array

System with meshed power and signal buses on cell array

System with meshed power and signal buses on cell array

System with meshed power and signal buses on cell array

System with meshed power and signal buses on cell array

Semiconductor memory including a circuit for selecting redundant me...

System with meshed power and signal buses on cell array

System with meshed power and signal buses on cell array

Semiconductor device

System with meshed power and signal buses on cell array

System with meshed power and signal buses on cell array

System with meshed power and signal buses on cell array

Sense amplifier driver having variable power-supply voltage

System with meshed power and signal buses on cell array

Semiconductor integrated circuit device having a constant delay-tim...

Semiconductor integrated circuit device having a controlled overdri...

Memory regulator control method with flexibility for a wide change...

Semiconductor integrated circuit device having means for peak curre...

Dynamic RAM and information processing system using the same

Patents Applicationslast 30 patents

SYSTEM WITH MESHED POWER AND SIGNAL BUSES ON CELL ARRAY

Semiconductor memory device and semiconductor device

System with meshed power and signal buses on cell array

System with meshed power and signal buses on cell array

SYSTEM WITH MESHED POWER AND SIGNAL BUSES ON CELL ARRAY

System with meshed power and signal buses on cell array

System with meshed power and signal buses on cell array

Semiconductor device

Semiconductor device

System with meshed power and signal buses on cell array