Leland R. Nevill

Person

Boise, ID, US

People

Patents Grantslast 30 patents

Information Patent Grant
Error detection/correction based memory management
- Patent number 9,483,370
- Issue date Nov 1, 2016
- Micron Technology, Inc.
- Cory J. Reche
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method for isolating a short-circuited integrated circuit (IC) from...
- Patent number 7,567,091
- Issue date Jul 28, 2009
- Micron Technology, Inc.
- Warren M. Farnworth
- G01 - MEASURING TESTING
Information Patent Grant
Method and apparatus for identifying integrated circuits
- Patent number RE40623
- Issue date Jan 20, 2009
- Micron Technology, Inc.
- Leland R. Nevill
- 235 - Registers
Information Patent Grant
Device and method for isolating a short-circuited integrated circui...
- Patent number 7,323,896
- Issue date Jan 29, 2008
- Micron Technology, Inc.
- Warren M. Farnworth
- G01 - MEASURING TESTING
Information Patent Grant
System for isolating a short-circuited integrated circuit (IC) from...
- Patent number 7,315,179
- Issue date Jan 1, 2008
- Micron Technology, Inc.
- Warren M. Farnworth
- G01 - MEASURING TESTING
Information Patent Grant
Device and method for isolating a short-circuited integrated circui...
- Patent number 7,276,927
- Issue date Oct 2, 2007
- Micron Technology, Inc.
- Warren M. Farnworth
- G01 - MEASURING TESTING
Information Patent Grant
Method for isolating a short-circuited integrated circuit (IC) from...
- Patent number 7,276,926
- Issue date Oct 2, 2007
- Micron Technology, Inc.
- Warren M. Farnworth
- G01 - MEASURING TESTING
Information Patent Grant
Device and method for isolating a short-circuited integrated circui...
- Patent number 7,212,020
- Issue date May 1, 2007
- Micron Technology, Inc.
- Warren M. Farnworth
- G01 - MEASURING TESTING
Information Patent Grant
Device and method for isolating a short-circuited integrated circui...
- Patent number 7,034,561
- Issue date Apr 25, 2006
- Micron Technology, Inc.
- Warren M. Farnworth
- G01 - MEASURING TESTING
Information Patent Grant
Data compression circuit and method for testing memory devices
- Patent number RE38956
- Issue date Jan 31, 2006
- Micron Technology, Inc.
- Ray Beffa
- 365 - Static information storage and retrieval
Information Patent Grant
Integrated circuit package alignment feature
- Patent number 6,858,453
- Issue date Feb 22, 2005
- Micron Technology, Inc.
- David J. Corisis
- G01 - MEASURING TESTING
Information Patent Grant
Reduced terminal testing system
- Patent number 6,852,999
- Issue date Feb 8, 2005
- Micron Technology, Inc.
- Warren M. Farnworth
- G11 - INFORMATION STORAGE
Information Patent Grant
Integrated circuit package alignment feature
- Patent number 6,836,003
- Issue date Dec 28, 2004
- Micron Technology, Inc.
- David J. Corisis
- G01 - MEASURING TESTING
Information Patent Grant
Device and method for isolating a short-circuited integrated circui...
- Patent number 6,831,475
- Issue date Dec 14, 2004
- Micron Technology, Inc.
- Warren M. Farnworth
- G01 - MEASURING TESTING
Information Patent Grant
Reduced terminal testing system
- Patent number 6,815,968
- Issue date Nov 9, 2004
- Micron Technology, Inc.
- Warren M. Farnworth
- G11 - INFORMATION STORAGE
Information Patent Grant
Method of using a semiconductor chip package
- Patent number 6,682,946
- Issue date Jan 27, 2004
- Micron Technology, Inc.
- Jerrold L. King
- G01 - MEASURING TESTING
Information Patent Grant
Semiconductor chip package with alignment structure
- Patent number 6,670,720
- Issue date Dec 30, 2003
- Micron Technology, Inc.
- Jerrold L. King
- G01 - MEASURING TESTING
Information Patent Grant
Device and method for isolating a short-circuited integrated circui...
- Patent number 6,636,068
- Issue date Oct 21, 2003
- Warren M. Farnworth
- G01 - MEASURING TESTING
Information Patent Grant
Reduced terminal testing system
- Patent number 6,534,785
- Issue date Mar 18, 2003
- Micron Technology, Inc.
- Warren M. Farnworth
- G11 - INFORMATION STORAGE
Information Patent Grant
Device and method for isolating a short-circuited integrated circui...
- Patent number 6,452,415
- Issue date Sep 17, 2002
- Micron Technology, Inc.
- Warren M. Farnworth
- G01 - MEASURING TESTING
Information Patent Grant
Reduced terminal testing system
- Patent number 6,424,168
- Issue date Jul 23, 2002
- Micron Technology, Inc.
- Warren M. Farnworth
- G11 - INFORMATION STORAGE
Information Patent Grant
Method of aligning and testing a semiconductor chip package
- Patent number 6,420,195
- Issue date Jul 16, 2002
- Micron Technology, Inc.
- Jerrold L. King
- G01 - MEASURING TESTING
Information Patent Grant
Device and method for isolating a short-circuited integrated circui...
- Patent number 6,313,658
- Issue date Nov 6, 2001
- Micron Technology, Inc.
- Warren M. Farnworth
- G01 - MEASURING TESTING
Information Patent Grant
Reduced terminal testing system
- Patent number 6,292,009
- Issue date Sep 18, 2001
- Micron Technology, Inc.
- Warren M. Farnworth
- G11 - INFORMATION STORAGE
Information Patent Grant
Integrated circuit package including lead frame with electrically i...
- Patent number 6,246,108
- Issue date Jun 12, 2001
- Micron Technology, Inc.
- David J. Corisis
- G01 - MEASURING TESTING
Information Patent Grant
Wafer level burn-in of memory integrated circuits
- Patent number 6,233,185
- Issue date May 15, 2001
- Micron Technology, Inc.
- Ray Beffa
- G11 - INFORMATION STORAGE
Information Patent Grant
Semiconductor chip package
- Patent number 6,198,172
- Issue date Mar 6, 2001
- Micron Technology, Inc.
- Jerrold L. King
- G01 - MEASURING TESTING
Information Patent Grant
Integrated circuit module having on-chip surge capacitors
- Patent number 6,184,568
- Issue date Feb 6, 2001
- Micron Technology, Inc.
- Stanley N. Protigal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Uniform temperature environmental testing apparatus for semiconduct...
- Patent number 6,154,042
- Issue date Nov 28, 2000
- Micron Technology, Inc.
- Leland R. Nevill
- G01 - MEASURING TESTING
Information Patent Grant
Self-test of a memory device
- Patent number 6,119,251
- Issue date Sep 12, 2000
- Micron Technology, Inc.
- Eugene H. Cloud
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
ERROR DETECTION/CORRECTION BASED MEMORY MANAGEMENT
- Publication number 20140164824
- Publication date Jun 12, 2014
- Micron Technology, Inc.
- Cory J. Reche
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ERROR DETECTION/CORRECTION BASED MEMORY MANAGEMENT
- Publication number 20130073898
- Publication date Mar 21, 2013
- Micron Technology, Inc.
- Cory J. Reche
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEM FOR ISOLATING A SHORT-CIRCUITED INTEGRATED CIRCUIT (IC) FROM...
- Publication number 20090273360
- Publication date Nov 5, 2009
- Micron Technology, Inc.
- Warren M. Farnworth
- G01 - MEASURING TESTING
Information Patent Application
Method for Isolating a Short-Circuited Integrated Circuit (IC) From...
- Publication number 20080111574
- Publication date May 15, 2008
- Micron Technology, Inc.
- Warren M. Farnworth
- G01 - MEASURING TESTING
Information Patent Application
Device and method for isolating a short-circuited integrated circui...
- Publication number 20070103167
- Publication date May 10, 2007
- Warren M. Farnworth
- G01 - MEASURING TESTING
Information Patent Application
Device and method for isolating a short-circuited integrated circui...
- Publication number 20070075723
- Publication date Apr 5, 2007
- Warren M. Farnworth
- G01 - MEASURING TESTING
Information Patent Application
Device and method for isolating a short-circuited integrated circui...
- Publication number 20070075725
- Publication date Apr 5, 2007
- Warren M. Farnworth
- G01 - MEASURING TESTING
Information Patent Application
Device and method for isolating a short-circuited integrated circui...
- Publication number 20070075722
- Publication date Apr 5, 2007
- Warren M. Farnworth
- G01 - MEASURING TESTING
Information Patent Application
Device and method for isolating a short-circuited integrated circui...
- Publication number 20060192582
- Publication date Aug 31, 2006
- Warren M. Farnworth
- G01 - MEASURING TESTING
Information Patent Application
Device and method for isolating a short-circuited integrated circui...
- Publication number 20050093566
- Publication date May 5, 2005
- Warren M. Farnworth
- G01 - MEASURING TESTING
Information Patent Application
Device and method for isolating a short-circuited integrated circui...
- Publication number 20040130345
- Publication date Jul 8, 2004
- Warren M. Farnworth
- G01 - MEASURING TESTING
Information Patent Application
Integrated circuit module having on-chip surge capacitors
- Publication number 20040061198
- Publication date Apr 1, 2004
- Stanley N. Protigal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Semiconductor device system with impedance matching of control signals
- Publication number 20030205779
- Publication date Nov 6, 2003
- Stanley N. Protigal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Reduced terminal testing system
- Publication number 20030178692
- Publication date Sep 25, 2003
- Warren M. Farnworth
- G01 - MEASURING TESTING
Information Patent Application
Reduced terminal testing system
- Publication number 20030003606
- Publication date Jan 2, 2003
- Warren M. Farnworth
- G01 - MEASURING TESTING
Information Patent Application
Device and method for isolating a short-circuited integrated circui...
- Publication number 20020190707
- Publication date Dec 19, 2002
- Warren M. Farnworth
- G01 - MEASURING TESTING
Information Patent Application
Method of using a semiconductor chip package
- Publication number 20020110957
- Publication date Aug 15, 2002
- Jerrold L. King
- G01 - MEASURING TESTING
Information Patent Application
Reduced terminal testing system
- Publication number 20020050836
- Publication date May 2, 2002
- Warren M. Farnworth
- G01 - MEASURING TESTING
Information Patent Application
Device and method for isolating a short-circuited integrated circui...
- Publication number 20020030507
- Publication date Mar 14, 2002
- Warren M. Farnworth
- G01 - MEASURING TESTING
Information Patent Application
Integrated circuit module having on-chip surge capacitors
- Publication number 20010042899
- Publication date Nov 22, 2001
- Stanley N. Protigal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Integrated circuit package alignment feature
- Publication number 20010011762
- Publication date Aug 9, 2001
- David J. Corisis
- G01 - MEASURING TESTING
Information Patent Application
Semiconductor chip package
- Publication number 20010008283
- Publication date Jul 19, 2001
- Micron Technology, Inc.
- Jerrold L. King
- G01 - MEASURING TESTING

Leland R. Nevill

Person

Patents Grantslast 30 patents

Error detection/correction based memory management

Method for isolating a short-circuited integrated circuit (IC) from...

Method and apparatus for identifying integrated circuits

Device and method for isolating a short-circuited integrated circui...

System for isolating a short-circuited integrated circuit (IC) from...

Device and method for isolating a short-circuited integrated circui...

Method for isolating a short-circuited integrated circuit (IC) from...

Device and method for isolating a short-circuited integrated circui...

Device and method for isolating a short-circuited integrated circui...

Data compression circuit and method for testing memory devices

Integrated circuit package alignment feature

Reduced terminal testing system

Integrated circuit package alignment feature

Device and method for isolating a short-circuited integrated circui...

Reduced terminal testing system

Method of using a semiconductor chip package

Semiconductor chip package with alignment structure

Device and method for isolating a short-circuited integrated circui...

Reduced terminal testing system

Device and method for isolating a short-circuited integrated circui...

Reduced terminal testing system

Method of aligning and testing a semiconductor chip package

Device and method for isolating a short-circuited integrated circui...

Reduced terminal testing system

Integrated circuit package including lead frame with electrically i...

Wafer level burn-in of memory integrated circuits

Semiconductor chip package

Integrated circuit module having on-chip surge capacitors

Uniform temperature environmental testing apparatus for semiconduct...

Self-test of a memory device

Patents Applicationslast 30 patents

ERROR DETECTION/CORRECTION BASED MEMORY MANAGEMENT

ERROR DETECTION/CORRECTION BASED MEMORY MANAGEMENT

SYSTEM FOR ISOLATING A SHORT-CIRCUITED INTEGRATED CIRCUIT (IC) FROM...

Method for Isolating a Short-Circuited Integrated Circuit (IC) From...

Device and method for isolating a short-circuited integrated circui...

Device and method for isolating a short-circuited integrated circui...

Device and method for isolating a short-circuited integrated circui...

Device and method for isolating a short-circuited integrated circui...

Device and method for isolating a short-circuited integrated circui...

Device and method for isolating a short-circuited integrated circui...

Device and method for isolating a short-circuited integrated circui...

Integrated circuit module having on-chip surge capacitors

Semiconductor device system with impedance matching of control signals

Reduced terminal testing system

Reduced terminal testing system

Device and method for isolating a short-circuited integrated circui...

Method of using a semiconductor chip package

Reduced terminal testing system

Device and method for isolating a short-circuited integrated circui...

Integrated circuit module having on-chip surge capacitors

Integrated circuit package alignment feature

Semiconductor chip package