Rajeev Malik

Person

Pleasantville, NY, US

People

Patents Grantslast 30 patents

Information Patent Grant
Device having dual etch stop liner and reformed silicide layer and...
- Patent number 7,928,571
- Issue date Apr 19, 2011
- International Business Machines Corporation
- Dureseti Chidambarrao
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device structure having low and high performance devi...
- Patent number 7,776,695
- Issue date Aug 17, 2010
- International Business Machines Corporation
- John C. Arnold
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Device having enhanced stress state and related methods
- Patent number 7,732,270
- Issue date Jun 8, 2010
- International Business Machines Corporation
- Dureseti Chidambarrao
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Preventing cavitation in high aspect ratio dielectric regions of se...
- Patent number 7,683,434
- Issue date Mar 23, 2010
- International Business Machines Corporation
- Paul D. Agnello
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
OPC trimming for performance
- Patent number 7,627,836
- Issue date Dec 1, 2009
- International Business Machines Corporation
- James A. Culp
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Preventing cavitation in high aspect ratio dielectric regions of se...
- Patent number 7,459,384
- Issue date Dec 2, 2008
- International Business Machines Corporation
- Paul D. Agnello
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Device having dual etch stop liner and protective layer
- Patent number 7,446,395
- Issue date Nov 4, 2008
- International Business Machines Corporation
- Dureseti Chidambarrao
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Device having dual etch stop liner and reformed silicide layer and...
- Patent number 7,446,062
- Issue date Nov 4, 2008
- International Business Machines Corporation
- Dureseti Chidambarrao
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Device having enhanced stress state and related methods
- Patent number 7,348,635
- Issue date Mar 25, 2008
- International Business Machines Corporation
- Dureseti Chidambarrao
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for forming dual etch stop liner and protective layer in a s...
- Patent number 7,306,983
- Issue date Dec 11, 2007
- International Business Machines Corporation
- Dureseti Chidambarrao
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for manufacturing tungsten/polysilicon word line structure i...
- Patent number 7,030,012
- Issue date Apr 18, 2006
- International Business Machines Corporation
- Ramachandra Divakaruni
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Apparatus and method to improve resist line roughness in semiconduc...
- Patent number 7,018,779
- Issue date Mar 28, 2006
- International Business Machines Corporation
- Wai-kin Li
- Y10 - TECHNICAL SUBJECTS COVERED BY FORMER USPC
Information Patent Grant
Gate metal recess for oxidation protection and parasitic capacitanc...
- Patent number 6,908,806
- Issue date Jun 21, 2005
- Infineon Technologies AG
- Haining Yang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for forming TTO nitride liner for improved collar protection...
- Patent number 6,897,107
- Issue date May 24, 2005
- International Business Machines Corporation
- Rama Divakaruni
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
TTO nitride liner for improved collar protection and TTO reliability
- Patent number 6,809,368
- Issue date Oct 26, 2004
- International Business Machines Corporation
- Rama Divakaruni
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Extendible process for improved top oxide layer for DRAM array and...
- Patent number 6,794,242
- Issue date Sep 21, 2004
- Infineon Technologies AG
- Thomas W. Dyer
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Three layer aluminum deposition process for high aspect ratio CL co...
- Patent number 6,794,282
- Issue date Sep 21, 2004
- Infineon Technologies AG
- Thomas Goebel
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Structure and methods for process integration in vertical DRAM cell...
- Patent number 6,790,739
- Issue date Sep 14, 2004
- International Business Machines Corporation
- Rajeev Malik
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Self-aligned contact formation using double SiN spacers
- Patent number 6,724,054
- Issue date Apr 20, 2004
- Infineon Technologies AG
- Woo-tag Kang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Structure and method for dual work function logic devices in vertic...
- Patent number 6,635,526
- Issue date Oct 21, 2003
- Infineon Technologies AG
- Rajeev Malik
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Structure and methods for process integration in vertical DRAM cell...
- Patent number 6,620,676
- Issue date Sep 16, 2003
- International Business Machines Corporation
- Rajeev Malik
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Modified vertical MOSFET and methods of formation thereof
- Patent number 6,541,810
- Issue date Apr 1, 2003
- International Business Machines Corporation
- Ramachandra Divakaruni
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Process for protecting array top oxide
- Patent number 6,509,226
- Issue date Jan 21, 2003
- International Business Machines Corporation
- Venkatachalam C. Jaiprakash
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Orientation independent oxidation of silicon
- Patent number 6,358,867
- Issue date Mar 19, 2002
- Infineon Technologies AG
- Helmut Horst Tews
- C30 - CRYSTAL GROWTH
Information Patent Grant
Method for forming and filling isolation trenches
- Patent number 6,294,423
- Issue date Sep 25, 2001
- Infineon Technologies North America Corp.
- Rajeev Malik
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
PREVENTING CAVITATION IN HIGH ASPECT RATIO DIELECTRIC REGIONS OF SE...
- Publication number 20080303070
- Publication date Dec 11, 2008
- Paul D. Agnello
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DEVICE HAVING ENHANCED STRESS STATE AND RELATED METHODS
- Publication number 20080108228
- Publication date May 8, 2008
- International Business Machines Corporation
- Dureseti Chidambarrao
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DEVICE HAVING DUAL ETCH STOP LINER AND REFORMED SILICIDE LAYER AND...
- Publication number 20070296044
- Publication date Dec 27, 2007
- International Business Machines Corporation
- Dureseti Chidambarrao
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DEVICE HAVING DUAL ETCH STOP LINER AND PROTECTIVE LAYER
- Publication number 20070292696
- Publication date Dec 20, 2007
- International Business Machines Corporation
- Dureseti Chidambarrao
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR DEVICE STRUCTURE HAVING LOW AND HIGH PERFORMANCE DEVI...
- Publication number 20070158753
- Publication date Jul 12, 2007
- International Business Machines Corporation
- John C. Arnold
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
OPC TRIMMING FOR PERFORMANCE
- Publication number 20070106968
- Publication date May 10, 2007
- International Business Machines Corporation
- James A. Culp
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DEVICE HAVING DUAL ETCH STOP LINER AND PROTECTIVE LAYER AND RELATED...
- Publication number 20060128086
- Publication date Jun 15, 2006
- International Business Machines Corporation
- Dureseti Chidambarrao
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DEVICE HAVING ENHANCED STRESS STATE AND RELATED METHODS
- Publication number 20060128091
- Publication date Jun 15, 2006
- International Business Machines Corporation
- Dureseti Chidambarrao
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DEVICE HAVING DUAL ETCH STOP LINER AND REFORMED SILICIDE LAYER AND...
- Publication number 20060128145
- Publication date Jun 15, 2006
- International Business Machines Corporation
- Dureseti Chidambarrao
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Apparatus and method to improve resist line roughness in semiconduc...
- Publication number 20060110685
- Publication date May 25, 2006
- IBM CORPORATION
- Wai-kin Li
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Application
Nitride and polysilicon interface with titanium layer
- Publication number 20060001162
- Publication date Jan 5, 2006
- Ronald J. Schutz
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PREVENTING CAVITATION IN HIGH ASPECT RATIO DIELECTRIC REGIONS OF SE...
- Publication number 20050287798
- Publication date Dec 29, 2005
- International Business Machines Corporation
- Paul D. Agnello
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD FOR MANUFACTURING TUNGSTEN/POLYSILICON WORD LINE STRUCTURE I...
- Publication number 20050202672
- Publication date Sep 15, 2005
- International Business Machines Corporation
- Ramachandra Divakaruni
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Extendible process for improved top oxide layer for DRAM array and...
- Publication number 20040256651
- Publication date Dec 23, 2004
- Infineon Technologies AG
- Thomas W. Dyer
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
TTO nitride liner for improved collar protection and TTO reliability
- Publication number 20040155275
- Publication date Aug 12, 2004
- International Business Machines Corporation
- Rama Divakaruni
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Gate metal recess for oxidation protection and parasitic capacitanc...
- Publication number 20040150056
- Publication date Aug 5, 2004
- Infineon Technologies North America Corp.
- Haining Yang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Apparatus and method to improve resist line roughness in semiconduc...
- Publication number 20040131979
- Publication date Jul 8, 2004
- International Business Machines Corporation
- Wai-kin Li
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Application
TTO nitride liner for improved collar protection and TTO reliability
- Publication number 20040106258
- Publication date Jun 3, 2004
- International Business Machines Corporation
- Rama Divakaruni
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Three layer aluminum deposition process for high aspect ratio CL co...
- Publication number 20040102001
- Publication date May 27, 2004
- Infineon Technologies North America Corp.
- Thomas Goebel
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
STRUCTURE AND METHODS FOR PROCESS INTEGRATION IN VERTICAL DRAM CELL...
- Publication number 20030186502
- Publication date Oct 2, 2003
- International Business Machines Corporation
- Rajeev Malik
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Structure and methods for process integration in vertical DRAM cell...
- Publication number 20030003653
- Publication date Jan 2, 2003
- International Business Machines Corporation
- Rajeev Malik
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Modified vertical MOSFET and methods of formation thereof
- Publication number 20030001200
- Publication date Jan 2, 2003
- International Business Machines Corporation
- Ramachandra Divakaruni
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
TTO nitride liner for improved collar protection and TTO reliability
- Publication number 20020149047
- Publication date Oct 17, 2002
- International Business Machines Coporation
- Rama Divakaruni
- H01 - BASIC ELECTRIC ELEMENTS

Rajeev Malik

Person

Patents Grantslast 30 patents

Device having dual etch stop liner and reformed silicide layer and...

Semiconductor device structure having low and high performance devi...

Device having enhanced stress state and related methods

Preventing cavitation in high aspect ratio dielectric regions of se...

OPC trimming for performance

Preventing cavitation in high aspect ratio dielectric regions of se...

Device having dual etch stop liner and protective layer

Device having dual etch stop liner and reformed silicide layer and...

Device having enhanced stress state and related methods

Method for forming dual etch stop liner and protective layer in a s...

Method for manufacturing tungsten/polysilicon word line structure i...

Apparatus and method to improve resist line roughness in semiconduc...

Gate metal recess for oxidation protection and parasitic capacitanc...

Method for forming TTO nitride liner for improved collar protection...

TTO nitride liner for improved collar protection and TTO reliability

Extendible process for improved top oxide layer for DRAM array and...

Three layer aluminum deposition process for high aspect ratio CL co...

Structure and methods for process integration in vertical DRAM cell...

Self-aligned contact formation using double SiN spacers

Structure and method for dual work function logic devices in vertic...

Structure and methods for process integration in vertical DRAM cell...

Modified vertical MOSFET and methods of formation thereof

Process for protecting array top oxide

Orientation independent oxidation of silicon

Method for forming and filling isolation trenches

Patents Applicationslast 30 patents

PREVENTING CAVITATION IN HIGH ASPECT RATIO DIELECTRIC REGIONS OF SE...

DEVICE HAVING ENHANCED STRESS STATE AND RELATED METHODS

DEVICE HAVING DUAL ETCH STOP LINER AND REFORMED SILICIDE LAYER AND...

DEVICE HAVING DUAL ETCH STOP LINER AND PROTECTIVE LAYER

SEMICONDUCTOR DEVICE STRUCTURE HAVING LOW AND HIGH PERFORMANCE DEVI...

OPC TRIMMING FOR PERFORMANCE

DEVICE HAVING DUAL ETCH STOP LINER AND PROTECTIVE LAYER AND RELATED...

DEVICE HAVING ENHANCED STRESS STATE AND RELATED METHODS

DEVICE HAVING DUAL ETCH STOP LINER AND REFORMED SILICIDE LAYER AND...

Apparatus and method to improve resist line roughness in semiconduc...

Nitride and polysilicon interface with titanium layer

PREVENTING CAVITATION IN HIGH ASPECT RATIO DIELECTRIC REGIONS OF SE...

METHOD FOR MANUFACTURING TUNGSTEN/POLYSILICON WORD LINE STRUCTURE I...

Extendible process for improved top oxide layer for DRAM array and...

TTO nitride liner for improved collar protection and TTO reliability

Gate metal recess for oxidation protection and parasitic capacitanc...

Apparatus and method to improve resist line roughness in semiconduc...

TTO nitride liner for improved collar protection and TTO reliability

Three layer aluminum deposition process for high aspect ratio CL co...

STRUCTURE AND METHODS FOR PROCESS INTEGRATION IN VERTICAL DRAM CELL...

Structure and methods for process integration in vertical DRAM cell...

Modified vertical MOSFET and methods of formation thereof

TTO nitride liner for improved collar protection and TTO reliability