Patent Application
20060128145
(1) Technical Field
The present invention relates generally to semiconductor devices and more particularly to an NFET/PFET device having dual etch stop liners and silicide layers of normal thickness and resistance.
(2) Related Art
The application of stresses to field effect transistors (FETs) is known to improve their performance. When applied in a longitudinal direction (i.e., in the direction of current flow), tensile stress is known to enhance electron mobility (or n-channel FET (NFET) drive currents) while compressive stress is known to enhance hole mobility (or p-channel FET (PFET) drive currents).
One way to apply such stresses to a FET is the use of intrinsically-stressed barrier silicon nitride liners. For example, a tensile-stressed silicon nitride liner may be used to cause tension in an NFET channel while a compressively-stressed silicon nitride liner may be used to cause compression in a PFET channel. Accordingly, a dual/hybrid liner scheme is necessary to induce the desired stresses in an adjacent NFET and PFET.
In the formation of a dual/hybrid barrier silicon nitride liners for stress enhancement of NFET/PFET devices, the first deposited liner must be removed in one of the two FET regions by patterning and etching. For example,
Referring to
In methods currently known in the art, a second silicon nitride liner is deposited onto device 100 after etching, resulting in silicide layers of different thicknesses adjacent NFET 140 and PFET 150. In addition to a difference in thickness, etched silicide layer 132a-b exhibits increased silicide resistance (Rs) relative to silicide layer 130a-b.
Silicide layer 130a-b normally has a thickness between about 15 nm and about 50 nm, with a corresponding Rs between about 6 ohm/sq and about 20 ohm/sq. By comparison, etched silicide layer 132a-b may have a thickness between about 5 nm and about 40 nm, with a corresponding Rs between about 12 ohm/sq and about 40 ohm/sq.
Particularly in technologies beyond 90 nm, which utilize very ultra small gatelengths (e.g., <35 nm) and diffusion widths (e.g., <100 nm), such an increase in Rs is unacceptable for at least two reasons. First, the increases in Rs will impact performance of the device. Second, erosion of the silicide layer during the overetch increases the chance of failure by the polysilicon conductor (PC)-opens mechanism (i.e., the silicide on top of the PC is eroded or absent).
Accordingly, a need exists for a semiconductor device having dual etch stop liners and silicide layers of normal thickness and resistance and methods for the manufacture of such a device.
The present invention provides a semiconductor device having dual silicon nitride liners and a reformed silicide layer and related methods for the manufacture of such a device. The reformed silicide layer has a thickness and resistance substantially similar to a silicide layer not exposed to the formation of the dual silicon nitride liners. A first aspect of the invention provides a method for use in the manufacture of a semiconductor device comprising the steps of applying a first silicon nitride liner to a silicide layer, removing a portion of the first silicon nitride liner, reforming a portion of the silicide layer removed during the removal step, and applying a second silicon nitride liner to the silicide layer.
A second aspect of the invention provides a method for use in the manufacture of a semiconductor device having an NFET and a PFET, comprising the steps of applying a first silicon nitride liner to the NFET, PFET, and a silicide layer adjacent at least one of the NFET and the PFET, removing a portion of the first silicon nitride liner adjacent one of the NFET and the PFET, reforming a portion of the silicide layer removed during the removal step, and applying a second silicon nitride liner to the reformed silicide layer and the one of the NFET and the PFET.
A third aspect of the invention provides a method of reforming a portion of a silicide layer, comprising the steps of applying a metal layer to a remaining portion of an etched silicide layer, and forming a silicide with the metal layer and the remaining portion of the silicide layer.
A fourth aspect of the invention provides a semiconductor device, comprising a first silicon nitride liner, a second silicon nitride liner, and a partially reformed silicide layer, wherein a portion of the silicide layer is formed by the resilicidation of a deposited metal.
The foregoing and other features of the invention will be apparent from the following more particular description of embodiments of the invention.
The embodiments of this invention will be described in detail, with reference to the following figures, wherein like designations denote like elements, and wherein:
Referring to
In
Referring now to
Finally, in
While formation of device 200 has been described as involving the deposition of a tensile silicon nitride liner 260 and the later deposition of a compressive silicon nitride liner 270, it should be appreciated that the order of deposition of these liners may be reversed. That is, it is also within the scope of the present invention to form device 200 by the first deposition of a compressive silicon nitride liner 270, etching of compressive silicon nitride liner 270 from an area around NFET 240, resilicidation of etched silicide layer 232a-b (this time adjacent NFET 240 rather than PFET 250), deposition of a tensile silicon nitride liner 260, and patterning and etching of tensile silicon nitride liner 260 from an area around PFET 250.
While this invention has been described in conjunction with the specific embodiments outlined above, it is evident that many alternatives, modifications and variations will be apparent to those skilled in the art. Accordingly, the embodiments of the invention as set forth above are intended to be illustrative, not limiting. Various changes may be made without departing from the spirit and scope of the invention as defined in the following claims.
