Rustom Irani

Person

Santa Clara, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Non-volatile memory structure and method of fabrication
- Patent number 7,964,459
- Issue date Jun 21, 2011
- Spansion Israel Ltd.
- Eli Lusky
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Forming silicon trench isolation (STI) in semiconductor devices sel...
- Patent number 7,811,887
- Issue date Oct 12, 2010
- Saifun Semiconductors Ltd.
- Rustom Irani
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Dense non-volatile memory array and method of fabrication
- Patent number 7,804,126
- Issue date Sep 28, 2010
- Saifun Semiconductors Ltd.
- Boaz Eitan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Dense non-volatile memory array and method of fabrication
- Patent number 7,786,512
- Issue date Aug 31, 2010
- Saifun Semiconductors Ltd.
- Ilan Bloom
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Double density NROM with nitride strips (DDNS)
- Patent number 7,638,835
- Issue date Dec 29, 2009
- Saifun Semiconductors Ltd.
- Rustom Irani
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Non-volatile memory structure and method of fabrication
- Patent number 7,638,850
- Issue date Dec 29, 2009
- Saifun Semiconductors Ltd.
- Eli Lusky
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Process for manufacturing semiconductor integrated memory devices w...
- Patent number 6,300,195
- Issue date Oct 9, 2001
- STMicroelectronics, SRL
- Pierantonio Pozzoni
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Scalable EPROM array
- Patent number 5,910,016
- Issue date Jun 8, 1999
- WaferScale Integration, Inc.
- Reza Kazerounian
- G11 - INFORMATION STORAGE
Information Patent Grant
Operating method for ROM array which minimizes band-to-band tunneling
- Patent number 5,838,046
- Issue date Nov 17, 1998
- WaferScale Integration Inc.
- Rustom F. Irani
- G11 - INFORMATION STORAGE
Information Patent Grant
Manufacturing method for ROM array with minimal band-to-band tunneling
- Patent number 5,683,925
- Issue date Nov 4, 1997
- WaferScale Integration Inc.
- Rustom F. Irani
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Scalable EPROM array with thick and thin non-field oxide gate insul...
- Patent number 5,623,443
- Issue date Apr 22, 1997
- WaferScale Integration, Inc.
- Reza Kazerounian
- G11 - INFORMATION STORAGE
Information Patent Grant
EPROM virtual ground array
- Patent number 5,151,375
- Issue date Sep 29, 1992
- WaferScale Integration, Inc.
- Reza Kazerounian
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
FORMING SILICON TRENCH ISOLATION (STI) IN SEMICONDUCTOR DEVICES SEL...
- Publication number 20110057241
- Publication date Mar 10, 2011
- Rustom IRANI
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Non-volatile memory structure and method of fabrication
- Publication number 20100173464
- Publication date Jul 8, 2010
- Eli Lusky
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Transition areas for dense memory arrays
- Publication number 20080266954
- Publication date Oct 30, 2008
- Boaz Eitan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Transition areas for dense memory arrays
- Publication number 20080239807
- Publication date Oct 2, 2008
- Boaz Eitan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Forming silicon trench isolation (STI) in semiconductor devices sel...
- Publication number 20080128774
- Publication date Jun 5, 2008
- Rustom IRANI
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Forming buried contact etch stop layer (CESL) in semiconductor devi...
- Publication number 20080111182
- Publication date May 15, 2008
- Rustom Irani
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
High aspect ration bitline oxides
- Publication number 20080025084
- Publication date Jan 31, 2008
- Rustom Irani
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Double density NROM with nitride strips (DDNS)
- Publication number 20070200180
- Publication date Aug 30, 2007
- Rustom Irani
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Transition areas for dense memory arrays
- Publication number 20070120180
- Publication date May 31, 2007
- Boaz Eitan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Dense non-volatile memory array and method of fabrication
- Publication number 20070051982
- Publication date Mar 8, 2007
- SAIFUN SEMICONDUCTORS LTD.
- Ilan Bloom
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Dense non-volatile memory array and method of fabrication
- Publication number 20070048940
- Publication date Mar 1, 2007
- SAIFUN SEMICONDUCTORS LTD.
- Boaz Eitan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MEMORY CELL WITH DOUBLE BB IMPLANT
- Publication number 20060261418
- Publication date Nov 23, 2006
- SAIFUN SEMICONDUCTORS LTD.
- Boaz Eitan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Non-volatile memory structure and method of fabrication
- Publication number 20060211188
- Publication date Sep 21, 2006
- SAIFUN SEMICONDUCTORS LTD.
- Eli Lusky
- H01 - BASIC ELECTRIC ELEMENTS

Rustom Irani

Person

Patents Grantslast 30 patents

Non-volatile memory structure and method of fabrication

Forming silicon trench isolation (STI) in semiconductor devices sel...

Dense non-volatile memory array and method of fabrication

Dense non-volatile memory array and method of fabrication

Double density NROM with nitride strips (DDNS)

Non-volatile memory structure and method of fabrication

Process for manufacturing semiconductor integrated memory devices w...

Scalable EPROM array

Operating method for ROM array which minimizes band-to-band tunneling

Manufacturing method for ROM array with minimal band-to-band tunneling

Scalable EPROM array with thick and thin non-field oxide gate insul...

EPROM virtual ground array

Patents Applicationslast 30 patents

FORMING SILICON TRENCH ISOLATION (STI) IN SEMICONDUCTOR DEVICES SEL...

Non-volatile memory structure and method of fabrication

Transition areas for dense memory arrays

Transition areas for dense memory arrays

Forming silicon trench isolation (STI) in semiconductor devices sel...

Forming buried contact etch stop layer (CESL) in semiconductor devi...

High aspect ration bitline oxides

Double density NROM with nitride strips (DDNS)

Transition areas for dense memory arrays

Dense non-volatile memory array and method of fabrication

Dense non-volatile memory array and method of fabrication

MEMORY CELL WITH DOUBLE BB IMPLANT

Non-volatile memory structure and method of fabrication