Sailesh KUMAR

Person

San Jose, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
System on chip (SoC) builder
- Patent number 11,176,302
- Issue date Nov 16, 2021
- Netspeed Systems, Inc.
- Nishant Rao
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Application mapping on hardened network-on-chip (NoC) of field-prog...
- Patent number 11,023,377
- Issue date Jun 1, 2021
- Netspeed Systems, Inc.
- Sailesh Kumar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Repository of integration description of hardware intellectual prop...
- Patent number 10,896,476
- Issue date Jan 19, 2021
- Netspeed Systems, Inc.
- Nishant Rao
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Interface virtualization and fast path for Network on Chip
- Patent number 10,749,811
- Issue date Aug 18, 2020
- Netspeed Systems, Inc.
- Joseph Rowlands
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Interface virtualization and fast path for network on chip
- Patent number 10,735,335
- Issue date Aug 4, 2020
- Netspeed Systems, Inc.
- Joseph Rowlands
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Systems and methods for facilitating low power on a network-on-chip
- Patent number 10,613,616
- Issue date Apr 7, 2020
- Netspeed Systems, Inc.
- James A. Bauman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systems and methods for facilitating low power on a network-on-chip
- Patent number 10,564,703
- Issue date Feb 18, 2020
- Netspeed Systems, Inc.
- James A. Bauman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systems and methods for facilitating low power on a network-on-chip
- Patent number 10,564,704
- Issue date Feb 18, 2020
- NetSpeed Systems, Inc.
- James A. Bauman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Heterogeneous SoC IP core placement in an interconnect to optimize...
- Patent number 10,554,496
- Issue date Feb 4, 2020
- NetSpeed Systems
- Eric Norige
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Automatic crossbar generation and router connections for network-on...
- Patent number 10,547,514
- Issue date Jan 28, 2020
- Netspeed Systems, Inc.
- Nishant Rao
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Automatic performance characterization of a network-on-chip (NOC) i...
- Patent number 10,528,682
- Issue date Jan 7, 2020
- NetSpeed Systems
- Sailesh Kumar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Buffer sizing of a NoC through machine learning
- Patent number 10,523,599
- Issue date Dec 31, 2019
- Netspeed Systems, Inc.
- Eric Norige
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
System level simulation in Network on Chip architecture
- Patent number 10,496,770
- Issue date Dec 3, 2019
- Sailesh Kumar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cost management against requirements for the generation of a NoC
- Patent number 10,469,338
- Issue date Nov 5, 2019
- William John Bainbridge
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cost management against requirements for the generation of a NoC
- Patent number 10,469,337
- Issue date Nov 5, 2019
- William John Bainbridge
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systems and methods for facilitating low power on a network-on-chip
- Patent number 10,452,124
- Issue date Oct 22, 2019
- James A. Bauman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cost management against requirements for the generation of a NoC
- Patent number 10,419,300
- Issue date Sep 17, 2019
- William John Bainbridge
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Heterogeneous channel capacities in an interconnect
- Patent number 10,355,996
- Issue date Jul 16, 2019
- Sailesh Kumar
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
System-on-chip (SoC) optimization through transformation and genera...
- Patent number 10,348,563
- Issue date Jul 9, 2019
- Nishant Rao
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Automatic generation of power management sequence in a SoC or NoC
- Patent number 10,324,509
- Issue date Jun 18, 2019
- Anup Gangwar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systems and methods for NoC construction
- Patent number 10,298,485
- Issue date May 21, 2019
- Pier Giorgio Raponi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Generating physically aware network-on-chip design from a physical...
- Patent number 10,218,580
- Issue date Feb 26, 2019
- NetSpeed Systems
- Rajesh Chopra
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Generation of network-on-chip layout based on user specified topolo...
- Patent number 10,218,581
- Issue date Feb 26, 2019
- NetSpeed Systems
- Pier Giorgio Raponi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
QoS in a system with end-to-end flow control and QoS aware buffer a...
- Patent number 10,110,499
- Issue date Oct 23, 2018
- NetSpeed Systems
- Sailesh Kumar
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Extracting features from a NoC for machine learning construction
- Patent number 10,084,725
- Issue date Sep 25, 2018
- Netspeed Systems, Inc.
- Pier Giorgio Raponi
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Streaming bridge design with host interfaces and network on chip (N...
- Patent number 10,084,692
- Issue date Sep 25, 2018
- Netspeed Systems, Inc.
- Rajesh Chopra
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Clock gating for system-on-chip elements
- Patent number 10,074,053
- Issue date Sep 11, 2018
- NetSpeed Systems
- Sailesh Kumar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Buffer sizing of a NoC through machine learning
- Patent number 10,063,496
- Issue date Aug 28, 2018
- NETSPEED SYSTEMS INC.
- Eric Norige
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Generation of network-on-chip layout based on user specified topolo...
- Patent number 10,050,843
- Issue date Aug 14, 2018
- NetSpeed Systems
- Pier Giorgio Raponi
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Automatic generation of power management sequence in a SoC or NoC
- Patent number 10,042,404
- Issue date Aug 7, 2018
- NetSpeed Systems
- Anup Gangwar
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
APPLICATION MAPPING ON HARDENED NETWORK-ON-CHIP (NOC) OF FIELD-PROG...
- Publication number 20220012177
- Publication date Jan 13, 2022
- NetSpeed Systems, Inc.
- Sailesh KUMAR
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPLICATION MAPPING ON HARDENED NETWORK-ON-CHIP (NOC) OF FIELD-PROG...
- Publication number 20190266089
- Publication date Aug 29, 2019
- NetSpeed Systems, Inc.
- Sailesh KUMAR
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEM ON CHIP (SOC) BUILDER
- Publication number 20190266307
- Publication date Aug 29, 2019
- NetSpeed Systems, Inc.
- Nishant RAO
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
BACKBONE NETWORK-ON-CHIP (NOC) FOR FIELD-PROGRAMMABLE GATE ARRAY (F...
- Publication number 20190266088
- Publication date Aug 29, 2019
- NetSpeed Systems, Inc.
- Sailesh KUMAR
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEMS AND METHODS FOR MAINTAINING NETWORK-ON-CHIP (NOC) SAFETY AN...
- Publication number 20190260504
- Publication date Aug 22, 2019
- NetSpeed Systems, Inc.
- Joji Philip
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
REPOSITORY OF INTEGRATION DESCRIPTION OF HARDWARE INTELLECTUAL PROP...
- Publication number 20190259113
- Publication date Aug 22, 2019
- NetSpeed Systems, Inc.
- Nishant RAO
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
AUTOMATIC CROSSBAR GENERATION AND ROUTER CONNECTIONS FOR NETWORK-ON...
- Publication number 20190260644
- Publication date Aug 22, 2019
- NetSpeed Systems, Inc.
- Nishant RAO
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Buffer Sizing of a NoC Through Machine Learning
- Publication number 20180324113
- Publication date Nov 8, 2018
- NetSpeed Systems, Inc.
- Eric NORIGE
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
GENERATION OF NETWORK-ON-CHIP LAYOUT BASED ON USER SPECIFIED TOPOLO...
- Publication number 20180302293
- Publication date Oct 18, 2018
- NetSpeed Systems, Inc.
- Pier Giorgio RAPONI
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
SYSTEM-ON-CHIP (SOC) OPTIMIZATION THROUGH TRANSFORMATION AND GENERA...
- Publication number 20180227180
- Publication date Aug 9, 2018
- NetSpeed Systems, Inc.
- Nishant RAO
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Systems and Methods for NoC Construction
- Publication number 20180227215
- Publication date Aug 9, 2018
- NetSpeed Systems, Inc.
- Pier Giorgio RAPONI
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Cost Management Against Requirements for the Generation of a NoC
- Publication number 20180219746
- Publication date Aug 2, 2018
- NetSpeed Systems, Inc.
- William John BAINBRIDGE
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Cost Management Against Requirements for the Generation of a NoC
- Publication number 20180219738
- Publication date Aug 2, 2018
- NetSpeed Systems, Inc.
- William John BAINBRIDGE
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Cost Management Against Requirements for the Generation of a NoC
- Publication number 20180219747
- Publication date Aug 2, 2018
- NetSpeed Systems, Inc.
- William John BAINBRIDGE
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Infrastructure to Apply Machine Learning for NoC Construction
- Publication number 20180198687
- Publication date Jul 12, 2018
- NetSpeed Systems, Inc.
- Nishant RAO
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
EXTRACTING FEATURES FROM A NoC FOR MACHINE LEARNING CONSTRUCTION
- Publication number 20180198734
- Publication date Jul 12, 2018
- NetSpeed Systems, Inc.
- Pier Giorgio RAPONI
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Metrics to Train Machine Learning Predictor for NoC Construction
- Publication number 20180197110
- Publication date Jul 12, 2018
- NetSpeed Systems, Inc.
- Nishant RAO
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Strategies for NoC Construction Using Machine Learning
- Publication number 20180198682
- Publication date Jul 12, 2018
- NetSpeed Systems, Inc.
- Nishant RAO
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Buffer Sizing of a NoC Through Machine Learning
- Publication number 20180198738
- Publication date Jul 12, 2018
- NetSpeed Systems, Inc.
- Eric NORIGE
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
INTERFACE VIRTUALIZATION AND FAST PATH FOR NETWORK ON CHIP
- Publication number 20180191626
- Publication date Jul 5, 2018
- NetSpeed Systems, Inc.
- Joseph Rowlands
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
TRAFFIC MAPPING OF A NETWORK ON CHIP THROUGH MACHINE LEARNING
- Publication number 20180183728
- Publication date Jun 28, 2018
- NetSpeed Systems, Inc.
- Sailesh KUMAR
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
INTERFACE VIRTUALIZATION AND FAST PATH FOR NETWORK ON CHIP
- Publication number 20180183722
- Publication date Jun 28, 2018
- NetSpeed Systems, Inc.
- Joseph Rowlands
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
SYSTEM AND METHOD FOR GROUPING OF NETWORK ON CHIP (NOC) ELEMENTS
- Publication number 20180183672
- Publication date Jun 28, 2018
- NetSpeed Systems, Inc.
- Eric Norige
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
INTERFACE VIRTUALIZATION AND FAST PATH FOR NETWORK ON CHIP
- Publication number 20180183721
- Publication date Jun 28, 2018
- NetSpeed Systems, Inc.
- Joseph Rowlands
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
TRAFFIC MAPPING OF A NETWORK ON CHIP THROUGH MACHINE LEARNING
- Publication number 20180183726
- Publication date Jun 28, 2018
- NetSpeed Systems, Inc.
- Sailesh KUMAR
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
TRAFFIC MAPPING OF A NETWORK ON CHIP THROUGH MACHINE LEARNING
- Publication number 20180183727
- Publication date Jun 28, 2018
- NetSpeed Systems, Inc.
- Sailesh KUMAR
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
AUTOMATIC GENERATION OF POWER MANAGEMENT SEQUENCE IN A SOC OR NOC
- Publication number 20180181174
- Publication date Jun 28, 2018
- NetSpeed Systems, Inc.
- Anup GANGWAR
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEMS AND METHODS FOR FACILITATING LOW POWER ON A NETWORK-ON-CHIP
- Publication number 20180181190
- Publication date Jun 28, 2018
- NetSpeed Systems, Inc.
- James A. BAUMAN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEMS AND METHODS FOR FACILITATING LOW POWER ON A NETWORK-ON-CHIP
- Publication number 20180181191
- Publication date Jun 28, 2018
- NetSpeed Systems, Inc.
- James A. BAUMAN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
AUTOMATIC GENERATION OF POWER MANAGEMENT SEQUENCE IN A SOC OR NOC
- Publication number 20180181173
- Publication date Jun 28, 2018
- NetSpeed Systems, Inc.
- Anup GANGWAR
- G06 - COMPUTING CALCULATING COUNTING

Sailesh KUMAR

Person

Patents Grantslast 30 patents

System on chip (SoC) builder

Application mapping on hardened network-on-chip (NoC) of field-prog...

Repository of integration description of hardware intellectual prop...

Interface virtualization and fast path for Network on Chip

Interface virtualization and fast path for network on chip

Systems and methods for facilitating low power on a network-on-chip

Systems and methods for facilitating low power on a network-on-chip

Systems and methods for facilitating low power on a network-on-chip

Heterogeneous SoC IP core placement in an interconnect to optimize...

Automatic crossbar generation and router connections for network-on...

Automatic performance characterization of a network-on-chip (NOC) i...

Buffer sizing of a NoC through machine learning

System level simulation in Network on Chip architecture

Cost management against requirements for the generation of a NoC

Cost management against requirements for the generation of a NoC

Systems and methods for facilitating low power on a network-on-chip

Cost management against requirements for the generation of a NoC

Heterogeneous channel capacities in an interconnect

System-on-chip (SoC) optimization through transformation and genera...

Automatic generation of power management sequence in a SoC or NoC

Systems and methods for NoC construction

Generating physically aware network-on-chip design from a physical...

Generation of network-on-chip layout based on user specified topolo...

QoS in a system with end-to-end flow control and QoS aware buffer a...

Extracting features from a NoC for machine learning construction

Streaming bridge design with host interfaces and network on chip (N...

Clock gating for system-on-chip elements

Buffer sizing of a NoC through machine learning

Generation of network-on-chip layout based on user specified topolo...

Automatic generation of power management sequence in a SoC or NoC

Patents Applicationslast 30 patents

APPLICATION MAPPING ON HARDENED NETWORK-ON-CHIP (NOC) OF FIELD-PROG...

APPLICATION MAPPING ON HARDENED NETWORK-ON-CHIP (NOC) OF FIELD-PROG...

SYSTEM ON CHIP (SOC) BUILDER

BACKBONE NETWORK-ON-CHIP (NOC) FOR FIELD-PROGRAMMABLE GATE ARRAY (F...

SYSTEMS AND METHODS FOR MAINTAINING NETWORK-ON-CHIP (NOC) SAFETY AN...

REPOSITORY OF INTEGRATION DESCRIPTION OF HARDWARE INTELLECTUAL PROP...

AUTOMATIC CROSSBAR GENERATION AND ROUTER CONNECTIONS FOR NETWORK-ON...

Buffer Sizing of a NoC Through Machine Learning

GENERATION OF NETWORK-ON-CHIP LAYOUT BASED ON USER SPECIFIED TOPOLO...

SYSTEM-ON-CHIP (SOC) OPTIMIZATION THROUGH TRANSFORMATION AND GENERA...

Systems and Methods for NoC Construction

Cost Management Against Requirements for the Generation of a NoC

Cost Management Against Requirements for the Generation of a NoC

Cost Management Against Requirements for the Generation of a NoC

Infrastructure to Apply Machine Learning for NoC Construction

EXTRACTING FEATURES FROM A NoC FOR MACHINE LEARNING CONSTRUCTION

Metrics to Train Machine Learning Predictor for NoC Construction

Strategies for NoC Construction Using Machine Learning

Buffer Sizing of a NoC Through Machine Learning

INTERFACE VIRTUALIZATION AND FAST PATH FOR NETWORK ON CHIP

TRAFFIC MAPPING OF A NETWORK ON CHIP THROUGH MACHINE LEARNING

INTERFACE VIRTUALIZATION AND FAST PATH FOR NETWORK ON CHIP

SYSTEM AND METHOD FOR GROUPING OF NETWORK ON CHIP (NOC) ELEMENTS

INTERFACE VIRTUALIZATION AND FAST PATH FOR NETWORK ON CHIP

TRAFFIC MAPPING OF A NETWORK ON CHIP THROUGH MACHINE LEARNING

TRAFFIC MAPPING OF A NETWORK ON CHIP THROUGH MACHINE LEARNING

AUTOMATIC GENERATION OF POWER MANAGEMENT SEQUENCE IN A SOC OR NOC

SYSTEMS AND METHODS FOR FACILITATING LOW POWER ON A NETWORK-ON-CHIP

SYSTEMS AND METHODS FOR FACILITATING LOW POWER ON A NETWORK-ON-CHIP

AUTOMATIC GENERATION OF POWER MANAGEMENT SEQUENCE IN A SOC OR NOC