Somchai Nondhasitthichai

Person

Bangkok, TH

People

Patents Grantslast 30 patents

Information Patent Grant
Semiconductor package with partial plating on contact side surfaces
- Patent number 10,515,878
- Issue date Dec 24, 2019
- UTAC HEADQUARTERS PTE. LTD.
- Somchai Nondhasitthichai
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor package with partial plating on contact side surfaces
- Patent number 10,204,850
- Issue date Feb 12, 2019
- UTAC HEADQUARTERS PTE, LTD.
- Somchai Nondhasitthichai
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Flip chip cavity package
- Patent number 9,947,605
- Issue date Apr 17, 2018
- UTAC HEADQUARTERS PTE. LTD.
- Saravuth Sirinorakul
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Molded leadframe substrate semiconductor package
- Patent number 9,899,208
- Issue date Feb 20, 2018
- UTAC Thai Limited
- Somchai Nondhasitthichai
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Singulation method for semiconductor package with plating on side o...
- Patent number 9,818,676
- Issue date Nov 14, 2017
- UTAC Thai Limited
- Saravuth Sirinorakul
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor package with partial plating on contact side surfaces
- Patent number 9,773,722
- Issue date Sep 26, 2017
- UTAC HEADQUARTERS PTE. LTD.
- Somchai Nondhasitthichai
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Flip chip cavity package
- Patent number 9,761,435
- Issue date Sep 12, 2017
- UTAC Thai Limited
- Saravuth Sirinorakul
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor package with partial plating on contact side surfaces
- Patent number 9,741,642
- Issue date Aug 22, 2017
- UTAC HEADQUARTERS PTE. LTD.
- Somchai Nondhasitthichai
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Molded leadframe substrate semiconductor package
- Patent number 9,711,343
- Issue date Jul 18, 2017
- UTAC THAI LIMITED
- Somchai Nondhasitthichai
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Singulation method for semiconductor package with plating on side o...
- Patent number 9,349,679
- Issue date May 24, 2016
- UTAC Thai Limited
- Saravuth Sirinorakul
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Molded leadframe substrate semiconductor package
- Patent number 9,196,470
- Issue date Nov 24, 2015
- UTAC Thai Limited
- Somchai Nondhasitthichai
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Molded leadframe substrate semiconductor package
- Patent number 9,099,294
- Issue date Aug 4, 2015
- UTAC Thai Limited
- Somchai Nondhasitthichai
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for forming lead frame land grid array
- Patent number 9,099,317
- Issue date Aug 4, 2015
- UTAC Thai Limited
- Somchai Nondhasitthichai
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Molded leadframe substrate semiconductor package
- Patent number 9,093,486
- Issue date Jul 28, 2015
- UTAC Thai Limited
- Somchai Nondhasitthichai
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Molded leadframe substrate semiconductor package
- Patent number 9,082,607
- Issue date Jul 14, 2015
- UTAC Thai Limited
- Somchai Nondhasitthichai
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Very extremely thin semiconductor package
- Patent number 8,704,381
- Issue date Apr 22, 2014
- UTAC Thai Limited
- Somchai Nondhasitthichai
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Lead frame land grid array with routing connector trace under unit
- Patent number 8,685,794
- Issue date Apr 1, 2014
- UTAC Thai Limited
- Somchai Nondhasitthichai
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Lead frame ball grid array with traces under die
- Patent number 8,652,879
- Issue date Feb 18, 2014
- UTAC Thai Limited
- Somchai Nondhasitthichai
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Very extremely thin semiconductor package
- Patent number 8,575,762
- Issue date Nov 5, 2013
- UTAC Thai Limited
- Somchai Nondhasitthichai
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Lead frame ball grid array with traces under die
- Patent number 8,492,906
- Issue date Jul 23, 2013
- UTAC Thai Limited
- Somchai Nondhasitthichai
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Lead frame land grid array with routing connector trace under unit
- Patent number 8,487,451
- Issue date Jul 16, 2013
- UTAC Thai Limited
- Somchai Nondhasitthichai
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Molded leadframe substrate semiconductor package
- Patent number 8,338,922
- Issue date Dec 25, 2012
- UTAC Thai Limited
- Saravuth Sirinorakul
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of manufacturing semiconductor package containing flip-chip...
- Patent number 8,129,229
- Issue date Mar 6, 2012
- UTAC Thai Limited
- Saravuth Sirinorakul
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Package with heat transfer
- Patent number 8,125,077
- Issue date Feb 28, 2012
- UTAC Thai Limited
- Saravuth Sirinorakul
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method and apparatus for no lead semiconductor package
- Patent number 8,071,426
- Issue date Dec 6, 2011
- UTAC Thai Limited
- Saravuth Sirinorakul
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method and apparatus for no lead semiconductor package
- Patent number 8,063,470
- Issue date Nov 22, 2011
- UTAC Thai Limited
- Saravuth Sirinorakul
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Package with heat transfer
- Patent number 8,013,437
- Issue date Sep 6, 2011
- UTAC Thai Limited
- Saravuth Sirinorakul
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method and apparatus for plating a semiconductor package
- Patent number 7,922,877
- Issue date Apr 12, 2011
- UTAC Thai Limited
- Chalermsak Sumithpibul
- C25 - ELECTROLYTIC OR ELECTROPHORETIC PROCESSES APPARATUS THEREFOR
Information Patent Grant
Molded leadframe substrate semiconductor package
- Patent number 7,790,512
- Issue date Sep 7, 2010
- UTAC Thai Limited
- Saravuth Sirinorakul
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method and apparatus for plating a semiconductor package
- Patent number 7,718,522
- Issue date May 18, 2010
- UTAC Thai Limited
- Chalermsak Sumithpibul
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
SINGULATION METHOD FOR SEMICONDUCTOR PACKAGE WITH PLATING ON SIDE O...
- Publication number 20160240460
- Publication date Aug 18, 2016
- UTAC Thai Limited
- Saravuth Sirinorakul
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
VERY EXTREMELY THIN SEMICONDUCTOR PACKAGE
- Publication number 20140015117
- Publication date Jan 16, 2014
- UTAC Thai Limited
- Somchai Nondhasitthichai
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
LEAD FRAME LAND GRID ARRAY WITH ROUTING CONNECTOR TRACE UNDER UNIT
- Publication number 20130337609
- Publication date Dec 19, 2013
- UTAC Thai Limited
- Somchai Nondhasitthichai
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
LEAD FRAME BALL GRID ARRAY WITH TRACES UNDER DIE
- Publication number 20130280866
- Publication date Oct 24, 2013
- Somchai Nondhasitthichai
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MOLDED LEADFRAME SUBSTRATE SEMICONDUCTOR PACKAGE
- Publication number 20130243893
- Publication date Sep 19, 2013
- UTAC Thai Limited
- Somchai Nondhasitthichai
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
QFN PROCESS FOR STRIP TEST
- Publication number 20120066899
- Publication date Mar 22, 2012
- UTAC Thai Limited
- Saravuth Sirinorakul
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SINGULATION METHOD FOR SEMICONDUCTOR PACKAGE WITH PLATING ON SIDE O...
- Publication number 20120049335
- Publication date Mar 1, 2012
- UTAC Thai Limited
- Saravuth Sirinorakul
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
LEAD FRAME BALL GRID ARRAY WITH TRACES UNDER DIE
- Publication number 20110198752
- Publication date Aug 18, 2011
- UTAC Thai Limited
- Somchai Nondhasitthichai
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
LEAD FRAME LAND GRID ARRAY WITH ROUTING CONNECTOR TRACE UNDER UNIT
- Publication number 20110147931
- Publication date Jun 23, 2011
- UTAC Thai Limited
- Somchai Nondhasitthichai
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MOLDED LEADFRAME SUBSTRATE SEMICONDUCTOR PACKAGE
- Publication number 20110076805
- Publication date Mar 31, 2011
- UTAC Thai Limited
- Somchai Nondhasitthichai
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FLIP CHIP CAVITY PACKAGE
- Publication number 20110039371
- Publication date Feb 17, 2011
- UTAC Thai Limited
- Saravuth Sirinorakul
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PACKAGE WITH HEAT TRANSFER
- Publication number 20100327432
- Publication date Dec 30, 2010
- UTAC THAI LIMITED
- Saravuth Sirinorakul
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD AND APPARATUS FOR NO LEAD SEMICONDUCTOR PACKAGE
- Publication number 20100311208
- Publication date Dec 9, 2010
- UTAC Thai Limited
- Saravuth Sirinorakul
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method and apparatus for plating a semiconductor package
- Publication number 20100140081
- Publication date Jun 10, 2010
- UTAC Thai Limited
- Chalermsak Sumithpibul
- C25 - ELECTROLYTIC OR ELECTROPHORETIC PROCESSES APPARATUS THEREFOR
Information Patent Application
Very extremely thin semiconductor package
- Publication number 20100127363
- Publication date May 27, 2010
- UTAC Thai Limited
- Somchai Nondhasitthichai
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD AND APPARATUS FOR PLATING A SEMICONDUCTOR PACKAGE
- Publication number 20080299756
- Publication date Dec 4, 2008
- UTAC Thai Limited
- Chalermsak Sumithpibul
- C25 - ELECTROLYTIC OR ELECTROPHORETIC PROCESSES APPARATUS THEREFOR
Information Patent Application
Semiconductor package including leadframe roughened with chemical e...
- Publication number 20060097366
- Publication date May 11, 2006
- NS Electronics Bangkok (1993) Ltd.
- Saravuth Sirinorakul
- H01 - BASIC ELECTRIC ELEMENTS

Somchai Nondhasitthichai

Person

Patents Grantslast 30 patents

Semiconductor package with partial plating on contact side surfaces

Semiconductor package with partial plating on contact side surfaces

Flip chip cavity package

Molded leadframe substrate semiconductor package

Singulation method for semiconductor package with plating on side o...

Semiconductor package with partial plating on contact side surfaces

Flip chip cavity package

Semiconductor package with partial plating on contact side surfaces

Molded leadframe substrate semiconductor package

Singulation method for semiconductor package with plating on side o...

Molded leadframe substrate semiconductor package

Molded leadframe substrate semiconductor package

Method for forming lead frame land grid array

Molded leadframe substrate semiconductor package

Molded leadframe substrate semiconductor package

Very extremely thin semiconductor package

Lead frame land grid array with routing connector trace under unit

Lead frame ball grid array with traces under die

Very extremely thin semiconductor package

Lead frame ball grid array with traces under die

Lead frame land grid array with routing connector trace under unit

Molded leadframe substrate semiconductor package

Method of manufacturing semiconductor package containing flip-chip...

Package with heat transfer

Method and apparatus for no lead semiconductor package

Method and apparatus for no lead semiconductor package

Package with heat transfer

Method and apparatus for plating a semiconductor package

Molded leadframe substrate semiconductor package

Method and apparatus for plating a semiconductor package

Patents Applicationslast 30 patents

SINGULATION METHOD FOR SEMICONDUCTOR PACKAGE WITH PLATING ON SIDE O...

VERY EXTREMELY THIN SEMICONDUCTOR PACKAGE

LEAD FRAME LAND GRID ARRAY WITH ROUTING CONNECTOR TRACE UNDER UNIT

LEAD FRAME BALL GRID ARRAY WITH TRACES UNDER DIE

MOLDED LEADFRAME SUBSTRATE SEMICONDUCTOR PACKAGE

QFN PROCESS FOR STRIP TEST

SINGULATION METHOD FOR SEMICONDUCTOR PACKAGE WITH PLATING ON SIDE O...

LEAD FRAME BALL GRID ARRAY WITH TRACES UNDER DIE

LEAD FRAME LAND GRID ARRAY WITH ROUTING CONNECTOR TRACE UNDER UNIT

MOLDED LEADFRAME SUBSTRATE SEMICONDUCTOR PACKAGE

FLIP CHIP CAVITY PACKAGE

PACKAGE WITH HEAT TRANSFER

METHOD AND APPARATUS FOR NO LEAD SEMICONDUCTOR PACKAGE

Method and apparatus for plating a semiconductor package

Very extremely thin semiconductor package

METHOD AND APPARATUS FOR PLATING A SEMICONDUCTOR PACKAGE

Semiconductor package including leadframe roughened with chemical e...