The present invention is in the field of semiconductor packaging and is more specifically directed to a flip chip cavity package.
The increasing demand for computer performance has led to higher chip internal clock frequencies and parallelism, and has increased the need for higher bandwidth and lower latencies. Processor frequencies are predicted to reach 29 GHz by 2018, and off-chip signaling interface speeds are expected to exceed 56 Gb/s. Optimization of bandwidth, power, pin count, or number of wires and cost are the goals for high-speed interconnect design. The electrical performance of interconnects is restricted by noise and timing limitations of the silicon, package, board and cable. To that end, semiconductor packages must be made smaller, conforming more and more closely to the size of the die encapsulated within. However, as the size of the package shrinks to the size of the die itself, the size of the package becomes insufficient to support the number of leads generally required by current applications.
Chip Scale Packages (CSP) have emerged as the dominant package for such applications.
To overcome the issues mentioned above, the semiconductor industry has moved toward Ball Grid Array (BGA) packages. The BGA is descended from the pin grid array (PGA), which is a package with one face covered (or partly covered) with pins in a grid pattern. These pins are used to conduct electrical signals from the integrated circuit (IC) to the printed circuit board (PCB) it is placed on. In a BGA, the pins are replaced by balls of solder formed on the bottom of the package. The device is placed on a PCB that carries copper pads in a pattern that matches the solder balls. The assembly is then heated, such as in a reflow oven or by an infrared heater, causing the solder balls to melt. Surface tension causes the molten solder to hold the package in alignment with the circuit board at the correct separation distance while the solder cools and solidifies. The BGA is a solution to the problem of producing a miniature package for an IC with many hundreds of I/O. As pin grid arrays and dual-in-line (DIP) surface mount (SOIC) packages are produced with more and more pins, and with decreasing spacing between the pins, difficulties arose in the soldering process. As package pins got closer together, the danger of accidentally bridging adjacent pins with solder grew. BGAs do not have this problem, because the solder is factory-applied to the package in exactly the right amount. Alternatively, solder balls can be replaced by solder landing pads, forming a Land Grid Array (LGA) package.
One aspect of the invention is a process for forming a semiconductor package. The process includes forming a first leadframe strip mounted upon an adhesive tape. The first leadframe strip is at least partially encased in a first mold compound thereby forming a molded leadframe strip. At least one flip chip semiconductor device is mounted on the molded leadframe strip in a face to face manner to allow electrical interconnection between each flip chip semiconductor device and its corresponding leadframe. Each flip chip semiconductor device has conductive masses attached thereon to effectuate electrical contact between the at least one flip chip semiconductor device and the corresponding molded leadframe. Preferably, the conductive masses are formed of solder. In one embodiment, the conductive masses are substantially spherical. In another embodiment, the conductive masses are substantially cylindrical. Liquid encapsulant is dispensed on each flip chip semiconductor device to encapsulate the flip chip semiconductor device. A cavity is formed between each flip chip semiconductor device and its molded leadframe. The molded leadframe strip, the at least one flip chip semiconductor device, and the conductive masses are at least partially encased in a second mold compound. In one embodiment, the second mold compound is molded so that a surface of the flip chip semiconductor device that is not attached to the molded leadframe is substantially exposed. In another embodiment, the second mold compound is dispensed to produce a globular form on the at least one flip chip semiconductor device to form the cavity between the at least one flip chip semiconductor device and the at least one molded leadframe. The molded leadframe strip is singulated to form discrete semiconductor packages.
In some embodiments, a second leadframe strip is coupled to the first leadframe strip to form a dual leadframe strip. The first leadframe strip and the second leadframe strip are able to be coupled by a soft metal which is formed of at least one of the following materials: gold, silver, lead, and tin. The first and second mold compounds can be identical or differing materials.
Another aspect of the invention is an apparatus for forming a semiconductor package. The apparatus includes a means for forming a first leadframe strip mounted upon an adhesive tape. Means is provided for at least partially encasing the first leadframe strip in a first mold compound thereby forming a molded leadframe strip. Means is provided for mounting at least one flip chip semiconductor device on the molded leadframe strip so that each flip chip semiconductor device having conductive masses attached thereon to effectuate electrical contact between each flip chip semiconductor device and the corresponding molded leadframe. Preferably, the conductive masses are formed of solder. In one embodiment, the conductive masses are substantially spherical. In another embodiment, the conductive masses are substantially cylindrical. Means is provided for dispensing liquid encapsulant on each flip chip semiconductor device to encapsulate the flip chip semiconductor device. A cavity is formed between each flip chip semiconductor device and its molded leadframe. Means is provided for at least partially encasing the molded leadframe strip, each flip chip semiconductor device, and the conductive masses in a second mold compound. In one embodiment, the second mold compound is molded so that a surface of the flip chip semiconductor device that is not attached to the molded leadframe is substantially exposed. In another embodiment, the second mold compound is dispensed to produce a globular form on the at least one flip chip semiconductor device to form the cavity between each flip chip semiconductor device and its molded leadframe. Means is provided for singulating the molded leadframe strip to faint discrete flip chip semiconductor packages.
In some embodiments, the apparatus includes a means to couple the first leadframe to a second leadframe by a soft metal. The soft metal is formed of at least one of the following materials: gold, silver, lead, and tin. The first and second mold compounds can be identical or differing materials.
Another aspect of the invention is a semiconductor package. The package includes a first leadframe so that the first leadframe is formed with a half etch technique. A substrate supports the first leadframe. The substrate includes a first mold compound. At least one flip chip semiconductor die is mounted on the first leadframe. A plurality of conductive masses effectuate electrical contact between the first leadframe and the corresponding flip chip semiconductor die. Preferably, the conductive masses are formed of solder. In one embodiment, the conductive masses are substantially spherical. In another embodiment, the conductive masses are substantially cylindrical. A second mold compound at least partially encases the first leadframe, each flip chip semiconductor die, and the plurality of conductive masses. In one embodiment, the second mold compound is molded so that a surface of the flip chip semiconductor device that is not attached to the molded leadframe is substantially exposed. In another embodiment, the second mold compound is molded to produce a globular form on each flip chip semiconductor device to form the cavity between each flip chip semiconductor device and its molded leadframe.
Optionally the semiconductor package includes a second leadframe coupled to the first leadframe by a soft metal. The soft metal is formed of at least one of the following materials: gold, silver, lead and tin.
The novel features of the invention are set forth in the appended claims. However, for purpose of explanation, several embodiments of the invention are set forth in the following figures.
In the following description, numerous details and alternatives are set forth for purpose of explanation. However, one of ordinary skill in the art will realize that the invention can be practiced without the use of these specific details. In other instances, well-known structures and devices are shown in block diagram form in order not to obscure the description of the invention with unnecessary detail. For example, it is commonly known in the art of semiconductor device assembly that assembly is generally done on a matrix array of leadframes, often referred to as leadframe strips. Each strip has a plurality of individual positions that will all be processed in the same way through various steps to form individual packaged semiconductor devices. A position can have one or more semiconductor die within.
Additional information on leadframe strips as described in the present invention can be found in the related U.S. patent application Ser. No. 11/788,496 filed Mar. 19, 2007, entitled “MOLDED LEADFRAME SUBSTRATE SEMICONDUCTOR PACKAGE,” the entirety of which is hereby incorporated by reference.
In a first aspect of the invention, a process 300 of forming semiconductor packages is detailed in
For more predictable molding results, carrier tape can be used to effectuate the molding process as shown in
In some applications, it is advantageous to allow for greater height clearance within the semiconductor package for example to accept thicker semiconductor devices.
An alternative surface is shown in
At the step 730, the flip chip semiconductor devices 706 are affixed onto the molded leadframe strip onto each individual position. In some embodiments, multiple devices 706 can be placed in each position as applications require. The flip chip devices 706 include conductive spheres 707 such as a solder ball affixed to effectuate electrical contact between the molded leadframe strip 705 and the devices 706. Alternatively, conductive cylinders (not shown) can be used instead of the conductive spheres 707. At the step 740, a liquid encapsulant 708 is dispensed to form a cavity 711 between the flip chip semiconductor devices 706 and the molded leadframe strip 705. Alternatively, a silicon coating can be used as the encapsulant 708 to form the cavity 711 between the flip chip semiconductor devices 706 and the molded leadframe strip 705. At the step 750, the molded leadframe strip 705, flip chip semiconductor devices 706 and conductive spheres 707 are encased in a second mold compound 712. The second mold compound 712 and the first mold compound 703 can be identical mold compounds or different mold compounds as applications require. The second mold compound 712 is preferably marked to facilitate alignment of a later singulation step. The adhesive tape 702 is removed. A post-mold plating process as practiced by a person of ordinary skill in the art can be performed on the molded leadframe 705. The post-mold plating process can be skipped if a pre-plated leadframe (PPF) is utilized for the leadframe strip 701.
At the step 760, the double molded leadframe strip 705 is singulated by saw blades 714. At the step 770, the singulated double molded leadframe strip 705 forms individual flip chip cavity packages 790. These individual devices can then be tested, marked and bulk packaged for shipping and assembly. It will be apparent to those of ordinary skill in the art of semiconductor device assembly that although few leads 718 are shown, a few to hundreds of leads are able to be realized using the process described herein. Flexibility in routing I/O is advantageous, since end users can have specific demands as to the locations of I/O on a package landing pattern. To that end, a second leadframe (not shown) can be used. The second leadframe can couple to the first leadframe by use of a soft metal. The soft metal can include the materials of gold, silver, lead and tin. The second leadframe can be used to route the I/O to any pattern required by an application, allowing great flexibility in footprints and landing patterns.
In another aspect of the invention,
At the step 830, the flip chip semiconductor devices 806 are affixed onto the molded leadframe strip onto each individual position. In some embodiments, multiple devices 806 can be placed in each position as applications require. The flip chip devices 806 include conductive spheres 807 such as a solder ball affixed to effectuate electrical contact between the molded leadframe strip 805 and the devices 806. Alternatively, conductive cylinders (not shown) can be used instead of the conductive spheres 807. At the step 840, a liquid encapsulant 808 is dispensed to form a cavity 811 between the flip chip semiconductor devices 806 and the molded leadframe strip 805. Alternatively, a silicon coating can be used as the encapsulant 808 to form the cavity 811 between the flip chip semiconductor devices 806 and the molded leadframe strip 805. At the step 850, the molded leadframe strip 805, flip chip semiconductor devices 806 and conductive spheres 807 are encased in a second mold compound 812. The second mold compound 812 is molded such that a top surface 809 of the flip chip semiconductor devices 806 are exposed. The second mold compound 812 and the first mold compound 803 can be identical mold compounds or different mold compounds as applications require. The second mold compound 812 is preferably marked to facilitate alignment of a later singulation step. The adhesive tape 802 is removed. A post-mold plating process as practiced by a person of ordinary skill in the art can be performed on the molded leadframe 805. The post-mold plating process can be skipped if a pre-plated leadframe (PPF) is utilized for the leadframe strip 801.
At the step 860, the double molded leadframe strip 805 is singulated by saw blades 814. At the step 870, the singulated double molded leadframe strip 805 forms individual flip chip cavity packages 890. These individual devices can then be tested, marked and bulk packaged for shipping and assembly. It will be apparent to those of ordinary skill in the art of semiconductor device assembly that although few leads 818 are shown, a few to hundreds of leads are able to be realized using the process described herein. Flexibility in routing I/O is advantageous, since end users can have specific demands as to the locations of I/O on a package landing pattern. To that end, a second leadframe (not shown) can be used. The second leadframe can couple to the first leadframe by use of a soft metal. The soft metal can include the materials of gold, silver, lead and tin. The second leadframe can be used to route the I/O to any pattern required by an application, allowing great flexibility in footprints and landing patterns.
In another aspect of the invention,
At the step 930, the flip chip semiconductor devices 906 are affixed onto the molded leadframe strip onto each individual position. In some embodiments, multiple devices 906 can be placed in each position as applications require. The flip chip devices 906 include conductive spheres 907 such as a solder ball affixed to effectuate electrical contact between the molded leadframe strip 905 and the devices 906. Alternatively, conductive cylinders (not shown) can be used instead of the conductive spheres 907. At the step 940, a liquid encapsulant 908 is dispensed to form a cavity 911 between the flip chip semiconductor devices 906 and the molded leadframe strip 905. Alternatively, a silicon coating can be used as the encapsulant 908 to form the cavity 911 between the flip chip semiconductor devices 906 and the molded leadframe strip 905. The molded leadframe strip 905, flip chip semiconductor devices 906 and conductive spheres 907 are encased in a second mold compound or globular form 912. The second mold compound 912 is dispensed and molded to produce the globular form 912 encasing the molded leadframe strip 905, flip chip semiconductor devices 906 and conductive spheres 907. The second mold compound 912 and the first mold compound 903 can be identical mold compounds or different mold compounds as applications require. At the step 950, the second mold compound 912 and the molded leadframe strip 905 are preferably marked to facilitate alignment of a later singulation step. The adhesive tape 902 is removed. A post-mold plating process as practiced by a person of ordinary skill in the art can be performed on the molded leadframe 905. The post-mold plating process can be skipped if a pre-plated leadframe (PPF) is utilized for the leadframe strip 901.
At the step 960, the double molded leadframe strip 905 is singulated by saw blades 914. At the step 970, the singulated double molded leadframe strip 905 forms individual flip chip cavity packages 990. These individual devices can then be tested, marked and bulk packaged for shipping and assembly. It will be apparent to those of ordinary skill in the art of semiconductor device assembly that although few leads 918 are shown, a few to hundreds of leads are able to be realized using the process described herein. Flexibility in routing I/O is advantageous, since end users can have specific demands as to the locations of I/O on a package landing pattern. To that end, a second leadframe (not shown) can be used. The second leadframe can couple to the first leadframe by use of a soft metal. The soft metal can include the materials of gold, silver, lead and tin. The second leadframe can be used to route the I/O to any pattern required by an application, allowing great flexibility in footprints and landing patterns.
While the invention has been described with reference to numerous specific details, one of ordinary skill in the art will recognize that the invention can be embodied in other specific forms without departing from the spirit of the invention. Thus, one of ordinary skill in the art will understand that the invention is not to be limited by the foregoing illustrative details, but rather is to be defined by the appended claims.
This application is a Divisional Application of the co-pending application Ser. No. 12/231,710, filed Sep. 4, 2008 and titled FLIP CHIP CAVITY PACKAGE,” hereby incorporated in its entirety. This application is a Continuation-in-part of the co-pending application Ser. No. 12/002,186, filed Dec. 14, 2007, and titled “CAVITY MOLDED LEADFRAME AND METHOD OF MANUFACTURING THE SAME”, application Ser. No. 12/002,054, filed Dec. 14, 2007, and titled “MOLDED LEADFRAME AND METHOD OF MANUFACTURING THE SAME” and application Ser. No. 12/002,187, filed Dec. 14, 2007, and titled “HALF ETCH PADDLE MOLDED LEADFRAME AND METHOD OF MANUFACTURING THE SAME”, all of which claim priority under 35 U.S.C. section 119(e) to the U.S. Provisional Application Ser. No. 60/875,162, filed Dec. 14, 2006, and titled “MOLDED-LEADFRAME SUBSTRATE SEMICONDUCTOR PACKAGE,” and the U.S. Provisional Application Ser. No. 60/877,274, filed Dec. 26, 2006, and titled “MOLDED-LEADFRAME SUBSTRATE SEMICONDUCTOR PACKAGE,” all of which are hereby incorporated by reference in their entirety.
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Number | Date | Country | |
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20110039371 A1 | Feb 2011 | US |
Number | Date | Country | |
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Parent | 12231710 | Sep 2008 | US |
Child | 12914694 | US |