Somnath Nag

Person

Saratoga, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Formation of a layer on a semiconductor substrate
- Patent number 10,096,473
- Issue date Oct 9, 2018
- Aixtron SE
- Maxim Kelman
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
High-productivity porous semiconductor manufacturing equipment
- Patent number 9,869,031
- Issue date Jan 16, 2018
- OB Realty, LLC.
- George D. Kamian
- C25 - ELECTROLYTIC OR ELECTROPHORETIC PROCESSES APPARATUS THEREFOR
Information Patent Grant
Method of fabricating a metal wrap through solar cell
- Patent number 9,455,360
- Issue date Sep 27, 2016
- Crystal Solar, Inc.
- Ashish Asthana
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Apparatus for forming porous silicon layers on at least two surface...
- Patent number 9,401,276
- Issue date Jul 26, 2016
- Solexel, Inc.
- Mehrdad M. Moslehi
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Methods for selectively coating three-dimensional features on a sub...
- Patent number 9,093,323
- Issue date Jul 28, 2015
- Solexel, Inc.
- David Xuan-Qi Wang
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Structure and method for creating a reusable template for detachabl...
- Patent number 9,053,957
- Issue date Jun 9, 2015
- Solexel, Inc.
- Suketu Parikh
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
High-productivity porous semiconductor manufacturing equipment
- Patent number 8,999,058
- Issue date Apr 7, 2015
- Solexel, Inc.
- George D. Kamian
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Porous silicon electro-etching system and method
- Patent number 8,926,803
- Issue date Jan 6, 2015
- Solexel, Inc.
- Doug Crafts
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
MWT architecture for thin SI solar cells
- Patent number 8,883,552
- Issue date Nov 11, 2014
- Crystal Solar Inc.
- Ashish Asthana
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Methods for liquid transfer coating of three-dimensional substrates
- Patent number 8,512,581
- Issue date Aug 20, 2013
- Solexel, Inc.
- David Xuan-Qi Wang
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Method of creating reusable template for detachable thin film subst...
- Patent number 8,445,314
- Issue date May 21, 2013
- Solexel, Inc.
- Suketu Parikh
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Double-sided reusable template for fabrication of semiconductor sub...
- Patent number 8,241,940
- Issue date Aug 14, 2012
- Solexel, Inc.
- Mehrdad M. Moslehi
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
High efficiency solar cells and manufacturing methods
- Patent number 7,786,376
- Issue date Aug 31, 2010
- Solexel, Inc.
- Somnath Nag
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Process sequence for doped silicon fill of deep trenches
- Patent number 7,713,881
- Issue date May 11, 2010
- Applied Materials, Inc.
- Ajit Paranjpe
- C23 - COATING METALLIC MATERIAL COATING MATERIAL WITH METALLIC MATERIAL CHEMI...
Information Patent Grant
Process sequence for doped silicon fill of deep trenches
- Patent number 7,446,366
- Issue date Nov 4, 2008
- Applied Materials, Inc.
- Ajit Paranjpe
- C23 - COATING METALLIC MATERIAL COATING MATERIAL WITH METALLIC MATERIAL CHEMI...
Information Patent Grant
Process sequence for doped silicon fill of deep trenches
- Patent number 7,109,097
- Issue date Sep 19, 2006
- Applied Materials, Inc.
- Ajit Paranjpe
- C23 - COATING METALLIC MATERIAL COATING MATERIAL WITH METALLIC MATERIAL CHEMI...
Information Patent Grant
Integrated circuit insulator and method
- Patent number 6,962,883
- Issue date Nov 8, 2005
- Texas Instruments Incorporated
- Somnath S. Nag
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Systems and methods to retard copper diffusion and improve film adh...
- Patent number 6,764,952
- Issue date Jul 20, 2004
- Novellus Systems, Inc.
- Jengyi Yu
- C23 - COATING METALLIC MATERIAL COATING MATERIAL WITH METALLIC MATERIAL CHEMI...
Information Patent Grant
Integration of fluorinated dielectrics in multi-level metallizations
- Patent number 6,424,040
- Issue date Jul 23, 2002
- Texas Instruments Incorporated
- Somnath S. Nag
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Low dielectric constant etch stop films
- Patent number 6,417,092
- Issue date Jul 9, 2002
- Novellus Systems, Inc.
- Sanjeev Jain
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit insulator and method
- Patent number 6,313,010
- Issue date Nov 6, 2001
- Texas Instruments Incorporated
- Somnath S. Nag
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
In-situ liner for isolation trench side walls and method
- Patent number 6,306,725
- Issue date Oct 23, 2001
- Texas Instruments Incorporated
- Somnath S. Nag
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Air-bridge integration scheme for reducing interconnect delay
- Patent number 6,297,125
- Issue date Oct 2, 2001
- Texas Instruments Incorporated
- Somnath S. Nag
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Self-planarizing low-temperature doped-silicate-glass process capab...
- Patent number 6,268,297
- Issue date Jul 31, 2001
- Texas Instruments Incorporated
- Somnath S. Nag
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of implementing air-gap technology for low capacitance ILD i...
- Patent number 6,214,719
- Issue date Apr 10, 2001
- Novellus Systems, Inc.
- Somnath Nag
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Process scheme to form controlled airgaps between interconnect line...
- Patent number 6,204,200
- Issue date Mar 20, 2001
- Texas Instruments Incorporated
- Benjamin P. Shieh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Protective liner for isolation trench side walls and method
- Patent number 6,143,625
- Issue date Nov 7, 2000
- Texas Instruments Incorporated
- Ih-Chin Chen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Interlevel dielectrics with reduced dielectric constant
- Patent number 6,127,285
- Issue date Oct 3, 2000
- Dallas Instruments Incorporated
- Somnath S. Nag
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Reducing non-uniformity in a refill layer thickness for a semicondu...
- Patent number 5,909,628
- Issue date Jun 1, 1999
- Texas Instruments Incorporated
- Amitava Chatterjee
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
FORMATION OF A LAYER ON A SEMICONDUCTOR SUBSTRATE
- Publication number 20170294306
- Publication date Oct 12, 2017
- AIXTRON SE
- Maxim Kelman
- C23 - COATING METALLIC MATERIAL COATING MATERIAL WITH METALLIC MATERIAL CHEMI...
Information Patent Application
PHOTOVOLTAIC MODULE FABRICATION WITH THIN SINGLE CRYSTAL EPITAXIAL...
- Publication number 20170141720
- Publication date May 18, 2017
- Crystal Solar, Incorporated
- Kramadhati V. Ravi
- H02 - GENERATION CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
Information Patent Application
PHOTOVOLTAIC MODULE FABRICATION WITH THIN SINGLE CRYSTAL EPITAXIAL...
- Publication number 20160233824
- Publication date Aug 11, 2016
- Crystal Solar, Incorporated
- Kramadhati V. Ravi
- H02 - GENERATION CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
Information Patent Application
HIGH-PRODUCTIVITY POROUS SEMICONDUCTOR MANUFACTURING EQUIPMENT
- Publication number 20150315719
- Publication date Nov 5, 2015
- SOLEXEL, INC.
- George D. Kamian
- C25 - ELECTROLYTIC OR ELECTROPHORETIC PROCESSES APPARATUS THEREFOR
Information Patent Application
REMOTE ACCESS, CONTROL, AND MANAGEMENT OF A POWER MICRO GRID
- Publication number 20150311721
- Publication date Oct 29, 2015
- NUEVO POWER, INC.
- Sanjay UPPAL
- H02 - GENERATION CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
Information Patent Application
POROUS SILICON ELECTRO-ETCHING SYSTEM AND METHOD
- Publication number 20150299892
- Publication date Oct 22, 2015
- SOLEXEL, INC.
- Mehrdad M. Moslehi
- C25 - ELECTROLYTIC OR ELECTROPHORETIC PROCESSES APPARATUS THEREFOR
Information Patent Application
MWT ARCHITECTURE FOR THIN SI SOLAR CELLS
- Publication number 20150187966
- Publication date Jul 2, 2015
- Crystal Solar, Inc.
- Ashish Asthana
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHODS FOR LIQUID TRANSER COATING OF THREE-DIMENSIONAL SUBSTRATES
- Publication number 20140127834
- Publication date May 8, 2014
- SOLEXEL, INC.
- David Xuan-Qi Wang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
STRUCTURE AND METHOD FOR CREATING A REUSABLE TEMPLATE FOR DETACHABL...
- Publication number 20130241038
- Publication date Sep 19, 2013
- SOLEXEL, INC.
- Suketu Parikh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DOUBLE-SIDED REUSABLE TEMPLATE FOR FABRICATION OF SEMICONDUCTOR SUB...
- Publication number 20130171808
- Publication date Jul 4, 2013
- SOLEXEL, INC.
- Mehrdad M. Moslehi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PHOTOVOLTAIC MODULE FABRICATION WITH THIN SINGLE CRYSTAL EPITAXIAL...
- Publication number 20130056044
- Publication date Mar 7, 2013
- Crystal Solar, Inc.
- Kramadhati V. Ravi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MWT ARCHITECTURE FOR THIN SI SOLAR CELLS
- Publication number 20120040487
- Publication date Feb 16, 2012
- Crystal Solar, Inc.
- Ashish Asthana
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Application
DOUBLE-SIDED REUSABLE TEMPLATE FOR FABRICATION OF SEMICONDUCTOR SUB...
- Publication number 20110256654
- Publication date Oct 20, 2011
- SOLEXEL, INC.
- Mehrdad M. Moslehi
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Application
POROUS SILICON ELECTRO-ETCHING SYSTEM AND METHOD
- Publication number 20110120882
- Publication date May 26, 2011
- SOLEXEL, INC.
- Doug Crafts
- C25 - ELECTROLYTIC OR ELECTROPHORETIC PROCESSES APPARATUS THEREFOR
Information Patent Application
HIGH-PRODUCTIVITY POROUS SEMICONDUCTOR MANUFACTURING EQUIPMENT
- Publication number 20110030610
- Publication date Feb 10, 2011
- SOLEXEL, INC.
- George D. Kamian
- C25 - ELECTROLYTIC OR ELECTROPHORETIC PROCESSES APPARATUS THEREFOR
Information Patent Application
METHOD OF CREATING REUSABLE TEMPLATE FOR DETACHABLE THIN FILM SUBST...
- Publication number 20110014742
- Publication date Jan 20, 2011
- SOLEXEL, INC.
- Suketu Parikh
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Application
Shadow Mask Methods For Manufacturing Three-Dimensional Thin-Film S...
- Publication number 20100304521
- Publication date Dec 2, 2010
- SOLEXEL, INC.
- Sean Michael Seutter
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Application
METHODS FOR LIQUID TRANSFER COATING OF THREE-DIMENSIONAL SUBSTRATES
- Publication number 20090042320
- Publication date Feb 12, 2009
- SOLEXEL, INC.
- David Xuan-Qi Wang
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Application
PROCESS SEQUENCE FOR DOPED SILICON FILL OF DEEP TRENCHES
- Publication number 20080318441
- Publication date Dec 25, 2008
- Applied Materials, Inc.
- Ajit Paranjpe
- C23 - COATING METALLIC MATERIAL COATING MATERIAL WITH METALLIC MATERIAL CHEMI...
Information Patent Application
High Efficiency Solar Cells and Manufacturing Methods
- Publication number 20080047601
- Publication date Feb 28, 2008
- Somnath Nag
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Application
Determining Information about Defects or Binning Defects Detected o...
- Publication number 20070280526
- Publication date Dec 6, 2007
- Irfan Malik
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PROCESS SEQUENCE FOR DOPED SILICON FILL OF DEEP TRENCHES
- Publication number 20060234470
- Publication date Oct 19, 2006
- Ajit Paranjpe
- C23 - COATING METALLIC MATERIAL COATING MATERIAL WITH METALLIC MATERIAL CHEMI...
Information Patent Application
Process sequence for doped silicon fill of deep trenches
- Publication number 20060128139
- Publication date Jun 15, 2006
- APPLIED MATERIALS, INC.
- Ajit Paranjpe
- C23 - COATING METALLIC MATERIAL COATING MATERIAL WITH METALLIC MATERIAL CHEMI...
Information Patent Application
Low temperature sin deposition methods
- Publication number 20060084283
- Publication date Apr 20, 2006
- Ajit P. Paranjpe
- C23 - COATING METALLIC MATERIAL COATING MATERIAL WITH METALLIC MATERIAL CHEMI...
Information Patent Application
Substrate carrier for parallel wafer processing reactor
- Publication number 20050188923
- Publication date Sep 1, 2005
- Robert C. Cook
- C23 - COATING METALLIC MATERIAL COATING MATERIAL WITH METALLIC MATERIAL CHEMI...
Information Patent Application
Integrated circuit insulator and method
- Publication number 20040259384
- Publication date Dec 23, 2004
- Somnath S. Nag
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Low dielectric constant etch stop films
- Publication number 20030036280
- Publication date Feb 20, 2003
- Novellus System, Inc.
- Sanjeev Jain
- H01 - BASIC ELECTRIC ELEMENTS

Somnath Nag

Person

Patents Grantslast 30 patents

Formation of a layer on a semiconductor substrate

High-productivity porous semiconductor manufacturing equipment

Method of fabricating a metal wrap through solar cell

Apparatus for forming porous silicon layers on at least two surface...

Methods for selectively coating three-dimensional features on a sub...

Structure and method for creating a reusable template for detachabl...

High-productivity porous semiconductor manufacturing equipment

Porous silicon electro-etching system and method

MWT architecture for thin SI solar cells

Methods for liquid transfer coating of three-dimensional substrates

Method of creating reusable template for detachable thin film subst...

Double-sided reusable template for fabrication of semiconductor sub...

High efficiency solar cells and manufacturing methods

Process sequence for doped silicon fill of deep trenches

Process sequence for doped silicon fill of deep trenches

Process sequence for doped silicon fill of deep trenches

Integrated circuit insulator and method

Systems and methods to retard copper diffusion and improve film adh...

Integration of fluorinated dielectrics in multi-level metallizations

Low dielectric constant etch stop films

Integrated circuit insulator and method

In-situ liner for isolation trench side walls and method

Air-bridge integration scheme for reducing interconnect delay

Self-planarizing low-temperature doped-silicate-glass process capab...

Method of implementing air-gap technology for low capacitance ILD i...

Process scheme to form controlled airgaps between interconnect line...

Protective liner for isolation trench side walls and method

Interlevel dielectrics with reduced dielectric constant

Reducing non-uniformity in a refill layer thickness for a semicondu...

Patents Applicationslast 30 patents

FORMATION OF A LAYER ON A SEMICONDUCTOR SUBSTRATE

PHOTOVOLTAIC MODULE FABRICATION WITH THIN SINGLE CRYSTAL EPITAXIAL...

PHOTOVOLTAIC MODULE FABRICATION WITH THIN SINGLE CRYSTAL EPITAXIAL...

HIGH-PRODUCTIVITY POROUS SEMICONDUCTOR MANUFACTURING EQUIPMENT

REMOTE ACCESS, CONTROL, AND MANAGEMENT OF A POWER MICRO GRID

POROUS SILICON ELECTRO-ETCHING SYSTEM AND METHOD

MWT ARCHITECTURE FOR THIN SI SOLAR CELLS

METHODS FOR LIQUID TRANSER COATING OF THREE-DIMENSIONAL SUBSTRATES

STRUCTURE AND METHOD FOR CREATING A REUSABLE TEMPLATE FOR DETACHABL...

DOUBLE-SIDED REUSABLE TEMPLATE FOR FABRICATION OF SEMICONDUCTOR SUB...

PHOTOVOLTAIC MODULE FABRICATION WITH THIN SINGLE CRYSTAL EPITAXIAL...

MWT ARCHITECTURE FOR THIN SI SOLAR CELLS

DOUBLE-SIDED REUSABLE TEMPLATE FOR FABRICATION OF SEMICONDUCTOR SUB...

POROUS SILICON ELECTRO-ETCHING SYSTEM AND METHOD

HIGH-PRODUCTIVITY POROUS SEMICONDUCTOR MANUFACTURING EQUIPMENT

METHOD OF CREATING REUSABLE TEMPLATE FOR DETACHABLE THIN FILM SUBST...

Shadow Mask Methods For Manufacturing Three-Dimensional Thin-Film S...

METHODS FOR LIQUID TRANSFER COATING OF THREE-DIMENSIONAL SUBSTRATES

PROCESS SEQUENCE FOR DOPED SILICON FILL OF DEEP TRENCHES

High Efficiency Solar Cells and Manufacturing Methods

Determining Information about Defects or Binning Defects Detected o...

PROCESS SEQUENCE FOR DOPED SILICON FILL OF DEEP TRENCHES

Process sequence for doped silicon fill of deep trenches

Low temperature sin deposition methods

Substrate carrier for parallel wafer processing reactor

Integrated circuit insulator and method

Low dielectric constant etch stop films