YUKIHITO OOWAKI

Person

TOKYO, JP

People

Patents Grantslast 30 patents

Information Patent Grant
Semiconductor device and method of designing a wiring of a semicond...
- Patent number 8,269,346
- Issue date Sep 18, 2012
- Kabushiki Kaisha Toshiba
- Shoji Seta
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device and system
- Patent number 7,487,370
- Issue date Feb 3, 2009
- Kabushiki Kaisha Toshiba
- Shinichiro Shiratake
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
MIS transistor and method for producing same
- Patent number 7,303,965
- Issue date Dec 4, 2007
- Kabushiki Kaisha Toshiba
- Yukihito Oowaki
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Chain ferroelectric random access memory (CFRAM) having an intrinsi...
- Patent number 7,295,456
- Issue date Nov 13, 2007
- Kabushiki Kaisha Toshiba
- Ryu Ogiwara
- G11 - INFORMATION STORAGE
Information Patent Grant
Semiconductor device adapted to minimize clock skew
- Patent number 7,236,035
- Issue date Jun 26, 2007
- Kabushiki Kaisha Toshiba
- Shinichiro Shiratake
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Ferroelectric memory with an intrinsic access transistor coupled to...
- Patent number 7,057,917
- Issue date Jun 6, 2006
- Kabushiki Kaisha Toshiba
- Ryu Ogiwara
- G11 - INFORMATION STORAGE
Information Patent Grant
Series connected TC unit type ferroelectric RAM and test method the...
- Patent number 6,993,691
- Issue date Jan 31, 2006
- Kabushiki Kaisha Toshiba
- Ryu Ogiwara
- G11 - INFORMATION STORAGE
Information Patent Grant
Ferroelectric memory
- Patent number 6,906,944
- Issue date Jun 14, 2005
- Kabushiki Kaisha Toshiba
- Yoshiaki Takeuchi
- G11 - INFORMATION STORAGE
Information Patent Grant
MIS transistor having a large driving current and method for produc...
- Patent number 6,690,047
- Issue date Feb 10, 2004
- Kabushiki Kaisha Toshiba
- Yukihito Oowaki
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Ferroelectric random access memory with isolation transistors coupl...
- Patent number 6,671,200
- Issue date Dec 30, 2003
- Kabushiki Kaisha Toshiba
- Ryu Ogiwara
- G11 - INFORMATION STORAGE
Information Patent Grant
Ferroelectric memory having a device responsive to current lowering
- Patent number 6,643,162
- Issue date Nov 4, 2003
- Kabushiki Kaisha Toshiba
- Yoshiaki Takeuchi
- G11 - INFORMATION STORAGE
Information Patent Grant
Ferroelectric random access memory
- Patent number 6,611,450
- Issue date Aug 26, 2003
- Kabushiki Kaisha Toshiba
- Yukihito Oowaki
- G11 - INFORMATION STORAGE
Information Patent Grant
Chain-type ferroelectric random access memory (FRAM) with rewrite t...
- Patent number 6,552,922
- Issue date Apr 22, 2003
- Kabushiki Kaisha Toshiba
- Ryu Ogiwara
- G11 - INFORMATION STORAGE
Information Patent Grant
Semiconductor memory device including a pair of MOS transistors for...
- Patent number 6,545,323
- Issue date Apr 8, 2003
- Kabushiki Kaisha Toshiba
- Yukihito Oowaki
- G11 - INFORMATION STORAGE
Information Patent Grant
Random access memory with divided memory banks and data read/write...
- Patent number 6,538,952
- Issue date Mar 25, 2003
- Kabushiki Kaisha Toshiba
- Yukihito Oowaki
- G11 - INFORMATION STORAGE
Information Patent Grant
Semiconductor apparatus and mode setting method for semiconductor a...
- Patent number 6,522,589
- Issue date Feb 18, 2003
- Kabushiki Kaisha Toshiba
- Tadashi Miyakawa
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor memory device
- Patent number 6,522,569
- Issue date Feb 18, 2003
- Kabushiki Kaisha Toshiba
- Tadashi Miyakawa
- G11 - INFORMATION STORAGE
Information Patent Grant
Ferroelectric memory having memory cell array accessibility safeguards
- Patent number 6,510,071
- Issue date Jan 21, 2003
- Kabushiki Kaisha Toshiba
- Yukihito Oowaki
- G11 - INFORMATION STORAGE
Information Patent Grant
Ferroelectric memory device
- Patent number 6,483,737
- Issue date Nov 19, 2002
- Kabushiki Kaisha Toshiba
- Yoshiaki Takeuchi
- G11 - INFORMATION STORAGE
Information Patent Grant
Apparatus comprising clock control circuit, method of controlling c...
- Patent number 6,473,865
- Issue date Oct 29, 2002
- Kabushiki Kaisha Toshiba
- Masahiro Kamoshida
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Chain type ferroelectric memory with isolation transistors coupled...
- Patent number 6,473,330
- Issue date Oct 29, 2002
- Kabushiki Kaisha Toshiba
- Ryu Ogiwara
- G11 - INFORMATION STORAGE
Information Patent Grant
Random access memory with divided memory banks and data read/write...
- Patent number 6,404,696
- Issue date Jun 11, 2002
- Kabushiki Kaisha Toshiba
- Yukihito Oowaki
- G11 - INFORMATION STORAGE
Information Patent Grant
Semiconductor integrated circuit
- Patent number 6,392,467
- Issue date May 21, 2002
- Toshiba Corporation
- Yukihito Oowaki
- G05 - CONTROLLING REGULATING
Information Patent Grant
Apparatus comprising clock control circuit and device using interna...
- Patent number 6,393,080
- Issue date May 21, 2002
- Kabushiki Kaisha Toshiba
- Masahiro Kamoshida
- G11 - INFORMATION STORAGE
Information Patent Grant
Clock control circuit
- Patent number 6,388,484
- Issue date May 14, 2002
- Kabushiki Kaisha Toshiba
- Masahiro Kamoshida
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Semiconductor memory device using ferroelectric film
- Patent number 6,366,490
- Issue date Apr 2, 2002
- Kabushiki Kaisha Toshiba
- Yoshiaki Takeuchi
- G11 - INFORMATION STORAGE
Information Patent Grant
Configurable integrated circuit and method of testing the same
- Patent number 6,349,395
- Issue date Feb 19, 2002
- Kabushiki Kaisha Toshiba
- Kazunori Ohuchi
- G01 - MEASURING TESTING
Information Patent Grant
Method of manufacturing semiconductor memory device
- Patent number 6,342,408
- Issue date Jan 29, 2002
- Kabushiki Kaisha Toshiba
- Yukihito Oowaki
- G11 - INFORMATION STORAGE
Information Patent Grant
Semiconductor integrated circuit for cryptographic process and encr...
- Patent number 6,327,654
- Issue date Dec 4, 2001
- Kabushiki Kaisha Toshiba
- Yukihito Oowaki
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
MISFET semiconductor device having relative impurity concentration...
- Patent number 6,323,525
- Issue date Nov 27, 2001
- Kabushiki Kaisha Toshiba
- Mitsuhiro Noguchi
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
SEMICONDUCTOR DEVICE AND METHOD OF DESIGNING A WIRING OF A SEMICOND...
- Publication number 20120025377
- Publication date Feb 2, 2012
- Kabushiki Kaisha Toshiba
- Shoji Seta
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Ferroelectric Memory and Semiconductor Memory
- Publication number 20080285327
- Publication date Nov 20, 2008
- KABUSHIKI KAISHA TOSHIBA
- Ryu Ogiwara
- G11 - INFORMATION STORAGE
Information Patent Application
Semiconductor device and system
- Publication number 20060271799
- Publication date Nov 30, 2006
- Kabushiki Kaisha Toshiba
- Shinichiro Shiratake
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Ferroelectric Memory and Semiconductor Memory
- Publication number 20060193162
- Publication date Aug 31, 2006
- KABUSHIKI KAISHA TOSHIBA
- Ryu Ogiwara
- G11 - INFORMATION STORAGE
Information Patent Application
Semiconductor device adapted to minimize clock skew
- Publication number 20060061401
- Publication date Mar 23, 2006
- Shinichiro Shiratake
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Ferroelectric memory and semiconductor memory
- Publication number 20040136225
- Publication date Jul 15, 2004
- KABUSHIKI KAISHA TOSHIBA
- Ryu Ogiwara
- G11 - INFORMATION STORAGE
Information Patent Application
Ferroelectric memory
- Publication number 20040062115
- Publication date Apr 1, 2004
- KABUSHIKI KAISHA TOSHIBA
- Yoshiaki Takeuchi
- G11 - INFORMATION STORAGE
Information Patent Application
Ferroelectric memory and semiconductor memory
- Publication number 20030128572
- Publication date Jul 10, 2003
- KABUSHIKI KAISHA TOSHIBA
- Ryu Ogiwara
- G11 - INFORMATION STORAGE
Information Patent Application
Ferroelectric memory and semiconductor memory
- Publication number 20020196656
- Publication date Dec 26, 2002
- KABUSHIKI KAISHA TOSHIBA
- Ryu Ogiwara
- G11 - INFORMATION STORAGE
Information Patent Application
Series connected TC unit type ferroelectric RAM and test method the...
- Publication number 20020188893
- Publication date Dec 12, 2002
- KABUSHIKI KAISHA TOSHIBA
- Ryu Ogiwara
- G11 - INFORMATION STORAGE
Information Patent Application
Ferroelectric random access memory
- Publication number 20020122328
- Publication date Sep 5, 2002
- Kabushiki Kaisha Toshiba
- Yukihito Oowaki
- G11 - INFORMATION STORAGE
Information Patent Application
MIS transistor having a large driving current and method for produc...
- Publication number 20020117725
- Publication date Aug 29, 2002
- Kabushiki Kaisha Toshiba
- Yukihito Oowaki
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Random access memory with divided memory banks and data read/write...
- Publication number 20020089891
- Publication date Jul 11, 2002
- Yukihito Oowaki
- G11 - INFORMATION STORAGE
Information Patent Application
Semiconductor memory device
- Publication number 20020056878
- Publication date May 16, 2002
- Yukihito Oowaki
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Ferroelectric memory device
- Publication number 20020044477
- Publication date Apr 18, 2002
- Yoshiaki Takeuchi
- G11 - INFORMATION STORAGE
Information Patent Application
Semiconductor memory device
- Publication number 20020034091
- Publication date Mar 21, 2002
- Tadashi Miyakawa
- G11 - INFORMATION STORAGE
Information Patent Application
RANDOM ACCESS MEMORY WITH DIVIDED MEMORY BANKS AND DATA READ/WRITE...
- Publication number 20020031037
- Publication date Mar 14, 2002
- Yukihito Oowaki
- G11 - INFORMATION STORAGE
Information Patent Application
SEMICONDUCTOR MEMORY DEVICE USING FERROELECTRIC FILM
- Publication number 20020024838
- Publication date Feb 28, 2002
- Yoshiaki Takeuchi
- G11 - INFORMATION STORAGE
Information Patent Application
CONFIGURABLE INTEGRATED CIRCUIT AND METHOD OF TESTING THE SAME
- Publication number 20020010885
- Publication date Jan 24, 2002
- KAZUNORI OHUCHI
- G01 - MEASURING TESTING
Information Patent Application
MIS transistor and method for producing same
- Publication number 20010030350
- Publication date Oct 18, 2001
- KABUSHIKI KAISHA TOSHIBA
- Yukihito Oowaki
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Ferroelectric memory
- Publication number 20010022741
- Publication date Sep 20, 2001
- Yoshiaki Takeuchi
- G11 - INFORMATION STORAGE
Information Patent Application
Ferroelectric memory
- Publication number 20010021120
- Publication date Sep 13, 2001
- Yukihito Oowaki
- G11 - INFORMATION STORAGE

YUKIHITO OOWAKI

Person

Patents Grantslast 30 patents

Semiconductor device and method of designing a wiring of a semicond...

Semiconductor device and system

MIS transistor and method for producing same

Chain ferroelectric random access memory (CFRAM) having an intrinsi...

Semiconductor device adapted to minimize clock skew

Ferroelectric memory with an intrinsic access transistor coupled to...

Series connected TC unit type ferroelectric RAM and test method the...

Ferroelectric memory

MIS transistor having a large driving current and method for produc...

Ferroelectric random access memory with isolation transistors coupl...

Ferroelectric memory having a device responsive to current lowering

Ferroelectric random access memory

Chain-type ferroelectric random access memory (FRAM) with rewrite t...

Semiconductor memory device including a pair of MOS transistors for...

Random access memory with divided memory banks and data read/write...

Semiconductor apparatus and mode setting method for semiconductor a...

Semiconductor memory device

Ferroelectric memory having memory cell array accessibility safeguards

Ferroelectric memory device

Apparatus comprising clock control circuit, method of controlling c...

Chain type ferroelectric memory with isolation transistors coupled...

Random access memory with divided memory banks and data read/write...

Semiconductor integrated circuit

Apparatus comprising clock control circuit and device using interna...

Clock control circuit

Semiconductor memory device using ferroelectric film

Configurable integrated circuit and method of testing the same

Method of manufacturing semiconductor memory device

Semiconductor integrated circuit for cryptographic process and encr...

MISFET semiconductor device having relative impurity concentration...

Patents Applicationslast 30 patents

SEMICONDUCTOR DEVICE AND METHOD OF DESIGNING A WIRING OF A SEMICOND...

Ferroelectric Memory and Semiconductor Memory

Semiconductor device and system

Ferroelectric Memory and Semiconductor Memory

Semiconductor device adapted to minimize clock skew

Ferroelectric memory and semiconductor memory

Ferroelectric memory

Ferroelectric memory and semiconductor memory

Ferroelectric memory and semiconductor memory

Series connected TC unit type ferroelectric RAM and test method the...

Ferroelectric random access memory

MIS transistor having a large driving current and method for produc...

Random access memory with divided memory banks and data read/write...

Semiconductor memory device

Ferroelectric memory device

Semiconductor memory device

RANDOM ACCESS MEMORY WITH DIVIDED MEMORY BANKS AND DATA READ/WRITE...

SEMICONDUCTOR MEMORY DEVICE USING FERROELECTRIC FILM

CONFIGURABLE INTEGRATED CIRCUIT AND METHOD OF TESTING THE SAME

MIS transistor and method for producing same

Ferroelectric memory

Ferroelectric memory